1 #include <linux/bitops.h> 2 #include <linux/types.h> 3 #include <linux/slab.h> 4 5 #include <asm/perf_event.h> 6 #include <asm/insn.h> 7 8 #include "../perf_event.h" 9 10 /* The size of a BTS record in bytes: */ 11 #define BTS_RECORD_SIZE 24 12 13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) 15 #define PEBS_FIXUP_SIZE PAGE_SIZE 16 17 /* 18 * pebs_record_32 for p4 and core not supported 19 20 struct pebs_record_32 { 21 u32 flags, ip; 22 u32 ax, bc, cx, dx; 23 u32 si, di, bp, sp; 24 }; 25 26 */ 27 28 union intel_x86_pebs_dse { 29 u64 val; 30 struct { 31 unsigned int ld_dse:4; 32 unsigned int ld_stlb_miss:1; 33 unsigned int ld_locked:1; 34 unsigned int ld_reserved:26; 35 }; 36 struct { 37 unsigned int st_l1d_hit:1; 38 unsigned int st_reserved1:3; 39 unsigned int st_stlb_miss:1; 40 unsigned int st_locked:1; 41 unsigned int st_reserved2:26; 42 }; 43 }; 44 45 46 /* 47 * Map PEBS Load Latency Data Source encodings to generic 48 * memory data source information 49 */ 50 #define P(a, b) PERF_MEM_S(a, b) 51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) 52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) 53 54 /* Version for Sandy Bridge and later */ 55 static u64 pebs_data_source[] = { 56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ 57 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */ 58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ 59 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ 60 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ 61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ 62 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ 63 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ 64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ 65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ 66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ 67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ 68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */ 69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */ 70 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */ 71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */ 72 }; 73 74 /* Patch up minor differences in the bits */ 75 void __init intel_pmu_pebs_data_source_nhm(void) 76 { 77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); 78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); 79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); 80 } 81 82 static u64 precise_store_data(u64 status) 83 { 84 union intel_x86_pebs_dse dse; 85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); 86 87 dse.val = status; 88 89 /* 90 * bit 4: TLB access 91 * 1 = stored missed 2nd level TLB 92 * 93 * so it either hit the walker or the OS 94 * otherwise hit 2nd level TLB 95 */ 96 if (dse.st_stlb_miss) 97 val |= P(TLB, MISS); 98 else 99 val |= P(TLB, HIT); 100 101 /* 102 * bit 0: hit L1 data cache 103 * if not set, then all we know is that 104 * it missed L1D 105 */ 106 if (dse.st_l1d_hit) 107 val |= P(LVL, HIT); 108 else 109 val |= P(LVL, MISS); 110 111 /* 112 * bit 5: Locked prefix 113 */ 114 if (dse.st_locked) 115 val |= P(LOCK, LOCKED); 116 117 return val; 118 } 119 120 static u64 precise_datala_hsw(struct perf_event *event, u64 status) 121 { 122 union perf_mem_data_src dse; 123 124 dse.val = PERF_MEM_NA; 125 126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) 127 dse.mem_op = PERF_MEM_OP_STORE; 128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) 129 dse.mem_op = PERF_MEM_OP_LOAD; 130 131 /* 132 * L1 info only valid for following events: 133 * 134 * MEM_UOPS_RETIRED.STLB_MISS_STORES 135 * MEM_UOPS_RETIRED.LOCK_STORES 136 * MEM_UOPS_RETIRED.SPLIT_STORES 137 * MEM_UOPS_RETIRED.ALL_STORES 138 */ 139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { 140 if (status & 1) 141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; 142 else 143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; 144 } 145 return dse.val; 146 } 147 148 static u64 load_latency_data(u64 status) 149 { 150 union intel_x86_pebs_dse dse; 151 u64 val; 152 int model = boot_cpu_data.x86_model; 153 int fam = boot_cpu_data.x86; 154 155 dse.val = status; 156 157 /* 158 * use the mapping table for bit 0-3 159 */ 160 val = pebs_data_source[dse.ld_dse]; 161 162 /* 163 * Nehalem models do not support TLB, Lock infos 164 */ 165 if (fam == 0x6 && (model == 26 || model == 30 166 || model == 31 || model == 46)) { 167 val |= P(TLB, NA) | P(LOCK, NA); 168 return val; 169 } 170 /* 171 * bit 4: TLB access 172 * 0 = did not miss 2nd level TLB 173 * 1 = missed 2nd level TLB 174 */ 175 if (dse.ld_stlb_miss) 176 val |= P(TLB, MISS) | P(TLB, L2); 177 else 178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); 179 180 /* 181 * bit 5: locked prefix 182 */ 183 if (dse.ld_locked) 184 val |= P(LOCK, LOCKED); 185 186 return val; 187 } 188 189 struct pebs_record_core { 190 u64 flags, ip; 191 u64 ax, bx, cx, dx; 192 u64 si, di, bp, sp; 193 u64 r8, r9, r10, r11; 194 u64 r12, r13, r14, r15; 195 }; 196 197 struct pebs_record_nhm { 198 u64 flags, ip; 199 u64 ax, bx, cx, dx; 200 u64 si, di, bp, sp; 201 u64 r8, r9, r10, r11; 202 u64 r12, r13, r14, r15; 203 u64 status, dla, dse, lat; 204 }; 205 206 /* 207 * Same as pebs_record_nhm, with two additional fields. 208 */ 209 struct pebs_record_hsw { 210 u64 flags, ip; 211 u64 ax, bx, cx, dx; 212 u64 si, di, bp, sp; 213 u64 r8, r9, r10, r11; 214 u64 r12, r13, r14, r15; 215 u64 status, dla, dse, lat; 216 u64 real_ip, tsx_tuning; 217 }; 218 219 union hsw_tsx_tuning { 220 struct { 221 u32 cycles_last_block : 32, 222 hle_abort : 1, 223 rtm_abort : 1, 224 instruction_abort : 1, 225 non_instruction_abort : 1, 226 retry : 1, 227 data_conflict : 1, 228 capacity_writes : 1, 229 capacity_reads : 1; 230 }; 231 u64 value; 232 }; 233 234 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL 235 236 /* Same as HSW, plus TSC */ 237 238 struct pebs_record_skl { 239 u64 flags, ip; 240 u64 ax, bx, cx, dx; 241 u64 si, di, bp, sp; 242 u64 r8, r9, r10, r11; 243 u64 r12, r13, r14, r15; 244 u64 status, dla, dse, lat; 245 u64 real_ip, tsx_tuning; 246 u64 tsc; 247 }; 248 249 void init_debug_store_on_cpu(int cpu) 250 { 251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 252 253 if (!ds) 254 return; 255 256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 257 (u32)((u64)(unsigned long)ds), 258 (u32)((u64)(unsigned long)ds >> 32)); 259 } 260 261 void fini_debug_store_on_cpu(int cpu) 262 { 263 if (!per_cpu(cpu_hw_events, cpu).ds) 264 return; 265 266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); 267 } 268 269 static DEFINE_PER_CPU(void *, insn_buffer); 270 271 static int alloc_pebs_buffer(int cpu) 272 { 273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 274 int node = cpu_to_node(cpu); 275 int max; 276 void *buffer, *ibuffer; 277 278 if (!x86_pmu.pebs) 279 return 0; 280 281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node); 282 if (unlikely(!buffer)) 283 return -ENOMEM; 284 285 /* 286 * HSW+ already provides us the eventing ip; no need to allocate this 287 * buffer then. 288 */ 289 if (x86_pmu.intel_cap.pebs_format < 2) { 290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); 291 if (!ibuffer) { 292 kfree(buffer); 293 return -ENOMEM; 294 } 295 per_cpu(insn_buffer, cpu) = ibuffer; 296 } 297 298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size; 299 300 ds->pebs_buffer_base = (u64)(unsigned long)buffer; 301 ds->pebs_index = ds->pebs_buffer_base; 302 ds->pebs_absolute_maximum = ds->pebs_buffer_base + 303 max * x86_pmu.pebs_record_size; 304 305 return 0; 306 } 307 308 static void release_pebs_buffer(int cpu) 309 { 310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 311 312 if (!ds || !x86_pmu.pebs) 313 return; 314 315 kfree(per_cpu(insn_buffer, cpu)); 316 per_cpu(insn_buffer, cpu) = NULL; 317 318 kfree((void *)(unsigned long)ds->pebs_buffer_base); 319 ds->pebs_buffer_base = 0; 320 } 321 322 static int alloc_bts_buffer(int cpu) 323 { 324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 325 int node = cpu_to_node(cpu); 326 int max, thresh; 327 void *buffer; 328 329 if (!x86_pmu.bts) 330 return 0; 331 332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node); 333 if (unlikely(!buffer)) { 334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); 335 return -ENOMEM; 336 } 337 338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; 339 thresh = max / 16; 340 341 ds->bts_buffer_base = (u64)(unsigned long)buffer; 342 ds->bts_index = ds->bts_buffer_base; 343 ds->bts_absolute_maximum = ds->bts_buffer_base + 344 max * BTS_RECORD_SIZE; 345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - 346 thresh * BTS_RECORD_SIZE; 347 348 return 0; 349 } 350 351 static void release_bts_buffer(int cpu) 352 { 353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 354 355 if (!ds || !x86_pmu.bts) 356 return; 357 358 kfree((void *)(unsigned long)ds->bts_buffer_base); 359 ds->bts_buffer_base = 0; 360 } 361 362 static int alloc_ds_buffer(int cpu) 363 { 364 int node = cpu_to_node(cpu); 365 struct debug_store *ds; 366 367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node); 368 if (unlikely(!ds)) 369 return -ENOMEM; 370 371 per_cpu(cpu_hw_events, cpu).ds = ds; 372 373 return 0; 374 } 375 376 static void release_ds_buffer(int cpu) 377 { 378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; 379 380 if (!ds) 381 return; 382 383 per_cpu(cpu_hw_events, cpu).ds = NULL; 384 kfree(ds); 385 } 386 387 void release_ds_buffers(void) 388 { 389 int cpu; 390 391 if (!x86_pmu.bts && !x86_pmu.pebs) 392 return; 393 394 get_online_cpus(); 395 for_each_online_cpu(cpu) 396 fini_debug_store_on_cpu(cpu); 397 398 for_each_possible_cpu(cpu) { 399 release_pebs_buffer(cpu); 400 release_bts_buffer(cpu); 401 release_ds_buffer(cpu); 402 } 403 put_online_cpus(); 404 } 405 406 void reserve_ds_buffers(void) 407 { 408 int bts_err = 0, pebs_err = 0; 409 int cpu; 410 411 x86_pmu.bts_active = 0; 412 x86_pmu.pebs_active = 0; 413 414 if (!x86_pmu.bts && !x86_pmu.pebs) 415 return; 416 417 if (!x86_pmu.bts) 418 bts_err = 1; 419 420 if (!x86_pmu.pebs) 421 pebs_err = 1; 422 423 get_online_cpus(); 424 425 for_each_possible_cpu(cpu) { 426 if (alloc_ds_buffer(cpu)) { 427 bts_err = 1; 428 pebs_err = 1; 429 } 430 431 if (!bts_err && alloc_bts_buffer(cpu)) 432 bts_err = 1; 433 434 if (!pebs_err && alloc_pebs_buffer(cpu)) 435 pebs_err = 1; 436 437 if (bts_err && pebs_err) 438 break; 439 } 440 441 if (bts_err) { 442 for_each_possible_cpu(cpu) 443 release_bts_buffer(cpu); 444 } 445 446 if (pebs_err) { 447 for_each_possible_cpu(cpu) 448 release_pebs_buffer(cpu); 449 } 450 451 if (bts_err && pebs_err) { 452 for_each_possible_cpu(cpu) 453 release_ds_buffer(cpu); 454 } else { 455 if (x86_pmu.bts && !bts_err) 456 x86_pmu.bts_active = 1; 457 458 if (x86_pmu.pebs && !pebs_err) 459 x86_pmu.pebs_active = 1; 460 461 for_each_online_cpu(cpu) 462 init_debug_store_on_cpu(cpu); 463 } 464 465 put_online_cpus(); 466 } 467 468 /* 469 * BTS 470 */ 471 472 struct event_constraint bts_constraint = 473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); 474 475 void intel_pmu_enable_bts(u64 config) 476 { 477 unsigned long debugctlmsr; 478 479 debugctlmsr = get_debugctlmsr(); 480 481 debugctlmsr |= DEBUGCTLMSR_TR; 482 debugctlmsr |= DEBUGCTLMSR_BTS; 483 if (config & ARCH_PERFMON_EVENTSEL_INT) 484 debugctlmsr |= DEBUGCTLMSR_BTINT; 485 486 if (!(config & ARCH_PERFMON_EVENTSEL_OS)) 487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; 488 489 if (!(config & ARCH_PERFMON_EVENTSEL_USR)) 490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; 491 492 update_debugctlmsr(debugctlmsr); 493 } 494 495 void intel_pmu_disable_bts(void) 496 { 497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 498 unsigned long debugctlmsr; 499 500 if (!cpuc->ds) 501 return; 502 503 debugctlmsr = get_debugctlmsr(); 504 505 debugctlmsr &= 506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | 507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); 508 509 update_debugctlmsr(debugctlmsr); 510 } 511 512 int intel_pmu_drain_bts_buffer(void) 513 { 514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 515 struct debug_store *ds = cpuc->ds; 516 struct bts_record { 517 u64 from; 518 u64 to; 519 u64 flags; 520 }; 521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; 522 struct bts_record *at, *base, *top; 523 struct perf_output_handle handle; 524 struct perf_event_header header; 525 struct perf_sample_data data; 526 unsigned long skip = 0; 527 struct pt_regs regs; 528 529 if (!event) 530 return 0; 531 532 if (!x86_pmu.bts_active) 533 return 0; 534 535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; 536 top = (struct bts_record *)(unsigned long)ds->bts_index; 537 538 if (top <= base) 539 return 0; 540 541 memset(®s, 0, sizeof(regs)); 542 543 ds->bts_index = ds->bts_buffer_base; 544 545 perf_sample_data_init(&data, 0, event->hw.last_period); 546 547 /* 548 * BTS leaks kernel addresses in branches across the cpl boundary, 549 * such as traps or system calls, so unless the user is asking for 550 * kernel tracing (and right now it's not possible), we'd need to 551 * filter them out. But first we need to count how many of those we 552 * have in the current batch. This is an extra O(n) pass, however, 553 * it's much faster than the other one especially considering that 554 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the 555 * alloc_bts_buffer()). 556 */ 557 for (at = base; at < top; at++) { 558 /* 559 * Note that right now *this* BTS code only works if 560 * attr::exclude_kernel is set, but let's keep this extra 561 * check here in case that changes. 562 */ 563 if (event->attr.exclude_kernel && 564 (kernel_ip(at->from) || kernel_ip(at->to))) 565 skip++; 566 } 567 568 /* 569 * Prepare a generic sample, i.e. fill in the invariant fields. 570 * We will overwrite the from and to address before we output 571 * the sample. 572 */ 573 perf_prepare_sample(&header, &data, event, ®s); 574 575 if (perf_output_begin(&handle, event, header.size * 576 (top - base - skip))) 577 return 1; 578 579 for (at = base; at < top; at++) { 580 /* Filter out any records that contain kernel addresses. */ 581 if (event->attr.exclude_kernel && 582 (kernel_ip(at->from) || kernel_ip(at->to))) 583 continue; 584 585 data.ip = at->from; 586 data.addr = at->to; 587 588 perf_output_sample(&handle, &header, &data, event); 589 } 590 591 perf_output_end(&handle); 592 593 /* There's new data available. */ 594 event->hw.interrupts++; 595 event->pending_kill = POLL_IN; 596 return 1; 597 } 598 599 static inline void intel_pmu_drain_pebs_buffer(void) 600 { 601 struct pt_regs regs; 602 603 x86_pmu.drain_pebs(®s); 604 } 605 606 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) 607 { 608 if (!sched_in) 609 intel_pmu_drain_pebs_buffer(); 610 } 611 612 /* 613 * PEBS 614 */ 615 struct event_constraint intel_core2_pebs_event_constraints[] = { 616 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 617 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ 618 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ 619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ 620 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 621 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 622 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 623 EVENT_CONSTRAINT_END 624 }; 625 626 struct event_constraint intel_atom_pebs_event_constraints[] = { 627 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ 628 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ 629 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ 630 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 631 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), 632 /* Allow all events as PEBS with no flags */ 633 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 634 EVENT_CONSTRAINT_END 635 }; 636 637 struct event_constraint intel_slm_pebs_event_constraints[] = { 638 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 639 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), 640 /* Allow all events as PEBS with no flags */ 641 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 642 EVENT_CONSTRAINT_END 643 }; 644 645 struct event_constraint intel_nehalem_pebs_event_constraints[] = { 646 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 647 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 648 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 649 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ 650 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 651 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 652 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ 653 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 654 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 655 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 656 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 657 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 658 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 659 EVENT_CONSTRAINT_END 660 }; 661 662 struct event_constraint intel_westmere_pebs_event_constraints[] = { 663 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ 664 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ 665 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ 666 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ 667 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ 668 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ 669 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ 670 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ 671 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ 672 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ 673 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ 674 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ 675 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 676 EVENT_CONSTRAINT_END 677 }; 678 679 struct event_constraint intel_snb_pebs_event_constraints[] = { 680 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 681 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 682 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 683 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 684 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 685 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 686 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 687 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 688 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 689 /* Allow all events as PEBS with no flags */ 690 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 691 EVENT_CONSTRAINT_END 692 }; 693 694 struct event_constraint intel_ivb_pebs_event_constraints[] = { 695 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 696 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ 697 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 698 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 699 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 700 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 701 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 702 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 703 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 704 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 705 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ 706 /* Allow all events as PEBS with no flags */ 707 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 708 EVENT_CONSTRAINT_END 709 }; 710 711 struct event_constraint intel_hsw_pebs_event_constraints[] = { 712 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 713 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 714 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 715 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 716 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 717 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 718 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 719 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 720 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 721 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 722 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 723 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 724 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 725 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 726 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 727 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 728 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 729 /* Allow all events as PEBS with no flags */ 730 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 731 EVENT_CONSTRAINT_END 732 }; 733 734 struct event_constraint intel_bdw_pebs_event_constraints[] = { 735 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ 736 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ 737 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 738 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 739 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 740 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 741 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 742 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 743 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 744 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 745 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 746 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 747 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 748 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 749 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 750 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 751 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 752 /* Allow all events as PEBS with no flags */ 753 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 754 EVENT_CONSTRAINT_END 755 }; 756 757 758 struct event_constraint intel_skl_pebs_event_constraints[] = { 759 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 760 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ 761 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), 762 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ 763 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), 764 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ 765 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ 766 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ 767 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ 768 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ 769 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ 770 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ 771 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ 772 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ 773 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 774 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 775 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ 776 /* Allow all events as PEBS with no flags */ 777 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 778 EVENT_CONSTRAINT_END 779 }; 780 781 struct event_constraint *intel_pebs_constraints(struct perf_event *event) 782 { 783 struct event_constraint *c; 784 785 if (!event->attr.precise_ip) 786 return NULL; 787 788 if (x86_pmu.pebs_constraints) { 789 for_each_event_constraint(c, x86_pmu.pebs_constraints) { 790 if ((event->hw.config & c->cmask) == c->code) { 791 event->hw.flags |= c->flags; 792 return c; 793 } 794 } 795 } 796 797 return &emptyconstraint; 798 } 799 800 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc) 801 { 802 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1)); 803 } 804 805 void intel_pmu_pebs_enable(struct perf_event *event) 806 { 807 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 808 struct hw_perf_event *hwc = &event->hw; 809 struct debug_store *ds = cpuc->ds; 810 bool first_pebs; 811 u64 threshold; 812 813 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; 814 815 first_pebs = !pebs_is_enabled(cpuc); 816 cpuc->pebs_enabled |= 1ULL << hwc->idx; 817 818 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 819 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); 820 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 821 cpuc->pebs_enabled |= 1ULL << 63; 822 823 /* 824 * When the event is constrained enough we can use a larger 825 * threshold and run the event with less frequent PMI. 826 */ 827 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) { 828 threshold = ds->pebs_absolute_maximum - 829 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size; 830 831 if (first_pebs) 832 perf_sched_cb_inc(event->ctx->pmu); 833 } else { 834 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; 835 836 /* 837 * If not all events can use larger buffer, 838 * roll back to threshold = 1 839 */ 840 if (!first_pebs && 841 (ds->pebs_interrupt_threshold > threshold)) 842 perf_sched_cb_dec(event->ctx->pmu); 843 } 844 845 /* Use auto-reload if possible to save a MSR write in the PMI */ 846 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 847 ds->pebs_event_reset[hwc->idx] = 848 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 849 } 850 851 if (first_pebs || ds->pebs_interrupt_threshold > threshold) 852 ds->pebs_interrupt_threshold = threshold; 853 } 854 855 void intel_pmu_pebs_disable(struct perf_event *event) 856 { 857 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 858 struct hw_perf_event *hwc = &event->hw; 859 struct debug_store *ds = cpuc->ds; 860 bool large_pebs = ds->pebs_interrupt_threshold > 861 ds->pebs_buffer_base + x86_pmu.pebs_record_size; 862 863 if (large_pebs) 864 intel_pmu_drain_pebs_buffer(); 865 866 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); 867 868 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) 869 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); 870 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) 871 cpuc->pebs_enabled &= ~(1ULL << 63); 872 873 if (large_pebs && !pebs_is_enabled(cpuc)) 874 perf_sched_cb_dec(event->ctx->pmu); 875 876 if (cpuc->enabled) 877 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 878 879 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 880 } 881 882 void intel_pmu_pebs_enable_all(void) 883 { 884 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 885 886 if (cpuc->pebs_enabled) 887 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 888 } 889 890 void intel_pmu_pebs_disable_all(void) 891 { 892 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 893 894 if (cpuc->pebs_enabled) 895 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 896 } 897 898 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) 899 { 900 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 901 unsigned long from = cpuc->lbr_entries[0].from; 902 unsigned long old_to, to = cpuc->lbr_entries[0].to; 903 unsigned long ip = regs->ip; 904 int is_64bit = 0; 905 void *kaddr; 906 int size; 907 908 /* 909 * We don't need to fixup if the PEBS assist is fault like 910 */ 911 if (!x86_pmu.intel_cap.pebs_trap) 912 return 1; 913 914 /* 915 * No LBR entry, no basic block, no rewinding 916 */ 917 if (!cpuc->lbr_stack.nr || !from || !to) 918 return 0; 919 920 /* 921 * Basic blocks should never cross user/kernel boundaries 922 */ 923 if (kernel_ip(ip) != kernel_ip(to)) 924 return 0; 925 926 /* 927 * unsigned math, either ip is before the start (impossible) or 928 * the basic block is larger than 1 page (sanity) 929 */ 930 if ((ip - to) > PEBS_FIXUP_SIZE) 931 return 0; 932 933 /* 934 * We sampled a branch insn, rewind using the LBR stack 935 */ 936 if (ip == to) { 937 set_linear_ip(regs, from); 938 return 1; 939 } 940 941 size = ip - to; 942 if (!kernel_ip(ip)) { 943 int bytes; 944 u8 *buf = this_cpu_read(insn_buffer); 945 946 /* 'size' must fit our buffer, see above */ 947 bytes = copy_from_user_nmi(buf, (void __user *)to, size); 948 if (bytes != 0) 949 return 0; 950 951 kaddr = buf; 952 } else { 953 kaddr = (void *)to; 954 } 955 956 do { 957 struct insn insn; 958 959 old_to = to; 960 961 #ifdef CONFIG_X86_64 962 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); 963 #endif 964 insn_init(&insn, kaddr, size, is_64bit); 965 insn_get_length(&insn); 966 /* 967 * Make sure there was not a problem decoding the 968 * instruction and getting the length. This is 969 * doubly important because we have an infinite 970 * loop if insn.length=0. 971 */ 972 if (!insn.length) 973 break; 974 975 to += insn.length; 976 kaddr += insn.length; 977 size -= insn.length; 978 } while (to < ip); 979 980 if (to == ip) { 981 set_linear_ip(regs, old_to); 982 return 1; 983 } 984 985 /* 986 * Even though we decoded the basic block, the instruction stream 987 * never matched the given IP, either the TO or the IP got corrupted. 988 */ 989 return 0; 990 } 991 992 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs) 993 { 994 if (pebs->tsx_tuning) { 995 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; 996 return tsx.cycles_last_block; 997 } 998 return 0; 999 } 1000 1001 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs) 1002 { 1003 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; 1004 1005 /* For RTM XABORTs also log the abort code from AX */ 1006 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) 1007 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; 1008 return txn; 1009 } 1010 1011 static void setup_pebs_sample_data(struct perf_event *event, 1012 struct pt_regs *iregs, void *__pebs, 1013 struct perf_sample_data *data, 1014 struct pt_regs *regs) 1015 { 1016 #define PERF_X86_EVENT_PEBS_HSW_PREC \ 1017 (PERF_X86_EVENT_PEBS_ST_HSW | \ 1018 PERF_X86_EVENT_PEBS_LD_HSW | \ 1019 PERF_X86_EVENT_PEBS_NA_HSW) 1020 /* 1021 * We cast to the biggest pebs_record but are careful not to 1022 * unconditionally access the 'extra' entries. 1023 */ 1024 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1025 struct pebs_record_skl *pebs = __pebs; 1026 u64 sample_type; 1027 int fll, fst, dsrc; 1028 int fl = event->hw.flags; 1029 1030 if (pebs == NULL) 1031 return; 1032 1033 sample_type = event->attr.sample_type; 1034 dsrc = sample_type & PERF_SAMPLE_DATA_SRC; 1035 1036 fll = fl & PERF_X86_EVENT_PEBS_LDLAT; 1037 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); 1038 1039 perf_sample_data_init(data, 0, event->hw.last_period); 1040 1041 data->period = event->hw.last_period; 1042 1043 /* 1044 * Use latency for weight (only avail with PEBS-LL) 1045 */ 1046 if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) 1047 data->weight = pebs->lat; 1048 1049 /* 1050 * data.data_src encodes the data source 1051 */ 1052 if (dsrc) { 1053 u64 val = PERF_MEM_NA; 1054 if (fll) 1055 val = load_latency_data(pebs->dse); 1056 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) 1057 val = precise_datala_hsw(event, pebs->dse); 1058 else if (fst) 1059 val = precise_store_data(pebs->dse); 1060 data->data_src.val = val; 1061 } 1062 1063 /* 1064 * We use the interrupt regs as a base because the PEBS record 1065 * does not contain a full regs set, specifically it seems to 1066 * lack segment descriptors, which get used by things like 1067 * user_mode(). 1068 * 1069 * In the simple case fix up only the IP and BP,SP regs, for 1070 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly. 1071 * A possible PERF_SAMPLE_REGS will have to transfer all regs. 1072 */ 1073 *regs = *iregs; 1074 regs->flags = pebs->flags; 1075 set_linear_ip(regs, pebs->ip); 1076 regs->bp = pebs->bp; 1077 regs->sp = pebs->sp; 1078 1079 if (sample_type & PERF_SAMPLE_REGS_INTR) { 1080 regs->ax = pebs->ax; 1081 regs->bx = pebs->bx; 1082 regs->cx = pebs->cx; 1083 regs->dx = pebs->dx; 1084 regs->si = pebs->si; 1085 regs->di = pebs->di; 1086 regs->bp = pebs->bp; 1087 regs->sp = pebs->sp; 1088 1089 regs->flags = pebs->flags; 1090 #ifndef CONFIG_X86_32 1091 regs->r8 = pebs->r8; 1092 regs->r9 = pebs->r9; 1093 regs->r10 = pebs->r10; 1094 regs->r11 = pebs->r11; 1095 regs->r12 = pebs->r12; 1096 regs->r13 = pebs->r13; 1097 regs->r14 = pebs->r14; 1098 regs->r15 = pebs->r15; 1099 #endif 1100 } 1101 1102 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) { 1103 regs->ip = pebs->real_ip; 1104 regs->flags |= PERF_EFLAGS_EXACT; 1105 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs)) 1106 regs->flags |= PERF_EFLAGS_EXACT; 1107 else 1108 regs->flags &= ~PERF_EFLAGS_EXACT; 1109 1110 if ((sample_type & PERF_SAMPLE_ADDR) && 1111 x86_pmu.intel_cap.pebs_format >= 1) 1112 data->addr = pebs->dla; 1113 1114 if (x86_pmu.intel_cap.pebs_format >= 2) { 1115 /* Only set the TSX weight when no memory weight. */ 1116 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) 1117 data->weight = intel_hsw_weight(pebs); 1118 1119 if (sample_type & PERF_SAMPLE_TRANSACTION) 1120 data->txn = intel_hsw_transaction(pebs); 1121 } 1122 1123 /* 1124 * v3 supplies an accurate time stamp, so we use that 1125 * for the time stamp. 1126 * 1127 * We can only do this for the default trace clock. 1128 */ 1129 if (x86_pmu.intel_cap.pebs_format >= 3 && 1130 event->attr.use_clockid == 0) 1131 data->time = native_sched_clock_from_tsc(pebs->tsc); 1132 1133 if (has_branch_stack(event)) 1134 data->br_stack = &cpuc->lbr_stack; 1135 } 1136 1137 static inline void * 1138 get_next_pebs_record_by_bit(void *base, void *top, int bit) 1139 { 1140 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1141 void *at; 1142 u64 pebs_status; 1143 1144 /* 1145 * fmt0 does not have a status bitfield (does not use 1146 * perf_record_nhm format) 1147 */ 1148 if (x86_pmu.intel_cap.pebs_format < 1) 1149 return base; 1150 1151 if (base == NULL) 1152 return NULL; 1153 1154 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1155 struct pebs_record_nhm *p = at; 1156 1157 if (test_bit(bit, (unsigned long *)&p->status)) { 1158 /* PEBS v3 has accurate status bits */ 1159 if (x86_pmu.intel_cap.pebs_format >= 3) 1160 return at; 1161 1162 if (p->status == (1 << bit)) 1163 return at; 1164 1165 /* clear non-PEBS bit and re-check */ 1166 pebs_status = p->status & cpuc->pebs_enabled; 1167 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; 1168 if (pebs_status == (1 << bit)) 1169 return at; 1170 } 1171 } 1172 return NULL; 1173 } 1174 1175 static void __intel_pmu_pebs_event(struct perf_event *event, 1176 struct pt_regs *iregs, 1177 void *base, void *top, 1178 int bit, int count) 1179 { 1180 struct perf_sample_data data; 1181 struct pt_regs regs; 1182 void *at = get_next_pebs_record_by_bit(base, top, bit); 1183 1184 if (!intel_pmu_save_and_restart(event) && 1185 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)) 1186 return; 1187 1188 while (count > 1) { 1189 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1190 perf_event_output(event, &data, ®s); 1191 at += x86_pmu.pebs_record_size; 1192 at = get_next_pebs_record_by_bit(at, top, bit); 1193 count--; 1194 } 1195 1196 setup_pebs_sample_data(event, iregs, at, &data, ®s); 1197 1198 /* 1199 * All but the last records are processed. 1200 * The last one is left to be able to call the overflow handler. 1201 */ 1202 if (perf_event_overflow(event, &data, ®s)) { 1203 x86_pmu_stop(event, 0); 1204 return; 1205 } 1206 1207 } 1208 1209 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) 1210 { 1211 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1212 struct debug_store *ds = cpuc->ds; 1213 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ 1214 struct pebs_record_core *at, *top; 1215 int n; 1216 1217 if (!x86_pmu.pebs_active) 1218 return; 1219 1220 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; 1221 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; 1222 1223 /* 1224 * Whatever else happens, drain the thing 1225 */ 1226 ds->pebs_index = ds->pebs_buffer_base; 1227 1228 if (!test_bit(0, cpuc->active_mask)) 1229 return; 1230 1231 WARN_ON_ONCE(!event); 1232 1233 if (!event->attr.precise_ip) 1234 return; 1235 1236 n = top - at; 1237 if (n <= 0) 1238 return; 1239 1240 __intel_pmu_pebs_event(event, iregs, at, top, 0, n); 1241 } 1242 1243 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) 1244 { 1245 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1246 struct debug_store *ds = cpuc->ds; 1247 struct perf_event *event; 1248 void *base, *at, *top; 1249 short counts[MAX_PEBS_EVENTS] = {}; 1250 short error[MAX_PEBS_EVENTS] = {}; 1251 int bit, i; 1252 1253 if (!x86_pmu.pebs_active) 1254 return; 1255 1256 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; 1257 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; 1258 1259 ds->pebs_index = ds->pebs_buffer_base; 1260 1261 if (unlikely(base >= top)) 1262 return; 1263 1264 for (at = base; at < top; at += x86_pmu.pebs_record_size) { 1265 struct pebs_record_nhm *p = at; 1266 u64 pebs_status; 1267 1268 /* PEBS v3 has accurate status bits */ 1269 if (x86_pmu.intel_cap.pebs_format >= 3) { 1270 for_each_set_bit(bit, (unsigned long *)&p->status, 1271 MAX_PEBS_EVENTS) 1272 counts[bit]++; 1273 1274 continue; 1275 } 1276 1277 pebs_status = p->status & cpuc->pebs_enabled; 1278 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1; 1279 1280 /* 1281 * On some CPUs the PEBS status can be zero when PEBS is 1282 * racing with clearing of GLOBAL_STATUS. 1283 * 1284 * Normally we would drop that record, but in the 1285 * case when there is only a single active PEBS event 1286 * we can assume it's for that event. 1287 */ 1288 if (!pebs_status && cpuc->pebs_enabled && 1289 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) 1290 pebs_status = cpuc->pebs_enabled; 1291 1292 bit = find_first_bit((unsigned long *)&pebs_status, 1293 x86_pmu.max_pebs_events); 1294 if (bit >= x86_pmu.max_pebs_events) 1295 continue; 1296 1297 /* 1298 * The PEBS hardware does not deal well with the situation 1299 * when events happen near to each other and multiple bits 1300 * are set. But it should happen rarely. 1301 * 1302 * If these events include one PEBS and multiple non-PEBS 1303 * events, it doesn't impact PEBS record. The record will 1304 * be handled normally. (slow path) 1305 * 1306 * If these events include two or more PEBS events, the 1307 * records for the events can be collapsed into a single 1308 * one, and it's not possible to reconstruct all events 1309 * that caused the PEBS record. It's called collision. 1310 * If collision happened, the record will be dropped. 1311 */ 1312 if (p->status != (1ULL << bit)) { 1313 for_each_set_bit(i, (unsigned long *)&pebs_status, 1314 x86_pmu.max_pebs_events) 1315 error[i]++; 1316 continue; 1317 } 1318 1319 counts[bit]++; 1320 } 1321 1322 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { 1323 if ((counts[bit] == 0) && (error[bit] == 0)) 1324 continue; 1325 1326 event = cpuc->events[bit]; 1327 WARN_ON_ONCE(!event); 1328 WARN_ON_ONCE(!event->attr.precise_ip); 1329 1330 /* log dropped samples number */ 1331 if (error[bit]) 1332 perf_log_lost_samples(event, error[bit]); 1333 1334 if (counts[bit]) { 1335 __intel_pmu_pebs_event(event, iregs, base, 1336 top, bit, counts[bit]); 1337 } 1338 } 1339 } 1340 1341 /* 1342 * BTS, PEBS probe and setup 1343 */ 1344 1345 void __init intel_ds_init(void) 1346 { 1347 /* 1348 * No support for 32bit formats 1349 */ 1350 if (!boot_cpu_has(X86_FEATURE_DTES64)) 1351 return; 1352 1353 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); 1354 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); 1355 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; 1356 if (x86_pmu.pebs) { 1357 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; 1358 int format = x86_pmu.intel_cap.pebs_format; 1359 1360 switch (format) { 1361 case 0: 1362 pr_cont("PEBS fmt0%c, ", pebs_type); 1363 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); 1364 /* 1365 * Using >PAGE_SIZE buffers makes the WRMSR to 1366 * PERF_GLOBAL_CTRL in intel_pmu_enable_all() 1367 * mysteriously hang on Core2. 1368 * 1369 * As a workaround, we don't do this. 1370 */ 1371 x86_pmu.pebs_buffer_size = PAGE_SIZE; 1372 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; 1373 break; 1374 1375 case 1: 1376 pr_cont("PEBS fmt1%c, ", pebs_type); 1377 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); 1378 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1379 break; 1380 1381 case 2: 1382 pr_cont("PEBS fmt2%c, ", pebs_type); 1383 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); 1384 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1385 break; 1386 1387 case 3: 1388 pr_cont("PEBS fmt3%c, ", pebs_type); 1389 x86_pmu.pebs_record_size = 1390 sizeof(struct pebs_record_skl); 1391 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1392 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME; 1393 break; 1394 1395 default: 1396 pr_cont("no PEBS fmt%d%c, ", format, pebs_type); 1397 x86_pmu.pebs = 0; 1398 } 1399 } 1400 } 1401 1402 void perf_restore_debug_store(void) 1403 { 1404 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); 1405 1406 if (!x86_pmu.bts && !x86_pmu.pebs) 1407 return; 1408 1409 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); 1410 } 1411