1 #ifndef __ASM_SH_CLOCK_H 2 #define __ASM_SH_CLOCK_H 3 4 #include <linux/list.h> 5 #include <linux/seq_file.h> 6 #include <linux/cpufreq.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 10 struct clk; 11 12 struct clk_ops { 13 void (*init)(struct clk *clk); 14 int (*enable)(struct clk *clk); 15 void (*disable)(struct clk *clk); 16 unsigned long (*recalc)(struct clk *clk); 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 18 int (*set_parent)(struct clk *clk, struct clk *parent); 19 long (*round_rate)(struct clk *clk, unsigned long rate); 20 }; 21 22 struct clk { 23 struct list_head node; 24 const char *name; 25 int id; 26 27 struct clk *parent; 28 struct clk_ops *ops; 29 30 struct list_head children; 31 struct list_head sibling; /* node for children */ 32 33 int usecount; 34 35 unsigned long rate; 36 unsigned long flags; 37 38 void __iomem *enable_reg; 39 unsigned int enable_bit; 40 41 unsigned long arch_flags; 42 void *priv; 43 struct dentry *dentry; 44 struct cpufreq_frequency_table *freq_table; 45 }; 46 47 #define CLK_ENABLE_ON_INIT (1 << 0) 48 49 /* Should be defined by processor-specific code */ 50 void __deprecated arch_init_clk_ops(struct clk_ops **, int type); 51 int __init arch_clk_init(void); 52 53 /* arch/sh/kernel/cpu/clock.c */ 54 int clk_init(void); 55 unsigned long followparent_recalc(struct clk *); 56 void recalculate_root_clocks(void); 57 void propagate_rate(struct clk *); 58 int clk_reparent(struct clk *child, struct clk *parent); 59 int clk_register(struct clk *); 60 void clk_unregister(struct clk *); 61 62 /* arch/sh/kernel/cpu/clock-cpg.c */ 63 int __init __deprecated cpg_clk_init(void); 64 65 /* the exported API, in addition to clk_set_rate */ 66 /** 67 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter 68 * @clk: clock source 69 * @rate: desired clock rate in Hz 70 * @algo_id: algorithm id to be passed down to ops->set_rate 71 * 72 * Returns success (0) or negative errno. 73 */ 74 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); 75 76 enum clk_sh_algo_id { 77 NO_CHANGE = 0, 78 79 IUS_N1_N1, 80 IUS_322, 81 IUS_522, 82 IUS_N11, 83 84 SB_N1, 85 86 SB3_N1, 87 SB3_32, 88 SB3_43, 89 SB3_54, 90 91 BP_N1, 92 93 IP_N1, 94 }; 95 96 struct clk_div_mult_table { 97 unsigned int *divisors; 98 unsigned int nr_divisors; 99 unsigned int *multipliers; 100 unsigned int nr_multipliers; 101 }; 102 103 struct cpufreq_frequency_table; 104 void clk_rate_table_build(struct clk *clk, 105 struct cpufreq_frequency_table *freq_table, 106 int nr_freqs, 107 struct clk_div_mult_table *src_table, 108 unsigned long *bitmap); 109 110 long clk_rate_table_round(struct clk *clk, 111 struct cpufreq_frequency_table *freq_table, 112 unsigned long rate); 113 114 int clk_rate_table_find(struct clk *clk, 115 struct cpufreq_frequency_table *freq_table, 116 unsigned long rate); 117 118 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ 119 { \ 120 .parent = _parent, \ 121 .enable_reg = (void __iomem *)_enable_reg, \ 122 .enable_bit = _enable_bit, \ 123 .flags = _flags, \ 124 } 125 126 int sh_clk_mstp32_register(struct clk *clks, int nr); 127 128 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ 129 { \ 130 .parent = _parent, \ 131 .enable_reg = (void __iomem *)_reg, \ 132 .enable_bit = _shift, \ 133 .arch_flags = _div_bitmap, \ 134 .flags = _flags, \ 135 } 136 137 struct clk_div4_table { 138 struct clk_div_mult_table *div_mult_table; 139 void (*kick)(struct clk *clk); 140 }; 141 142 int sh_clk_div4_register(struct clk *clks, int nr, 143 struct clk_div4_table *table); 144 int sh_clk_div4_enable_register(struct clk *clks, int nr, 145 struct clk_div4_table *table); 146 int sh_clk_div4_reparent_register(struct clk *clks, int nr, 147 struct clk_div4_table *table); 148 149 #define SH_CLK_DIV6(_parent, _reg, _flags) \ 150 { \ 151 .parent = _parent, \ 152 .enable_reg = (void __iomem *)_reg, \ 153 .flags = _flags, \ 154 } 155 156 int sh_clk_div6_register(struct clk *clks, int nr); 157 158 #endif /* __ASM_SH_CLOCK_H */ 159