xref: /linux/arch/sh/boards/board-sh7785lcr.c (revision f03c4866d31e913a8dbc84f7d1459abdaf0bd326)
1c8b5d9dcSPaul Mundt /*
2c8b5d9dcSPaul Mundt  * Renesas Technology Corp. R0P7785LC0011RL Support.
3c8b5d9dcSPaul Mundt  *
4c8b5d9dcSPaul Mundt  * Copyright (C) 2008  Yoshihiro Shimoda
5a77b5ac0SPaul Mundt  * Copyright (C) 2009  Paul Mundt
6c8b5d9dcSPaul Mundt  *
7c8b5d9dcSPaul Mundt  * This file is subject to the terms and conditions of the GNU General Public
8c8b5d9dcSPaul Mundt  * License.  See the file "COPYING" in the main directory of this archive
9c8b5d9dcSPaul Mundt  * for more details.
10c8b5d9dcSPaul Mundt  */
11c8b5d9dcSPaul Mundt #include <linux/init.h>
12c8b5d9dcSPaul Mundt #include <linux/platform_device.h>
13c8b5d9dcSPaul Mundt #include <linux/sm501.h>
14c8b5d9dcSPaul Mundt #include <linux/sm501-regs.h>
15c8b5d9dcSPaul Mundt #include <linux/fb.h>
16c8b5d9dcSPaul Mundt #include <linux/mtd/physmap.h>
17c8b5d9dcSPaul Mundt #include <linux/delay.h>
185a62a225SYoshihiro Shimoda #include <linux/interrupt.h>
19c8b5d9dcSPaul Mundt #include <linux/i2c.h>
20c8b5d9dcSPaul Mundt #include <linux/i2c-pca-platform.h>
21c8b5d9dcSPaul Mundt #include <linux/i2c-algo-pca.h>
225a62a225SYoshihiro Shimoda #include <linux/usb/r8a66597.h>
23604437f0SPaul Mundt #include <linux/irq.h>
24d57d6408SPaul Mundt #include <linux/io.h>
25a77b5ac0SPaul Mundt #include <linux/clk.h>
26a77b5ac0SPaul Mundt #include <linux/errno.h>
277639a454SPaul Mundt #include <mach/sh7785lcr.h>
285a62a225SYoshihiro Shimoda #include <cpu/sh7785.h>
29a77b5ac0SPaul Mundt #include <asm/heartbeat.h>
30a77b5ac0SPaul Mundt #include <asm/clock.h>
31*f03c4866SPaul Mundt #include <asm/bl_bit.h>
32c8b5d9dcSPaul Mundt 
33c8b5d9dcSPaul Mundt /*
34c8b5d9dcSPaul Mundt  * NOTE: This board has 2 physical memory maps.
35c8b5d9dcSPaul Mundt  *	 Please look at include/asm-sh/sh7785lcr.h or hardware manual.
36c8b5d9dcSPaul Mundt  */
37a09d2831SPaul Mundt static struct resource heartbeat_resource = {
38c8b5d9dcSPaul Mundt 	.start	= PLD_LEDCR,
39c8b5d9dcSPaul Mundt 	.end	= PLD_LEDCR,
40a09d2831SPaul Mundt 	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
41c8b5d9dcSPaul Mundt };
42c8b5d9dcSPaul Mundt 
43c8b5d9dcSPaul Mundt static struct platform_device heartbeat_device = {
44c8b5d9dcSPaul Mundt 	.name		= "heartbeat",
45c8b5d9dcSPaul Mundt 	.id		= -1,
46a09d2831SPaul Mundt 	.num_resources	= 1,
47a09d2831SPaul Mundt 	.resource	= &heartbeat_resource,
48c8b5d9dcSPaul Mundt };
49c8b5d9dcSPaul Mundt 
50c8b5d9dcSPaul Mundt static struct mtd_partition nor_flash_partitions[] = {
51c8b5d9dcSPaul Mundt 	{
52c8b5d9dcSPaul Mundt 		.name		= "loader",
53c8b5d9dcSPaul Mundt 		.offset		= 0x00000000,
54c8b5d9dcSPaul Mundt 		.size		= 512 * 1024,
55c8b5d9dcSPaul Mundt 	},
56c8b5d9dcSPaul Mundt 	{
57c8b5d9dcSPaul Mundt 		.name		= "bootenv",
58c8b5d9dcSPaul Mundt 		.offset		= MTDPART_OFS_APPEND,
59c8b5d9dcSPaul Mundt 		.size		= 512 * 1024,
60c8b5d9dcSPaul Mundt 	},
61c8b5d9dcSPaul Mundt 	{
62c8b5d9dcSPaul Mundt 		.name		= "kernel",
63c8b5d9dcSPaul Mundt 		.offset		= MTDPART_OFS_APPEND,
64c8b5d9dcSPaul Mundt 		.size		= 4 * 1024 * 1024,
65c8b5d9dcSPaul Mundt 	},
66c8b5d9dcSPaul Mundt 	{
67c8b5d9dcSPaul Mundt 		.name		= "data",
68c8b5d9dcSPaul Mundt 		.offset		= MTDPART_OFS_APPEND,
69c8b5d9dcSPaul Mundt 		.size		= MTDPART_SIZ_FULL,
70c8b5d9dcSPaul Mundt 	},
71c8b5d9dcSPaul Mundt };
72c8b5d9dcSPaul Mundt 
73c8b5d9dcSPaul Mundt static struct physmap_flash_data nor_flash_data = {
74c8b5d9dcSPaul Mundt 	.width		= 4,
75c8b5d9dcSPaul Mundt 	.parts		= nor_flash_partitions,
76c8b5d9dcSPaul Mundt 	.nr_parts	= ARRAY_SIZE(nor_flash_partitions),
77c8b5d9dcSPaul Mundt };
78c8b5d9dcSPaul Mundt 
79c8b5d9dcSPaul Mundt static struct resource nor_flash_resources[] = {
80c8b5d9dcSPaul Mundt 	[0]	= {
81c8b5d9dcSPaul Mundt 		.start	= NOR_FLASH_ADDR,
82c8b5d9dcSPaul Mundt 		.end	= NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
83c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_MEM,
84c8b5d9dcSPaul Mundt 	}
85c8b5d9dcSPaul Mundt };
86c8b5d9dcSPaul Mundt 
87c8b5d9dcSPaul Mundt static struct platform_device nor_flash_device = {
88c8b5d9dcSPaul Mundt 	.name		= "physmap-flash",
89c8b5d9dcSPaul Mundt 	.dev		= {
90c8b5d9dcSPaul Mundt 		.platform_data	= &nor_flash_data,
91c8b5d9dcSPaul Mundt 	},
92c8b5d9dcSPaul Mundt 	.num_resources	= ARRAY_SIZE(nor_flash_resources),
93c8b5d9dcSPaul Mundt 	.resource	= nor_flash_resources,
94c8b5d9dcSPaul Mundt };
95c8b5d9dcSPaul Mundt 
965a62a225SYoshihiro Shimoda static struct r8a66597_platdata r8a66597_data = {
975a62a225SYoshihiro Shimoda 	.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
985a62a225SYoshihiro Shimoda 	.vif = 1,
995a62a225SYoshihiro Shimoda };
1005a62a225SYoshihiro Shimoda 
101c8b5d9dcSPaul Mundt static struct resource r8a66597_usb_host_resources[] = {
102c8b5d9dcSPaul Mundt 	[0] = {
103c8b5d9dcSPaul Mundt 		.start	= R8A66597_ADDR,
104c8b5d9dcSPaul Mundt 		.end	= R8A66597_ADDR + R8A66597_SIZE - 1,
105c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_MEM,
106c8b5d9dcSPaul Mundt 	},
107c8b5d9dcSPaul Mundt 	[1] = {
108c8b5d9dcSPaul Mundt 		.start	= 2,
109c8b5d9dcSPaul Mundt 		.end	= 2,
1105a62a225SYoshihiro Shimoda 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
111c8b5d9dcSPaul Mundt 	},
112c8b5d9dcSPaul Mundt };
113c8b5d9dcSPaul Mundt 
114c8b5d9dcSPaul Mundt static struct platform_device r8a66597_usb_host_device = {
115c8b5d9dcSPaul Mundt 	.name		= "r8a66597_hcd",
116c8b5d9dcSPaul Mundt 	.id		= -1,
117c8b5d9dcSPaul Mundt 	.dev = {
118c8b5d9dcSPaul Mundt 		.dma_mask		= NULL,
119c8b5d9dcSPaul Mundt 		.coherent_dma_mask	= 0xffffffff,
1205a62a225SYoshihiro Shimoda 		.platform_data		= &r8a66597_data,
121c8b5d9dcSPaul Mundt 	},
122c8b5d9dcSPaul Mundt 	.num_resources	= ARRAY_SIZE(r8a66597_usb_host_resources),
123c8b5d9dcSPaul Mundt 	.resource	= r8a66597_usb_host_resources,
124c8b5d9dcSPaul Mundt };
125c8b5d9dcSPaul Mundt 
126c8b5d9dcSPaul Mundt static struct resource sm501_resources[] = {
127c8b5d9dcSPaul Mundt 	[0]	= {
128c8b5d9dcSPaul Mundt 		.start	= SM107_MEM_ADDR,
129c8b5d9dcSPaul Mundt 		.end	= SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
130c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_MEM,
131c8b5d9dcSPaul Mundt 	},
132c8b5d9dcSPaul Mundt 	[1]	= {
133c8b5d9dcSPaul Mundt 		.start	= SM107_REG_ADDR,
134c8b5d9dcSPaul Mundt 		.end	= SM107_REG_ADDR + SM107_REG_SIZE - 1,
135c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_MEM,
136c8b5d9dcSPaul Mundt 	},
137c8b5d9dcSPaul Mundt 	[2]	= {
138c8b5d9dcSPaul Mundt 		.start	= 10,
139c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_IRQ,
140c8b5d9dcSPaul Mundt 	},
141c8b5d9dcSPaul Mundt };
142c8b5d9dcSPaul Mundt 
143c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_crt = {
144c8b5d9dcSPaul Mundt 	.pixclock	= 35714,	/* 28MHz */
145c8b5d9dcSPaul Mundt 	.xres		= 640,
146c8b5d9dcSPaul Mundt 	.yres		= 480,
147c8b5d9dcSPaul Mundt 	.left_margin	= 105,
148c8b5d9dcSPaul Mundt 	.right_margin	= 16,
149c8b5d9dcSPaul Mundt 	.upper_margin	= 33,
150c8b5d9dcSPaul Mundt 	.lower_margin	= 10,
151c8b5d9dcSPaul Mundt 	.hsync_len	= 39,
152c8b5d9dcSPaul Mundt 	.vsync_len	= 2,
153c8b5d9dcSPaul Mundt 	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
154c8b5d9dcSPaul Mundt };
155c8b5d9dcSPaul Mundt 
156c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_pnl = {
157c8b5d9dcSPaul Mundt 	.pixclock	= 40000,	/* 25MHz */
158c8b5d9dcSPaul Mundt 	.xres		= 640,
159c8b5d9dcSPaul Mundt 	.yres		= 480,
160c8b5d9dcSPaul Mundt 	.left_margin	= 2,
161c8b5d9dcSPaul Mundt 	.right_margin	= 16,
162c8b5d9dcSPaul Mundt 	.upper_margin	= 33,
163c8b5d9dcSPaul Mundt 	.lower_margin	= 10,
164c8b5d9dcSPaul Mundt 	.hsync_len	= 39,
165c8b5d9dcSPaul Mundt 	.vsync_len	= 2,
166c8b5d9dcSPaul Mundt 	.sync		= 0,
167c8b5d9dcSPaul Mundt };
168c8b5d9dcSPaul Mundt 
169c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
170c8b5d9dcSPaul Mundt 	.def_bpp	= 16,
171c8b5d9dcSPaul Mundt 	.def_mode	= &sm501_default_mode_pnl,
172c8b5d9dcSPaul Mundt 	.flags		= SM501FB_FLAG_USE_INIT_MODE |
173c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_USE_HWCURSOR |
174c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_USE_HWACCEL |
175c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_DISABLE_AT_EXIT |
176c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_PANEL_NO_VBIASEN,
177c8b5d9dcSPaul Mundt };
178c8b5d9dcSPaul Mundt 
179c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
180c8b5d9dcSPaul Mundt 	.def_bpp	= 16,
181c8b5d9dcSPaul Mundt 	.def_mode	= &sm501_default_mode_crt,
182c8b5d9dcSPaul Mundt 	.flags		= SM501FB_FLAG_USE_INIT_MODE |
183c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_USE_HWCURSOR |
184c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_USE_HWACCEL |
185c8b5d9dcSPaul Mundt 			  SM501FB_FLAG_DISABLE_AT_EXIT,
186c8b5d9dcSPaul Mundt };
187c8b5d9dcSPaul Mundt 
188c8b5d9dcSPaul Mundt static struct sm501_platdata_fb sm501_fb_pdata = {
189c8b5d9dcSPaul Mundt 	.fb_route	= SM501_FB_OWN,
190c8b5d9dcSPaul Mundt 	.fb_crt		= &sm501_pdata_fbsub_crt,
191c8b5d9dcSPaul Mundt 	.fb_pnl		= &sm501_pdata_fbsub_pnl,
192c8b5d9dcSPaul Mundt };
193c8b5d9dcSPaul Mundt 
194c8b5d9dcSPaul Mundt static struct sm501_initdata sm501_initdata = {
195c8b5d9dcSPaul Mundt 	.gpio_high	= {
196c8b5d9dcSPaul Mundt 		.set	= 0x00001fe0,
197c8b5d9dcSPaul Mundt 		.mask	= 0x0,
198c8b5d9dcSPaul Mundt 	},
199c8b5d9dcSPaul Mundt 	.devices	= 0,
200c8b5d9dcSPaul Mundt 	.mclk		= 84 * 1000000,
201c8b5d9dcSPaul Mundt 	.m1xclk		= 112 * 1000000,
202c8b5d9dcSPaul Mundt };
203c8b5d9dcSPaul Mundt 
204c8b5d9dcSPaul Mundt static struct sm501_platdata sm501_platform_data = {
205c8b5d9dcSPaul Mundt 	.init		= &sm501_initdata,
206c8b5d9dcSPaul Mundt 	.fb		= &sm501_fb_pdata,
207c8b5d9dcSPaul Mundt };
208c8b5d9dcSPaul Mundt 
209c8b5d9dcSPaul Mundt static struct platform_device sm501_device = {
210c8b5d9dcSPaul Mundt 	.name		= "sm501",
211c8b5d9dcSPaul Mundt 	.id		= -1,
212c8b5d9dcSPaul Mundt 	.dev		= {
213c8b5d9dcSPaul Mundt 		.platform_data	= &sm501_platform_data,
214c8b5d9dcSPaul Mundt 	},
215c8b5d9dcSPaul Mundt 	.num_resources	= ARRAY_SIZE(sm501_resources),
216c8b5d9dcSPaul Mundt 	.resource	= sm501_resources,
217c8b5d9dcSPaul Mundt };
218c8b5d9dcSPaul Mundt 
219e79d5747SYoshihiro Shimoda static struct resource i2c_proto_resources[] = {
220e79d5747SYoshihiro Shimoda 	[0] = {
221e79d5747SYoshihiro Shimoda 		.start	= PCA9564_PROTO_32BIT_ADDR,
222e79d5747SYoshihiro Shimoda 		.end	= PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
223e79d5747SYoshihiro Shimoda 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
224e79d5747SYoshihiro Shimoda 	},
225e79d5747SYoshihiro Shimoda 	[1] = {
226e79d5747SYoshihiro Shimoda 		.start	= 12,
227e79d5747SYoshihiro Shimoda 		.end	= 12,
228e79d5747SYoshihiro Shimoda 		.flags	= IORESOURCE_IRQ,
229e79d5747SYoshihiro Shimoda 	},
230e79d5747SYoshihiro Shimoda };
231e79d5747SYoshihiro Shimoda 
232c8b5d9dcSPaul Mundt static struct resource i2c_resources[] = {
233c8b5d9dcSPaul Mundt 	[0] = {
234c8b5d9dcSPaul Mundt 		.start	= PCA9564_ADDR,
235c8b5d9dcSPaul Mundt 		.end	= PCA9564_ADDR + PCA9564_SIZE - 1,
236c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
237c8b5d9dcSPaul Mundt 	},
238c8b5d9dcSPaul Mundt 	[1] = {
239c8b5d9dcSPaul Mundt 		.start	= 12,
240c8b5d9dcSPaul Mundt 		.end	= 12,
241c8b5d9dcSPaul Mundt 		.flags	= IORESOURCE_IRQ,
242c8b5d9dcSPaul Mundt 	},
243c8b5d9dcSPaul Mundt };
244c8b5d9dcSPaul Mundt 
245c8b5d9dcSPaul Mundt static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
246c8b5d9dcSPaul Mundt 	.gpio			= 0,
247c8b5d9dcSPaul Mundt 	.i2c_clock_speed	= I2C_PCA_CON_330kHz,
2488e99ada8SWolfram Sang 	.timeout		= HZ,
249c8b5d9dcSPaul Mundt };
250c8b5d9dcSPaul Mundt 
251c8b5d9dcSPaul Mundt static struct platform_device i2c_device = {
252c8b5d9dcSPaul Mundt 	.name		= "i2c-pca-platform",
253c8b5d9dcSPaul Mundt 	.id		= -1,
254c8b5d9dcSPaul Mundt 	.dev		= {
255c8b5d9dcSPaul Mundt 		.platform_data	= &i2c_platform_data,
256c8b5d9dcSPaul Mundt 	},
257c8b5d9dcSPaul Mundt 	.num_resources	= ARRAY_SIZE(i2c_resources),
258c8b5d9dcSPaul Mundt 	.resource	= i2c_resources,
259c8b5d9dcSPaul Mundt };
260c8b5d9dcSPaul Mundt 
261c8b5d9dcSPaul Mundt static struct platform_device *sh7785lcr_devices[] __initdata = {
262c8b5d9dcSPaul Mundt 	&heartbeat_device,
263c8b5d9dcSPaul Mundt 	&nor_flash_device,
264c8b5d9dcSPaul Mundt 	&r8a66597_usb_host_device,
265c8b5d9dcSPaul Mundt 	&sm501_device,
266c8b5d9dcSPaul Mundt 	&i2c_device,
267c8b5d9dcSPaul Mundt };
268c8b5d9dcSPaul Mundt 
269c8b5d9dcSPaul Mundt static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
270c8b5d9dcSPaul Mundt 	{
271c8b5d9dcSPaul Mundt 		I2C_BOARD_INFO("r2025sd", 0x32),
272c8b5d9dcSPaul Mundt 	},
273c8b5d9dcSPaul Mundt };
274c8b5d9dcSPaul Mundt 
275c8b5d9dcSPaul Mundt static int __init sh7785lcr_devices_setup(void)
276c8b5d9dcSPaul Mundt {
277c8b5d9dcSPaul Mundt 	i2c_register_board_info(0, sh7785lcr_i2c_devices,
278c8b5d9dcSPaul Mundt 				ARRAY_SIZE(sh7785lcr_i2c_devices));
279c8b5d9dcSPaul Mundt 
280e79d5747SYoshihiro Shimoda 	if (mach_is_sh7785lcr_pt()) {
281d1af119aSPaul Mundt 		i2c_device.resource = i2c_proto_resources;
282e79d5747SYoshihiro Shimoda 		i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
283e79d5747SYoshihiro Shimoda 	}
284e79d5747SYoshihiro Shimoda 
285c8b5d9dcSPaul Mundt 	return platform_add_devices(sh7785lcr_devices,
286c8b5d9dcSPaul Mundt 				    ARRAY_SIZE(sh7785lcr_devices));
287c8b5d9dcSPaul Mundt }
28895d210ceSNobuhiro Iwamatsu device_initcall(sh7785lcr_devices_setup);
289c8b5d9dcSPaul Mundt 
290c8b5d9dcSPaul Mundt /* Initialize IRQ setting */
291c8b5d9dcSPaul Mundt void __init init_sh7785lcr_IRQ(void)
292c8b5d9dcSPaul Mundt {
293c8b5d9dcSPaul Mundt 	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
294c8b5d9dcSPaul Mundt 	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
295c8b5d9dcSPaul Mundt }
296c8b5d9dcSPaul Mundt 
297a77b5ac0SPaul Mundt static int sh7785lcr_clk_init(void)
298a77b5ac0SPaul Mundt {
299a77b5ac0SPaul Mundt 	struct clk *clk;
300a77b5ac0SPaul Mundt 	int ret;
301a77b5ac0SPaul Mundt 
302a77b5ac0SPaul Mundt 	clk = clk_get(NULL, "extal");
3037912825dSPaul Mundt 	if (IS_ERR(clk))
304a77b5ac0SPaul Mundt 		return PTR_ERR(clk);
305a77b5ac0SPaul Mundt 	ret = clk_set_rate(clk, 33333333);
306a77b5ac0SPaul Mundt 	clk_put(clk);
307a77b5ac0SPaul Mundt 
308a77b5ac0SPaul Mundt 	return ret;
309a77b5ac0SPaul Mundt }
310a77b5ac0SPaul Mundt 
311c8b5d9dcSPaul Mundt static void sh7785lcr_power_off(void)
312c8b5d9dcSPaul Mundt {
313df4d4f1aSYoshihiro Shimoda 	unsigned char *p;
314df4d4f1aSYoshihiro Shimoda 
315df4d4f1aSYoshihiro Shimoda 	p = ioremap(PLD_POFCR, PLD_POFCR + 1);
316df4d4f1aSYoshihiro Shimoda 	if (!p) {
317df4d4f1aSYoshihiro Shimoda 		printk(KERN_ERR "%s: ioremap error.\n", __func__);
318df4d4f1aSYoshihiro Shimoda 		return;
319df4d4f1aSYoshihiro Shimoda 	}
320df4d4f1aSYoshihiro Shimoda 	*p = 0x01;
321df4d4f1aSYoshihiro Shimoda 	iounmap(p);
322600fa578SMagnus Damm 	set_bl_bit();
323600fa578SMagnus Damm 	while (1)
324600fa578SMagnus Damm 		cpu_relax();
325c8b5d9dcSPaul Mundt }
326c8b5d9dcSPaul Mundt 
327c8b5d9dcSPaul Mundt /* Initialize the board */
328c8b5d9dcSPaul Mundt static void __init sh7785lcr_setup(char **cmdline_p)
329c8b5d9dcSPaul Mundt {
330c8b5d9dcSPaul Mundt 	void __iomem *sm501_reg;
331c8b5d9dcSPaul Mundt 
332c8b5d9dcSPaul Mundt 	printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
333c8b5d9dcSPaul Mundt 
334c8b5d9dcSPaul Mundt 	pm_power_off = sh7785lcr_power_off;
335c8b5d9dcSPaul Mundt 
336c8b5d9dcSPaul Mundt 	/* sm501 DRAM configuration */
337d57d6408SPaul Mundt 	sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
3386f82b6ebSMatt Fleming 	if (!sm501_reg) {
3396f82b6ebSMatt Fleming 		printk(KERN_ERR "%s: ioremap error.\n", __func__);
3406f82b6ebSMatt Fleming 		return;
3416f82b6ebSMatt Fleming 	}
3426f82b6ebSMatt Fleming 
3436f82b6ebSMatt Fleming 	writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
344d57d6408SPaul Mundt 	iounmap(sm501_reg);
345c8b5d9dcSPaul Mundt }
346c8b5d9dcSPaul Mundt 
34763d12e23SMagnus Damm /* Return the board specific boot mode pin configuration */
34863d12e23SMagnus Damm static int sh7785lcr_mode_pins(void)
34963d12e23SMagnus Damm {
35063d12e23SMagnus Damm 	int value = 0;
35163d12e23SMagnus Damm 
35263d12e23SMagnus Damm 	/* These are the factory default settings of S1 and S2.
35363d12e23SMagnus Damm 	 * If you change these dip switches then you will need to
35463d12e23SMagnus Damm 	 * adjust the values below as well.
35563d12e23SMagnus Damm 	 */
3560d4fdbb6SMagnus Damm 	value |= MODE_PIN4; /* Clock Mode 16 */
3570d4fdbb6SMagnus Damm 	value |= MODE_PIN5; /* 32-bit Area0 bus width */
3580d4fdbb6SMagnus Damm 	value |= MODE_PIN6; /* 32-bit Area0 bus width */
3590d4fdbb6SMagnus Damm 	value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
3600d4fdbb6SMagnus Damm 	value |= MODE_PIN8; /* Little Endian */
3610d4fdbb6SMagnus Damm 	value |= MODE_PIN9; /* Master Mode */
3620d4fdbb6SMagnus Damm 	value |= MODE_PIN14; /* No PLL step-up */
36363d12e23SMagnus Damm 
36463d12e23SMagnus Damm 	return value;
36563d12e23SMagnus Damm }
36663d12e23SMagnus Damm 
367c8b5d9dcSPaul Mundt /*
368c8b5d9dcSPaul Mundt  * The Machine Vector
369c8b5d9dcSPaul Mundt  */
370c8b5d9dcSPaul Mundt static struct sh_machine_vector mv_sh7785lcr __initmv = {
371c8b5d9dcSPaul Mundt 	.mv_name		= "SH7785LCR",
372c8b5d9dcSPaul Mundt 	.mv_setup		= sh7785lcr_setup,
373a77b5ac0SPaul Mundt 	.mv_clk_init		= sh7785lcr_clk_init,
374c8b5d9dcSPaul Mundt 	.mv_init_irq		= init_sh7785lcr_IRQ,
37563d12e23SMagnus Damm 	.mv_mode_pins		= sh7785lcr_mode_pins,
376c8b5d9dcSPaul Mundt };
377c8b5d9dcSPaul Mundt 
378