1c8b5d9dcSPaul Mundt /* 2c8b5d9dcSPaul Mundt * Renesas Technology Corp. R0P7785LC0011RL Support. 3c8b5d9dcSPaul Mundt * 4c8b5d9dcSPaul Mundt * Copyright (C) 2008 Yoshihiro Shimoda 5a77b5ac0SPaul Mundt * Copyright (C) 2009 Paul Mundt 6c8b5d9dcSPaul Mundt * 7c8b5d9dcSPaul Mundt * This file is subject to the terms and conditions of the GNU General Public 8c8b5d9dcSPaul Mundt * License. See the file "COPYING" in the main directory of this archive 9c8b5d9dcSPaul Mundt * for more details. 10c8b5d9dcSPaul Mundt */ 11c8b5d9dcSPaul Mundt #include <linux/init.h> 12c8b5d9dcSPaul Mundt #include <linux/platform_device.h> 13c8b5d9dcSPaul Mundt #include <linux/sm501.h> 14c8b5d9dcSPaul Mundt #include <linux/sm501-regs.h> 15c8b5d9dcSPaul Mundt #include <linux/fb.h> 16c8b5d9dcSPaul Mundt #include <linux/mtd/physmap.h> 17c8b5d9dcSPaul Mundt #include <linux/delay.h> 18*5a62a225SYoshihiro Shimoda #include <linux/interrupt.h> 19c8b5d9dcSPaul Mundt #include <linux/i2c.h> 20c8b5d9dcSPaul Mundt #include <linux/i2c-pca-platform.h> 21c8b5d9dcSPaul Mundt #include <linux/i2c-algo-pca.h> 22*5a62a225SYoshihiro Shimoda #include <linux/usb/r8a66597.h> 23604437f0SPaul Mundt #include <linux/irq.h> 24a77b5ac0SPaul Mundt #include <linux/clk.h> 25a77b5ac0SPaul Mundt #include <linux/errno.h> 267639a454SPaul Mundt #include <mach/sh7785lcr.h> 27*5a62a225SYoshihiro Shimoda #include <cpu/sh7785.h> 28a77b5ac0SPaul Mundt #include <asm/heartbeat.h> 29a77b5ac0SPaul Mundt #include <asm/clock.h> 30c8b5d9dcSPaul Mundt 31c8b5d9dcSPaul Mundt /* 32c8b5d9dcSPaul Mundt * NOTE: This board has 2 physical memory maps. 33c8b5d9dcSPaul Mundt * Please look at include/asm-sh/sh7785lcr.h or hardware manual. 34c8b5d9dcSPaul Mundt */ 35c8b5d9dcSPaul Mundt static struct resource heartbeat_resources[] = { 36c8b5d9dcSPaul Mundt [0] = { 37c8b5d9dcSPaul Mundt .start = PLD_LEDCR, 38c8b5d9dcSPaul Mundt .end = PLD_LEDCR, 39c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM, 40c8b5d9dcSPaul Mundt }, 41c8b5d9dcSPaul Mundt }; 42c8b5d9dcSPaul Mundt 43c8b5d9dcSPaul Mundt static struct heartbeat_data heartbeat_data = { 44c8b5d9dcSPaul Mundt .regsize = 8, 45c8b5d9dcSPaul Mundt }; 46c8b5d9dcSPaul Mundt 47c8b5d9dcSPaul Mundt static struct platform_device heartbeat_device = { 48c8b5d9dcSPaul Mundt .name = "heartbeat", 49c8b5d9dcSPaul Mundt .id = -1, 50c8b5d9dcSPaul Mundt .dev = { 51c8b5d9dcSPaul Mundt .platform_data = &heartbeat_data, 52c8b5d9dcSPaul Mundt }, 53c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(heartbeat_resources), 54c8b5d9dcSPaul Mundt .resource = heartbeat_resources, 55c8b5d9dcSPaul Mundt }; 56c8b5d9dcSPaul Mundt 57c8b5d9dcSPaul Mundt static struct mtd_partition nor_flash_partitions[] = { 58c8b5d9dcSPaul Mundt { 59c8b5d9dcSPaul Mundt .name = "loader", 60c8b5d9dcSPaul Mundt .offset = 0x00000000, 61c8b5d9dcSPaul Mundt .size = 512 * 1024, 62c8b5d9dcSPaul Mundt }, 63c8b5d9dcSPaul Mundt { 64c8b5d9dcSPaul Mundt .name = "bootenv", 65c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND, 66c8b5d9dcSPaul Mundt .size = 512 * 1024, 67c8b5d9dcSPaul Mundt }, 68c8b5d9dcSPaul Mundt { 69c8b5d9dcSPaul Mundt .name = "kernel", 70c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND, 71c8b5d9dcSPaul Mundt .size = 4 * 1024 * 1024, 72c8b5d9dcSPaul Mundt }, 73c8b5d9dcSPaul Mundt { 74c8b5d9dcSPaul Mundt .name = "data", 75c8b5d9dcSPaul Mundt .offset = MTDPART_OFS_APPEND, 76c8b5d9dcSPaul Mundt .size = MTDPART_SIZ_FULL, 77c8b5d9dcSPaul Mundt }, 78c8b5d9dcSPaul Mundt }; 79c8b5d9dcSPaul Mundt 80c8b5d9dcSPaul Mundt static struct physmap_flash_data nor_flash_data = { 81c8b5d9dcSPaul Mundt .width = 4, 82c8b5d9dcSPaul Mundt .parts = nor_flash_partitions, 83c8b5d9dcSPaul Mundt .nr_parts = ARRAY_SIZE(nor_flash_partitions), 84c8b5d9dcSPaul Mundt }; 85c8b5d9dcSPaul Mundt 86c8b5d9dcSPaul Mundt static struct resource nor_flash_resources[] = { 87c8b5d9dcSPaul Mundt [0] = { 88c8b5d9dcSPaul Mundt .start = NOR_FLASH_ADDR, 89c8b5d9dcSPaul Mundt .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, 90c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM, 91c8b5d9dcSPaul Mundt } 92c8b5d9dcSPaul Mundt }; 93c8b5d9dcSPaul Mundt 94c8b5d9dcSPaul Mundt static struct platform_device nor_flash_device = { 95c8b5d9dcSPaul Mundt .name = "physmap-flash", 96c8b5d9dcSPaul Mundt .dev = { 97c8b5d9dcSPaul Mundt .platform_data = &nor_flash_data, 98c8b5d9dcSPaul Mundt }, 99c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(nor_flash_resources), 100c8b5d9dcSPaul Mundt .resource = nor_flash_resources, 101c8b5d9dcSPaul Mundt }; 102c8b5d9dcSPaul Mundt 103*5a62a225SYoshihiro Shimoda static struct r8a66597_platdata r8a66597_data = { 104*5a62a225SYoshihiro Shimoda .xtal = R8A66597_PLATDATA_XTAL_12MHZ, 105*5a62a225SYoshihiro Shimoda .vif = 1, 106*5a62a225SYoshihiro Shimoda }; 107*5a62a225SYoshihiro Shimoda 108c8b5d9dcSPaul Mundt static struct resource r8a66597_usb_host_resources[] = { 109c8b5d9dcSPaul Mundt [0] = { 110c8b5d9dcSPaul Mundt .start = R8A66597_ADDR, 111c8b5d9dcSPaul Mundt .end = R8A66597_ADDR + R8A66597_SIZE - 1, 112c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM, 113c8b5d9dcSPaul Mundt }, 114c8b5d9dcSPaul Mundt [1] = { 115c8b5d9dcSPaul Mundt .start = 2, 116c8b5d9dcSPaul Mundt .end = 2, 117*5a62a225SYoshihiro Shimoda .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 118c8b5d9dcSPaul Mundt }, 119c8b5d9dcSPaul Mundt }; 120c8b5d9dcSPaul Mundt 121c8b5d9dcSPaul Mundt static struct platform_device r8a66597_usb_host_device = { 122c8b5d9dcSPaul Mundt .name = "r8a66597_hcd", 123c8b5d9dcSPaul Mundt .id = -1, 124c8b5d9dcSPaul Mundt .dev = { 125c8b5d9dcSPaul Mundt .dma_mask = NULL, 126c8b5d9dcSPaul Mundt .coherent_dma_mask = 0xffffffff, 127*5a62a225SYoshihiro Shimoda .platform_data = &r8a66597_data, 128c8b5d9dcSPaul Mundt }, 129c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), 130c8b5d9dcSPaul Mundt .resource = r8a66597_usb_host_resources, 131c8b5d9dcSPaul Mundt }; 132c8b5d9dcSPaul Mundt 133c8b5d9dcSPaul Mundt static struct resource sm501_resources[] = { 134c8b5d9dcSPaul Mundt [0] = { 135c8b5d9dcSPaul Mundt .start = SM107_MEM_ADDR, 136c8b5d9dcSPaul Mundt .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, 137c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM, 138c8b5d9dcSPaul Mundt }, 139c8b5d9dcSPaul Mundt [1] = { 140c8b5d9dcSPaul Mundt .start = SM107_REG_ADDR, 141c8b5d9dcSPaul Mundt .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, 142c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM, 143c8b5d9dcSPaul Mundt }, 144c8b5d9dcSPaul Mundt [2] = { 145c8b5d9dcSPaul Mundt .start = 10, 146c8b5d9dcSPaul Mundt .flags = IORESOURCE_IRQ, 147c8b5d9dcSPaul Mundt }, 148c8b5d9dcSPaul Mundt }; 149c8b5d9dcSPaul Mundt 150c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_crt = { 151c8b5d9dcSPaul Mundt .pixclock = 35714, /* 28MHz */ 152c8b5d9dcSPaul Mundt .xres = 640, 153c8b5d9dcSPaul Mundt .yres = 480, 154c8b5d9dcSPaul Mundt .left_margin = 105, 155c8b5d9dcSPaul Mundt .right_margin = 16, 156c8b5d9dcSPaul Mundt .upper_margin = 33, 157c8b5d9dcSPaul Mundt .lower_margin = 10, 158c8b5d9dcSPaul Mundt .hsync_len = 39, 159c8b5d9dcSPaul Mundt .vsync_len = 2, 160c8b5d9dcSPaul Mundt .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 161c8b5d9dcSPaul Mundt }; 162c8b5d9dcSPaul Mundt 163c8b5d9dcSPaul Mundt static struct fb_videomode sm501_default_mode_pnl = { 164c8b5d9dcSPaul Mundt .pixclock = 40000, /* 25MHz */ 165c8b5d9dcSPaul Mundt .xres = 640, 166c8b5d9dcSPaul Mundt .yres = 480, 167c8b5d9dcSPaul Mundt .left_margin = 2, 168c8b5d9dcSPaul Mundt .right_margin = 16, 169c8b5d9dcSPaul Mundt .upper_margin = 33, 170c8b5d9dcSPaul Mundt .lower_margin = 10, 171c8b5d9dcSPaul Mundt .hsync_len = 39, 172c8b5d9dcSPaul Mundt .vsync_len = 2, 173c8b5d9dcSPaul Mundt .sync = 0, 174c8b5d9dcSPaul Mundt }; 175c8b5d9dcSPaul Mundt 176c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { 177c8b5d9dcSPaul Mundt .def_bpp = 16, 178c8b5d9dcSPaul Mundt .def_mode = &sm501_default_mode_pnl, 179c8b5d9dcSPaul Mundt .flags = SM501FB_FLAG_USE_INIT_MODE | 180c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWCURSOR | 181c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWACCEL | 182c8b5d9dcSPaul Mundt SM501FB_FLAG_DISABLE_AT_EXIT | 183c8b5d9dcSPaul Mundt SM501FB_FLAG_PANEL_NO_VBIASEN, 184c8b5d9dcSPaul Mundt }; 185c8b5d9dcSPaul Mundt 186c8b5d9dcSPaul Mundt static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { 187c8b5d9dcSPaul Mundt .def_bpp = 16, 188c8b5d9dcSPaul Mundt .def_mode = &sm501_default_mode_crt, 189c8b5d9dcSPaul Mundt .flags = SM501FB_FLAG_USE_INIT_MODE | 190c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWCURSOR | 191c8b5d9dcSPaul Mundt SM501FB_FLAG_USE_HWACCEL | 192c8b5d9dcSPaul Mundt SM501FB_FLAG_DISABLE_AT_EXIT, 193c8b5d9dcSPaul Mundt }; 194c8b5d9dcSPaul Mundt 195c8b5d9dcSPaul Mundt static struct sm501_platdata_fb sm501_fb_pdata = { 196c8b5d9dcSPaul Mundt .fb_route = SM501_FB_OWN, 197c8b5d9dcSPaul Mundt .fb_crt = &sm501_pdata_fbsub_crt, 198c8b5d9dcSPaul Mundt .fb_pnl = &sm501_pdata_fbsub_pnl, 199c8b5d9dcSPaul Mundt }; 200c8b5d9dcSPaul Mundt 201c8b5d9dcSPaul Mundt static struct sm501_initdata sm501_initdata = { 202c8b5d9dcSPaul Mundt .gpio_high = { 203c8b5d9dcSPaul Mundt .set = 0x00001fe0, 204c8b5d9dcSPaul Mundt .mask = 0x0, 205c8b5d9dcSPaul Mundt }, 206c8b5d9dcSPaul Mundt .devices = 0, 207c8b5d9dcSPaul Mundt .mclk = 84 * 1000000, 208c8b5d9dcSPaul Mundt .m1xclk = 112 * 1000000, 209c8b5d9dcSPaul Mundt }; 210c8b5d9dcSPaul Mundt 211c8b5d9dcSPaul Mundt static struct sm501_platdata sm501_platform_data = { 212c8b5d9dcSPaul Mundt .init = &sm501_initdata, 213c8b5d9dcSPaul Mundt .fb = &sm501_fb_pdata, 214c8b5d9dcSPaul Mundt }; 215c8b5d9dcSPaul Mundt 216c8b5d9dcSPaul Mundt static struct platform_device sm501_device = { 217c8b5d9dcSPaul Mundt .name = "sm501", 218c8b5d9dcSPaul Mundt .id = -1, 219c8b5d9dcSPaul Mundt .dev = { 220c8b5d9dcSPaul Mundt .platform_data = &sm501_platform_data, 221c8b5d9dcSPaul Mundt }, 222c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(sm501_resources), 223c8b5d9dcSPaul Mundt .resource = sm501_resources, 224c8b5d9dcSPaul Mundt }; 225c8b5d9dcSPaul Mundt 226c8b5d9dcSPaul Mundt static struct resource i2c_resources[] = { 227c8b5d9dcSPaul Mundt [0] = { 228c8b5d9dcSPaul Mundt .start = PCA9564_ADDR, 229c8b5d9dcSPaul Mundt .end = PCA9564_ADDR + PCA9564_SIZE - 1, 230c8b5d9dcSPaul Mundt .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 231c8b5d9dcSPaul Mundt }, 232c8b5d9dcSPaul Mundt [1] = { 233c8b5d9dcSPaul Mundt .start = 12, 234c8b5d9dcSPaul Mundt .end = 12, 235c8b5d9dcSPaul Mundt .flags = IORESOURCE_IRQ, 236c8b5d9dcSPaul Mundt }, 237c8b5d9dcSPaul Mundt }; 238c8b5d9dcSPaul Mundt 239c8b5d9dcSPaul Mundt static struct i2c_pca9564_pf_platform_data i2c_platform_data = { 240c8b5d9dcSPaul Mundt .gpio = 0, 241c8b5d9dcSPaul Mundt .i2c_clock_speed = I2C_PCA_CON_330kHz, 2428e99ada8SWolfram Sang .timeout = HZ, 243c8b5d9dcSPaul Mundt }; 244c8b5d9dcSPaul Mundt 245c8b5d9dcSPaul Mundt static struct platform_device i2c_device = { 246c8b5d9dcSPaul Mundt .name = "i2c-pca-platform", 247c8b5d9dcSPaul Mundt .id = -1, 248c8b5d9dcSPaul Mundt .dev = { 249c8b5d9dcSPaul Mundt .platform_data = &i2c_platform_data, 250c8b5d9dcSPaul Mundt }, 251c8b5d9dcSPaul Mundt .num_resources = ARRAY_SIZE(i2c_resources), 252c8b5d9dcSPaul Mundt .resource = i2c_resources, 253c8b5d9dcSPaul Mundt }; 254c8b5d9dcSPaul Mundt 255c8b5d9dcSPaul Mundt static struct platform_device *sh7785lcr_devices[] __initdata = { 256c8b5d9dcSPaul Mundt &heartbeat_device, 257c8b5d9dcSPaul Mundt &nor_flash_device, 258c8b5d9dcSPaul Mundt &r8a66597_usb_host_device, 259c8b5d9dcSPaul Mundt &sm501_device, 260c8b5d9dcSPaul Mundt &i2c_device, 261c8b5d9dcSPaul Mundt }; 262c8b5d9dcSPaul Mundt 263c8b5d9dcSPaul Mundt static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { 264c8b5d9dcSPaul Mundt { 265c8b5d9dcSPaul Mundt I2C_BOARD_INFO("r2025sd", 0x32), 266c8b5d9dcSPaul Mundt }, 267c8b5d9dcSPaul Mundt }; 268c8b5d9dcSPaul Mundt 269c8b5d9dcSPaul Mundt static int __init sh7785lcr_devices_setup(void) 270c8b5d9dcSPaul Mundt { 271c8b5d9dcSPaul Mundt i2c_register_board_info(0, sh7785lcr_i2c_devices, 272c8b5d9dcSPaul Mundt ARRAY_SIZE(sh7785lcr_i2c_devices)); 273c8b5d9dcSPaul Mundt 274c8b5d9dcSPaul Mundt return platform_add_devices(sh7785lcr_devices, 275c8b5d9dcSPaul Mundt ARRAY_SIZE(sh7785lcr_devices)); 276c8b5d9dcSPaul Mundt } 277c8b5d9dcSPaul Mundt __initcall(sh7785lcr_devices_setup); 278c8b5d9dcSPaul Mundt 279c8b5d9dcSPaul Mundt /* Initialize IRQ setting */ 280c8b5d9dcSPaul Mundt void __init init_sh7785lcr_IRQ(void) 281c8b5d9dcSPaul Mundt { 282c8b5d9dcSPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRQ7654); 283c8b5d9dcSPaul Mundt plat_irq_setup_pins(IRQ_MODE_IRQ3210); 284c8b5d9dcSPaul Mundt } 285c8b5d9dcSPaul Mundt 286a77b5ac0SPaul Mundt static int sh7785lcr_clk_init(void) 287a77b5ac0SPaul Mundt { 288a77b5ac0SPaul Mundt struct clk *clk; 289a77b5ac0SPaul Mundt int ret; 290a77b5ac0SPaul Mundt 291a77b5ac0SPaul Mundt clk = clk_get(NULL, "extal"); 292a77b5ac0SPaul Mundt if (!clk || IS_ERR(clk)) 293a77b5ac0SPaul Mundt return PTR_ERR(clk); 294a77b5ac0SPaul Mundt ret = clk_set_rate(clk, 33333333); 295a77b5ac0SPaul Mundt clk_put(clk); 296a77b5ac0SPaul Mundt 297a77b5ac0SPaul Mundt return ret; 298a77b5ac0SPaul Mundt } 299a77b5ac0SPaul Mundt 300c8b5d9dcSPaul Mundt static void sh7785lcr_power_off(void) 301c8b5d9dcSPaul Mundt { 302df4d4f1aSYoshihiro Shimoda unsigned char *p; 303df4d4f1aSYoshihiro Shimoda 304df4d4f1aSYoshihiro Shimoda p = ioremap(PLD_POFCR, PLD_POFCR + 1); 305df4d4f1aSYoshihiro Shimoda if (!p) { 306df4d4f1aSYoshihiro Shimoda printk(KERN_ERR "%s: ioremap error.\n", __func__); 307df4d4f1aSYoshihiro Shimoda return; 308df4d4f1aSYoshihiro Shimoda } 309df4d4f1aSYoshihiro Shimoda *p = 0x01; 310df4d4f1aSYoshihiro Shimoda iounmap(p); 311600fa578SMagnus Damm set_bl_bit(); 312600fa578SMagnus Damm while (1) 313600fa578SMagnus Damm cpu_relax(); 314c8b5d9dcSPaul Mundt } 315c8b5d9dcSPaul Mundt 316c8b5d9dcSPaul Mundt /* Initialize the board */ 317c8b5d9dcSPaul Mundt static void __init sh7785lcr_setup(char **cmdline_p) 318c8b5d9dcSPaul Mundt { 319c8b5d9dcSPaul Mundt void __iomem *sm501_reg; 320c8b5d9dcSPaul Mundt 321c8b5d9dcSPaul Mundt printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); 322c8b5d9dcSPaul Mundt 323c8b5d9dcSPaul Mundt pm_power_off = sh7785lcr_power_off; 324c8b5d9dcSPaul Mundt 325c8b5d9dcSPaul Mundt /* sm501 DRAM configuration */ 326c8b5d9dcSPaul Mundt sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; 327c8b5d9dcSPaul Mundt writel(0x000307c2, sm501_reg); 328c8b5d9dcSPaul Mundt } 329c8b5d9dcSPaul Mundt 33063d12e23SMagnus Damm /* Return the board specific boot mode pin configuration */ 33163d12e23SMagnus Damm static int sh7785lcr_mode_pins(void) 33263d12e23SMagnus Damm { 33363d12e23SMagnus Damm int value = 0; 33463d12e23SMagnus Damm 33563d12e23SMagnus Damm /* These are the factory default settings of S1 and S2. 33663d12e23SMagnus Damm * If you change these dip switches then you will need to 33763d12e23SMagnus Damm * adjust the values below as well. 33863d12e23SMagnus Damm */ 3390d4fdbb6SMagnus Damm value |= MODE_PIN4; /* Clock Mode 16 */ 3400d4fdbb6SMagnus Damm value |= MODE_PIN5; /* 32-bit Area0 bus width */ 3410d4fdbb6SMagnus Damm value |= MODE_PIN6; /* 32-bit Area0 bus width */ 3420d4fdbb6SMagnus Damm value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ 3430d4fdbb6SMagnus Damm value |= MODE_PIN8; /* Little Endian */ 3440d4fdbb6SMagnus Damm value |= MODE_PIN9; /* Master Mode */ 3450d4fdbb6SMagnus Damm value |= MODE_PIN14; /* No PLL step-up */ 34663d12e23SMagnus Damm 34763d12e23SMagnus Damm return value; 34863d12e23SMagnus Damm } 34963d12e23SMagnus Damm 350c8b5d9dcSPaul Mundt /* 351c8b5d9dcSPaul Mundt * The Machine Vector 352c8b5d9dcSPaul Mundt */ 353c8b5d9dcSPaul Mundt static struct sh_machine_vector mv_sh7785lcr __initmv = { 354c8b5d9dcSPaul Mundt .mv_name = "SH7785LCR", 355c8b5d9dcSPaul Mundt .mv_setup = sh7785lcr_setup, 356a77b5ac0SPaul Mundt .mv_clk_init = sh7785lcr_clk_init, 357c8b5d9dcSPaul Mundt .mv_init_irq = init_sh7785lcr_IRQ, 35863d12e23SMagnus Damm .mv_mode_pins = sh7785lcr_mode_pins, 359c8b5d9dcSPaul Mundt }; 360c8b5d9dcSPaul Mundt 361