1 /* 2 * arch/ppc/platforms/setup.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Adapted from 'alpha' version by Gary Thomas 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 */ 8 9 /* 10 * bootup setup stuff.. 11 */ 12 13 #include <linux/config.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/mm.h> 18 #include <linux/stddef.h> 19 #include <linux/unistd.h> 20 #include <linux/ptrace.h> 21 #include <linux/slab.h> 22 #include <linux/user.h> 23 #include <linux/a.out.h> 24 #include <linux/tty.h> 25 #include <linux/major.h> 26 #include <linux/interrupt.h> 27 #include <linux/reboot.h> 28 #include <linux/init.h> 29 #include <linux/pci.h> 30 #include <linux/version.h> 31 #include <linux/adb.h> 32 #include <linux/module.h> 33 #include <linux/delay.h> 34 #include <linux/ide.h> 35 #include <linux/console.h> 36 #include <linux/seq_file.h> 37 #include <linux/root_dev.h> 38 #include <linux/initrd.h> 39 #include <linux/module.h> 40 41 #include <asm/io.h> 42 #include <asm/pgtable.h> 43 #include <asm/prom.h> 44 #include <asm/gg2.h> 45 #include <asm/pci-bridge.h> 46 #include <asm/dma.h> 47 #include <asm/machdep.h> 48 #include <asm/irq.h> 49 #include <asm/hydra.h> 50 #include <asm/sections.h> 51 #include <asm/time.h> 52 #include <asm/btext.h> 53 #include <asm/i8259.h> 54 #include <asm/mpic.h> 55 #include <asm/rtas.h> 56 #include <asm/xmon.h> 57 58 #include "chrp.h" 59 60 void rtas_indicator_progress(char *, unsigned short); 61 void btext_progress(char *, unsigned short); 62 63 int _chrp_type; 64 EXPORT_SYMBOL(_chrp_type); 65 66 struct mpic *chrp_mpic; 67 68 /* 69 * XXX this should be in xmon.h, but putting it there means xmon.h 70 * has to include <linux/interrupt.h> (to get irqreturn_t), which 71 * causes all sorts of problems. -- paulus 72 */ 73 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); 74 75 extern unsigned long loops_per_jiffy; 76 77 #ifdef CONFIG_SMP 78 extern struct smp_ops_t chrp_smp_ops; 79 #endif 80 81 static const char *gg2_memtypes[4] = { 82 "FPM", "SDRAM", "EDO", "BEDO" 83 }; 84 static const char *gg2_cachesizes[4] = { 85 "256 KB", "512 KB", "1 MB", "Reserved" 86 }; 87 static const char *gg2_cachetypes[4] = { 88 "Asynchronous", "Reserved", "Flow-Through Synchronous", 89 "Pipelined Synchronous" 90 }; 91 static const char *gg2_cachemodes[4] = { 92 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" 93 }; 94 95 void chrp_show_cpuinfo(struct seq_file *m) 96 { 97 int i, sdramen; 98 unsigned int t; 99 struct device_node *root; 100 const char *model = ""; 101 102 root = find_path_device("/"); 103 if (root) 104 model = get_property(root, "model", NULL); 105 seq_printf(m, "machine\t\t: CHRP %s\n", model); 106 107 /* longtrail (goldengate) stuff */ 108 if (!strncmp(model, "IBM,LongTrail", 13)) { 109 /* VLSI VAS96011/12 `Golden Gate 2' */ 110 /* Memory banks */ 111 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) 112 >>31) & 1; 113 for (i = 0; i < (sdramen ? 4 : 6); i++) { 114 t = in_le32(gg2_pci_config_base+ 115 GG2_PCI_DRAM_BANK0+ 116 i*4); 117 if (!(t & 1)) 118 continue; 119 switch ((t>>8) & 0x1f) { 120 case 0x1f: 121 model = "4 MB"; 122 break; 123 case 0x1e: 124 model = "8 MB"; 125 break; 126 case 0x1c: 127 model = "16 MB"; 128 break; 129 case 0x18: 130 model = "32 MB"; 131 break; 132 case 0x10: 133 model = "64 MB"; 134 break; 135 case 0x00: 136 model = "128 MB"; 137 break; 138 default: 139 model = "Reserved"; 140 break; 141 } 142 seq_printf(m, "memory bank %d\t: %s %s\n", i, model, 143 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); 144 } 145 /* L2 cache */ 146 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); 147 seq_printf(m, "board l2\t: %s %s (%s)\n", 148 gg2_cachesizes[(t>>7) & 3], 149 gg2_cachetypes[(t>>2) & 3], 150 gg2_cachemodes[t & 3]); 151 } 152 } 153 154 /* 155 * Fixes for the National Semiconductor PC78308VUL SuperI/O 156 * 157 * Some versions of Open Firmware incorrectly initialize the IRQ settings 158 * for keyboard and mouse 159 */ 160 static inline void __init sio_write(u8 val, u8 index) 161 { 162 outb(index, 0x15c); 163 outb(val, 0x15d); 164 } 165 166 static inline u8 __init sio_read(u8 index) 167 { 168 outb(index, 0x15c); 169 return inb(0x15d); 170 } 171 172 static void __init sio_fixup_irq(const char *name, u8 device, u8 level, 173 u8 type) 174 { 175 u8 level0, type0, active; 176 177 /* select logical device */ 178 sio_write(device, 0x07); 179 active = sio_read(0x30); 180 level0 = sio_read(0x70); 181 type0 = sio_read(0x71); 182 if (level0 != level || type0 != type || !active) { 183 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " 184 "remapping to level %d, type %d, active\n", 185 name, level0, type0, !active ? "in" : "", level, type); 186 sio_write(0x01, 0x30); 187 sio_write(level, 0x70); 188 sio_write(type, 0x71); 189 } 190 } 191 192 static void __init sio_init(void) 193 { 194 struct device_node *root; 195 196 if ((root = find_path_device("/")) && 197 !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) { 198 /* logical device 0 (KBC/Keyboard) */ 199 sio_fixup_irq("keyboard", 0, 1, 2); 200 /* select logical device 1 (KBC/Mouse) */ 201 sio_fixup_irq("mouse", 1, 12, 2); 202 } 203 } 204 205 206 static void __init pegasos_set_l2cr(void) 207 { 208 struct device_node *np; 209 210 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ 211 if (_chrp_type != _CHRP_Pegasos) 212 return; 213 214 /* Enable L2 cache if needed */ 215 np = find_type_devices("cpu"); 216 if (np != NULL) { 217 unsigned int *l2cr = (unsigned int *) 218 get_property (np, "l2cr", NULL); 219 if (l2cr == NULL) { 220 printk ("Pegasos l2cr : no cpu l2cr property found\n"); 221 return; 222 } 223 if (!((*l2cr) & 0x80000000)) { 224 printk ("Pegasos l2cr : L2 cache was not active, " 225 "activating\n"); 226 _set_L2CR(0); 227 _set_L2CR((*l2cr) | 0x80000000); 228 } 229 } 230 } 231 232 void __init chrp_setup_arch(void) 233 { 234 struct device_node *root = find_path_device ("/"); 235 char *machine = NULL; 236 struct device_node *device; 237 unsigned int *p = NULL; 238 239 /* init to some ~sane value until calibrate_delay() runs */ 240 loops_per_jiffy = 50000000/HZ; 241 242 if (root) 243 machine = get_property(root, "model", NULL); 244 if (machine && strncmp(machine, "Pegasos", 7) == 0) { 245 _chrp_type = _CHRP_Pegasos; 246 } else if (machine && strncmp(machine, "IBM", 3) == 0) { 247 _chrp_type = _CHRP_IBM; 248 } else if (machine && strncmp(machine, "MOT", 3) == 0) { 249 _chrp_type = _CHRP_Motorola; 250 } else { 251 /* Let's assume it is an IBM chrp if all else fails */ 252 _chrp_type = _CHRP_IBM; 253 } 254 printk("chrp type = %x\n", _chrp_type); 255 256 rtas_initialize(); 257 if (rtas_token("display-character") >= 0) 258 ppc_md.progress = rtas_progress; 259 260 #ifdef CONFIG_BOOTX_TEXT 261 if (ppc_md.progress == NULL && boot_text_mapped) 262 ppc_md.progress = btext_progress; 263 #endif 264 265 #ifdef CONFIG_BLK_DEV_INITRD 266 /* this is fine for chrp */ 267 initrd_below_start_ok = 1; 268 269 if (initrd_start) 270 ROOT_DEV = Root_RAM0; 271 else 272 #endif 273 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ 274 275 /* On pegasos, enable the L2 cache if not already done by OF */ 276 pegasos_set_l2cr(); 277 278 /* Lookup PCI host bridges */ 279 chrp_find_bridges(); 280 281 /* 282 * Temporary fixes for PCI devices. 283 * -- Geert 284 */ 285 hydra_init(); /* Mac I/O */ 286 287 /* 288 * Fix the Super I/O configuration 289 */ 290 sio_init(); 291 292 /* Get the event scan rate for the rtas so we know how 293 * often it expects a heartbeat. -- Cort 294 */ 295 device = find_devices("rtas"); 296 if (device) 297 p = (unsigned int *) get_property 298 (device, "rtas-event-scan-rate", NULL); 299 if (p && *p) { 300 ppc_md.heartbeat = chrp_event_scan; 301 ppc_md.heartbeat_reset = HZ / (*p * 30) - 1; 302 ppc_md.heartbeat_count = 1; 303 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", 304 *p, ppc_md.heartbeat_reset); 305 } 306 307 pci_create_OF_bus_map(); 308 309 /* 310 * Print the banner, then scroll down so boot progress 311 * can be printed. -- Cort 312 */ 313 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); 314 } 315 316 void 317 chrp_event_scan(void) 318 { 319 unsigned char log[1024]; 320 int ret = 0; 321 322 /* XXX: we should loop until the hardware says no more error logs -- Cort */ 323 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, 324 __pa(log), 1024); 325 ppc_md.heartbeat_count = ppc_md.heartbeat_reset; 326 } 327 328 /* 329 * Finds the open-pic node and sets up the mpic driver. 330 */ 331 static void __init chrp_find_openpic(void) 332 { 333 struct device_node *np, *root; 334 int len, i, j, irq_count; 335 int isu_size, idu_size; 336 unsigned int *iranges, *opprop = NULL; 337 int oplen = 0; 338 unsigned long opaddr; 339 int na = 1; 340 unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS]; 341 342 np = find_type_devices("open-pic"); 343 if (np == NULL) 344 return; 345 root = find_path_device("/"); 346 if (root) { 347 opprop = (unsigned int *) get_property 348 (root, "platform-open-pic", &oplen); 349 na = prom_n_addr_cells(root); 350 } 351 if (opprop && oplen >= na * sizeof(unsigned int)) { 352 opaddr = opprop[na-1]; /* assume 32-bit */ 353 oplen /= na * sizeof(unsigned int); 354 } else { 355 if (np->n_addrs == 0) 356 return; 357 opaddr = np->addrs[0].address; 358 oplen = 0; 359 } 360 361 printk(KERN_INFO "OpenPIC at %lx\n", opaddr); 362 363 irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */ 364 prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS - 4); 365 366 iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len); 367 if (iranges == NULL) 368 len = 0; /* non-distributed mpic */ 369 else 370 len /= 2 * sizeof(unsigned int); 371 372 /* 373 * The first pair of cells in interrupt-ranges refers to the 374 * IDU; subsequent pairs refer to the ISUs. 375 */ 376 if (oplen < len) { 377 printk(KERN_ERR "Insufficient addresses for distributed" 378 " OpenPIC (%d < %d)\n", np->n_addrs, len); 379 len = oplen; 380 } 381 382 isu_size = 0; 383 idu_size = 0; 384 if (len > 0 && iranges[1] != 0) { 385 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", 386 iranges[0], iranges[0] + iranges[1] - 1); 387 idu_size = iranges[1]; 388 } 389 if (len > 1) 390 isu_size = iranges[3]; 391 392 chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY, 393 isu_size, NUM_ISA_INTERRUPTS, irq_count, 394 NR_IRQS - 4, init_senses, irq_count, 395 " MPIC "); 396 if (chrp_mpic == NULL) { 397 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 398 return; 399 } 400 401 j = na - 1; 402 for (i = 1; i < len; ++i) { 403 iranges += 2; 404 j += na; 405 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", 406 iranges[0], iranges[0] + iranges[1] - 1, 407 opprop[j]); 408 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); 409 } 410 411 mpic_init(chrp_mpic); 412 mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL); 413 } 414 415 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 416 static struct irqaction xmon_irqaction = { 417 .handler = xmon_irq, 418 .mask = CPU_MASK_NONE, 419 .name = "XMON break", 420 }; 421 #endif 422 423 void __init chrp_init_IRQ(void) 424 { 425 struct device_node *np; 426 unsigned long chrp_int_ack = 0; 427 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 428 struct device_node *kbd; 429 #endif 430 431 for (np = find_devices("pci"); np != NULL; np = np->next) { 432 unsigned int *addrp = (unsigned int *) 433 get_property(np, "8259-interrupt-acknowledge", NULL); 434 435 if (addrp == NULL) 436 continue; 437 chrp_int_ack = addrp[prom_n_addr_cells(np)-1]; 438 break; 439 } 440 if (np == NULL) 441 printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n"); 442 443 chrp_find_openpic(); 444 445 i8259_init(chrp_int_ack, 0); 446 447 if (_chrp_type == _CHRP_Pegasos) 448 ppc_md.get_irq = i8259_irq; 449 else 450 ppc_md.get_irq = mpic_get_irq; 451 452 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) 453 /* see if there is a keyboard in the device tree 454 with a parent of type "adb" */ 455 for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next) 456 if (kbd->parent && kbd->parent->type 457 && strcmp(kbd->parent->type, "adb") == 0) 458 break; 459 if (kbd) 460 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); 461 #endif 462 } 463 464 void __init 465 chrp_init2(void) 466 { 467 #ifdef CONFIG_NVRAM 468 chrp_nvram_init(); 469 #endif 470 471 request_region(0x20,0x20,"pic1"); 472 request_region(0xa0,0x20,"pic2"); 473 request_region(0x00,0x20,"dma1"); 474 request_region(0x40,0x20,"timer"); 475 request_region(0x80,0x10,"dma page reg"); 476 request_region(0xc0,0x20,"dma2"); 477 478 if (ppc_md.progress) 479 ppc_md.progress(" Have fun! ", 0x7777); 480 } 481 482 void __init chrp_init(void) 483 { 484 ISA_DMA_THRESHOLD = ~0L; 485 DMA_MODE_READ = 0x44; 486 DMA_MODE_WRITE = 0x48; 487 isa_io_base = CHRP_ISA_IO_BASE; /* default value */ 488 ppc_do_canonicalize_irqs = 1; 489 490 /* Assume we have an 8259... */ 491 __irq_offset_value = NUM_ISA_INTERRUPTS; 492 493 ppc_md.setup_arch = chrp_setup_arch; 494 ppc_md.show_cpuinfo = chrp_show_cpuinfo; 495 496 ppc_md.init_IRQ = chrp_init_IRQ; 497 ppc_md.init = chrp_init2; 498 499 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 500 501 ppc_md.restart = rtas_restart; 502 ppc_md.power_off = rtas_power_off; 503 ppc_md.halt = rtas_halt; 504 505 ppc_md.time_init = chrp_time_init; 506 ppc_md.set_rtc_time = chrp_set_rtc_time; 507 ppc_md.get_rtc_time = chrp_get_rtc_time; 508 ppc_md.calibrate_decr = chrp_calibrate_decr; 509 510 #ifdef CONFIG_SMP 511 smp_ops = &chrp_smp_ops; 512 #endif /* CONFIG_SMP */ 513 } 514 515 #ifdef CONFIG_BOOTX_TEXT 516 void 517 btext_progress(char *s, unsigned short hex) 518 { 519 btext_drawstring(s); 520 btext_drawstring("\n"); 521 } 522 #endif /* CONFIG_BOOTX_TEXT */ 523