xref: /linux/arch/powerpc/platforms/8xx/mpc885ads.h (revision e5451c8f8330e03ad3cfa16048b4daf961af434f)
1*df34403dSVitaly Bordug /*
2*df34403dSVitaly Bordug  * A collection of structures, addresses, and values associated with
3*df34403dSVitaly Bordug  * the Freescale MPC885ADS board.
4*df34403dSVitaly Bordug  * Copied from the FADS stuff.
5*df34403dSVitaly Bordug  *
6*df34403dSVitaly Bordug  * Author: MontaVista Software, Inc.
7*df34403dSVitaly Bordug  *         source@mvista.com
8*df34403dSVitaly Bordug  *
9*df34403dSVitaly Bordug  * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
10*df34403dSVitaly Bordug  * terms of the GNU General Public License version 2.  This program is licensed
11*df34403dSVitaly Bordug  * "as is" without any warranty of any kind, whether express or implied.
12*df34403dSVitaly Bordug  */
13*df34403dSVitaly Bordug 
14*df34403dSVitaly Bordug #ifdef __KERNEL__
15*df34403dSVitaly Bordug #ifndef __ASM_MPC885ADS_H__
16*df34403dSVitaly Bordug #define __ASM_MPC885ADS_H__
17*df34403dSVitaly Bordug 
18*df34403dSVitaly Bordug #include <sysdev/fsl_soc.h>
19*df34403dSVitaly Bordug 
20*df34403dSVitaly Bordug /* Bits of interest in the BCSRs.
21*df34403dSVitaly Bordug  */
22*df34403dSVitaly Bordug #define BCSR1_ETHEN		((uint)0x20000000)
23*df34403dSVitaly Bordug #define BCSR1_IRDAEN		((uint)0x10000000)
24*df34403dSVitaly Bordug #define BCSR1_RS232EN_1		((uint)0x01000000)
25*df34403dSVitaly Bordug #define BCSR1_PCCEN		((uint)0x00800000)
26*df34403dSVitaly Bordug #define BCSR1_PCCVCC0		((uint)0x00400000)
27*df34403dSVitaly Bordug #define BCSR1_PCCVPP0		((uint)0x00200000)
28*df34403dSVitaly Bordug #define BCSR1_PCCVPP1		((uint)0x00100000)
29*df34403dSVitaly Bordug #define BCSR1_PCCVPP_MASK	(BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
30*df34403dSVitaly Bordug #define BCSR1_RS232EN_2		((uint)0x00040000)
31*df34403dSVitaly Bordug #define BCSR1_PCCVCC1		((uint)0x00010000)
32*df34403dSVitaly Bordug #define BCSR1_PCCVCC_MASK	(BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
33*df34403dSVitaly Bordug 
34*df34403dSVitaly Bordug #define BCSR4_ETH10_RST		((uint)0x80000000)	/* 10Base-T PHY reset*/
35*df34403dSVitaly Bordug #define BCSR4_USB_LO_SPD	((uint)0x04000000)
36*df34403dSVitaly Bordug #define BCSR4_USB_VCC		((uint)0x02000000)
37*df34403dSVitaly Bordug #define BCSR4_USB_FULL_SPD	((uint)0x00040000)
38*df34403dSVitaly Bordug #define BCSR4_USB_EN		((uint)0x00020000)
39*df34403dSVitaly Bordug 
40*df34403dSVitaly Bordug #define BCSR5_MII2_EN		0x40
41*df34403dSVitaly Bordug #define BCSR5_MII2_RST		0x20
42*df34403dSVitaly Bordug #define BCSR5_T1_RST		0x10
43*df34403dSVitaly Bordug #define BCSR5_ATM155_RST	0x08
44*df34403dSVitaly Bordug #define BCSR5_ATM25_RST		0x04
45*df34403dSVitaly Bordug #define BCSR5_MII1_EN		0x02
46*df34403dSVitaly Bordug #define BCSR5_MII1_RST		0x01
47*df34403dSVitaly Bordug 
48*df34403dSVitaly Bordug #endif /* __ASM_MPC885ADS_H__ */
49*df34403dSVitaly Bordug #endif /* __KERNEL__ */
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