1 /* 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * Modified by Cort Dougan (cort@cs.nmt.edu) 10 * and Paul Mackerras (paulus@samba.org) 11 */ 12 13 /* 14 * This file handles the architecture-dependent parts of hardware exceptions 15 */ 16 17 #include <linux/config.h> 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/kernel.h> 21 #include <linux/mm.h> 22 #include <linux/stddef.h> 23 #include <linux/unistd.h> 24 #include <linux/ptrace.h> 25 #include <linux/slab.h> 26 #include <linux/user.h> 27 #include <linux/a.out.h> 28 #include <linux/interrupt.h> 29 #include <linux/init.h> 30 #include <linux/module.h> 31 #include <linux/prctl.h> 32 #include <linux/delay.h> 33 #include <linux/kprobes.h> 34 #include <linux/kexec.h> 35 36 #include <asm/kdebug.h> 37 #include <asm/pgtable.h> 38 #include <asm/uaccess.h> 39 #include <asm/system.h> 40 #include <asm/io.h> 41 #include <asm/machdep.h> 42 #include <asm/rtas.h> 43 #include <asm/pmc.h> 44 #ifdef CONFIG_PPC32 45 #include <asm/reg.h> 46 #endif 47 #ifdef CONFIG_PMAC_BACKLIGHT 48 #include <asm/backlight.h> 49 #endif 50 #ifdef CONFIG_PPC64 51 #include <asm/firmware.h> 52 #include <asm/processor.h> 53 #endif 54 55 #ifdef CONFIG_PPC64 /* XXX */ 56 #define _IO_BASE pci_io_base 57 #endif 58 59 #ifdef CONFIG_DEBUGGER 60 int (*__debugger)(struct pt_regs *regs); 61 int (*__debugger_ipi)(struct pt_regs *regs); 62 int (*__debugger_bpt)(struct pt_regs *regs); 63 int (*__debugger_sstep)(struct pt_regs *regs); 64 int (*__debugger_iabr_match)(struct pt_regs *regs); 65 int (*__debugger_dabr_match)(struct pt_regs *regs); 66 int (*__debugger_fault_handler)(struct pt_regs *regs); 67 68 EXPORT_SYMBOL(__debugger); 69 EXPORT_SYMBOL(__debugger_ipi); 70 EXPORT_SYMBOL(__debugger_bpt); 71 EXPORT_SYMBOL(__debugger_sstep); 72 EXPORT_SYMBOL(__debugger_iabr_match); 73 EXPORT_SYMBOL(__debugger_dabr_match); 74 EXPORT_SYMBOL(__debugger_fault_handler); 75 #endif 76 77 ATOMIC_NOTIFIER_HEAD(powerpc_die_chain); 78 79 int register_die_notifier(struct notifier_block *nb) 80 { 81 return atomic_notifier_chain_register(&powerpc_die_chain, nb); 82 } 83 EXPORT_SYMBOL(register_die_notifier); 84 85 int unregister_die_notifier(struct notifier_block *nb) 86 { 87 return atomic_notifier_chain_unregister(&powerpc_die_chain, nb); 88 } 89 EXPORT_SYMBOL(unregister_die_notifier); 90 91 /* 92 * Trap & Exception support 93 */ 94 95 static DEFINE_SPINLOCK(die_lock); 96 97 int die(const char *str, struct pt_regs *regs, long err) 98 { 99 static int die_counter, crash_dump_start = 0; 100 101 if (debugger(regs)) 102 return 1; 103 104 console_verbose(); 105 spin_lock_irq(&die_lock); 106 bust_spinlocks(1); 107 #ifdef CONFIG_PMAC_BACKLIGHT 108 if (machine_is(powermac)) { 109 set_backlight_enable(1); 110 set_backlight_level(BACKLIGHT_MAX); 111 } 112 #endif 113 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); 114 #ifdef CONFIG_PREEMPT 115 printk("PREEMPT "); 116 #endif 117 #ifdef CONFIG_SMP 118 printk("SMP NR_CPUS=%d ", NR_CPUS); 119 #endif 120 #ifdef CONFIG_DEBUG_PAGEALLOC 121 printk("DEBUG_PAGEALLOC "); 122 #endif 123 #ifdef CONFIG_NUMA 124 printk("NUMA "); 125 #endif 126 printk("%s\n", ppc_md.name ? "" : ppc_md.name); 127 128 print_modules(); 129 show_regs(regs); 130 bust_spinlocks(0); 131 132 if (!crash_dump_start && kexec_should_crash(current)) { 133 crash_dump_start = 1; 134 spin_unlock_irq(&die_lock); 135 crash_kexec(regs); 136 /* NOTREACHED */ 137 } 138 spin_unlock_irq(&die_lock); 139 if (crash_dump_start) 140 /* 141 * Only for soft-reset: Other CPUs will be responded to an IPI 142 * sent by first kexec CPU. 143 */ 144 for(;;) 145 ; 146 147 if (in_interrupt()) 148 panic("Fatal exception in interrupt"); 149 150 if (panic_on_oops) { 151 #ifdef CONFIG_PPC64 152 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 153 ssleep(5); 154 #endif 155 panic("Fatal exception"); 156 } 157 do_exit(err); 158 159 return 0; 160 } 161 162 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) 163 { 164 siginfo_t info; 165 166 if (!user_mode(regs)) { 167 if (die("Exception in kernel mode", regs, signr)) 168 return; 169 } 170 171 memset(&info, 0, sizeof(info)); 172 info.si_signo = signr; 173 info.si_code = code; 174 info.si_addr = (void __user *) addr; 175 force_sig_info(signr, &info, current); 176 177 /* 178 * Init gets no signals that it doesn't have a handler for. 179 * That's all very well, but if it has caused a synchronous 180 * exception and we ignore the resulting signal, it will just 181 * generate the same exception over and over again and we get 182 * nowhere. Better to kill it and let the kernel panic. 183 */ 184 if (current->pid == 1) { 185 __sighandler_t handler; 186 187 spin_lock_irq(¤t->sighand->siglock); 188 handler = current->sighand->action[signr-1].sa.sa_handler; 189 spin_unlock_irq(¤t->sighand->siglock); 190 if (handler == SIG_DFL) { 191 /* init has generated a synchronous exception 192 and it doesn't have a handler for the signal */ 193 printk(KERN_CRIT "init has generated signal %d " 194 "but has no handler for it\n", signr); 195 do_exit(signr); 196 } 197 } 198 } 199 200 #ifdef CONFIG_PPC64 201 void system_reset_exception(struct pt_regs *regs) 202 { 203 /* See if any machine dependent calls */ 204 if (ppc_md.system_reset_exception) { 205 if (ppc_md.system_reset_exception(regs)) 206 return; 207 } 208 209 die("System Reset", regs, SIGABRT); 210 211 /* Must die if the interrupt is not recoverable */ 212 if (!(regs->msr & MSR_RI)) 213 panic("Unrecoverable System Reset"); 214 215 /* What should we do here? We could issue a shutdown or hard reset. */ 216 } 217 #endif 218 219 /* 220 * I/O accesses can cause machine checks on powermacs. 221 * Check if the NIP corresponds to the address of a sync 222 * instruction for which there is an entry in the exception 223 * table. 224 * Note that the 601 only takes a machine check on TEA 225 * (transfer error ack) signal assertion, and does not 226 * set any of the top 16 bits of SRR1. 227 * -- paulus. 228 */ 229 static inline int check_io_access(struct pt_regs *regs) 230 { 231 #ifdef CONFIG_PPC_PMAC 232 unsigned long msr = regs->msr; 233 const struct exception_table_entry *entry; 234 unsigned int *nip = (unsigned int *)regs->nip; 235 236 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) 237 && (entry = search_exception_tables(regs->nip)) != NULL) { 238 /* 239 * Check that it's a sync instruction, or somewhere 240 * in the twi; isync; nop sequence that inb/inw/inl uses. 241 * As the address is in the exception table 242 * we should be able to read the instr there. 243 * For the debug message, we look at the preceding 244 * load or store. 245 */ 246 if (*nip == 0x60000000) /* nop */ 247 nip -= 2; 248 else if (*nip == 0x4c00012c) /* isync */ 249 --nip; 250 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { 251 /* sync or twi */ 252 unsigned int rb; 253 254 --nip; 255 rb = (*nip >> 11) & 0x1f; 256 printk(KERN_DEBUG "%s bad port %lx at %p\n", 257 (*nip & 0x100)? "OUT to": "IN from", 258 regs->gpr[rb] - _IO_BASE, nip); 259 regs->msr |= MSR_RI; 260 regs->nip = entry->fixup; 261 return 1; 262 } 263 } 264 #endif /* CONFIG_PPC_PMAC */ 265 return 0; 266 } 267 268 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 269 /* On 4xx, the reason for the machine check or program exception 270 is in the ESR. */ 271 #define get_reason(regs) ((regs)->dsisr) 272 #ifndef CONFIG_FSL_BOOKE 273 #define get_mc_reason(regs) ((regs)->dsisr) 274 #else 275 #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) 276 #endif 277 #define REASON_FP ESR_FP 278 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) 279 #define REASON_PRIVILEGED ESR_PPR 280 #define REASON_TRAP ESR_PTR 281 282 /* single-step stuff */ 283 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 284 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 285 286 #else 287 /* On non-4xx, the reason for the machine check or program 288 exception is in the MSR. */ 289 #define get_reason(regs) ((regs)->msr) 290 #define get_mc_reason(regs) ((regs)->msr) 291 #define REASON_FP 0x100000 292 #define REASON_ILLEGAL 0x80000 293 #define REASON_PRIVILEGED 0x40000 294 #define REASON_TRAP 0x20000 295 296 #define single_stepping(regs) ((regs)->msr & MSR_SE) 297 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) 298 #endif 299 300 /* 301 * This is "fall-back" implementation for configurations 302 * which don't provide platform-specific machine check info 303 */ 304 void __attribute__ ((weak)) 305 platform_machine_check(struct pt_regs *regs) 306 { 307 } 308 309 void machine_check_exception(struct pt_regs *regs) 310 { 311 #ifdef CONFIG_PPC64 312 int recover = 0; 313 314 /* See if any machine dependent calls */ 315 if (ppc_md.machine_check_exception) 316 recover = ppc_md.machine_check_exception(regs); 317 318 if (recover) 319 return; 320 #else 321 unsigned long reason = get_mc_reason(regs); 322 323 if (user_mode(regs)) { 324 regs->msr |= MSR_RI; 325 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); 326 return; 327 } 328 329 #if defined(CONFIG_8xx) && defined(CONFIG_PCI) 330 /* the qspan pci read routines can cause machine checks -- Cort */ 331 bad_page_fault(regs, regs->dar, SIGBUS); 332 return; 333 #endif 334 335 if (debugger_fault_handler(regs)) { 336 regs->msr |= MSR_RI; 337 return; 338 } 339 340 if (check_io_access(regs)) 341 return; 342 343 #if defined(CONFIG_4xx) && !defined(CONFIG_440A) 344 if (reason & ESR_IMCP) { 345 printk("Instruction"); 346 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 347 } else 348 printk("Data"); 349 printk(" machine check in kernel mode.\n"); 350 #elif defined(CONFIG_440A) 351 printk("Machine check in kernel mode.\n"); 352 if (reason & ESR_IMCP){ 353 printk("Instruction Synchronous Machine Check exception\n"); 354 mtspr(SPRN_ESR, reason & ~ESR_IMCP); 355 } 356 else { 357 u32 mcsr = mfspr(SPRN_MCSR); 358 if (mcsr & MCSR_IB) 359 printk("Instruction Read PLB Error\n"); 360 if (mcsr & MCSR_DRB) 361 printk("Data Read PLB Error\n"); 362 if (mcsr & MCSR_DWB) 363 printk("Data Write PLB Error\n"); 364 if (mcsr & MCSR_TLBP) 365 printk("TLB Parity Error\n"); 366 if (mcsr & MCSR_ICP){ 367 flush_instruction_cache(); 368 printk("I-Cache Parity Error\n"); 369 } 370 if (mcsr & MCSR_DCSP) 371 printk("D-Cache Search Parity Error\n"); 372 if (mcsr & MCSR_DCFP) 373 printk("D-Cache Flush Parity Error\n"); 374 if (mcsr & MCSR_IMPE) 375 printk("Machine Check exception is imprecise\n"); 376 377 /* Clear MCSR */ 378 mtspr(SPRN_MCSR, mcsr); 379 } 380 #elif defined (CONFIG_E500) 381 printk("Machine check in kernel mode.\n"); 382 printk("Caused by (from MCSR=%lx): ", reason); 383 384 if (reason & MCSR_MCP) 385 printk("Machine Check Signal\n"); 386 if (reason & MCSR_ICPERR) 387 printk("Instruction Cache Parity Error\n"); 388 if (reason & MCSR_DCP_PERR) 389 printk("Data Cache Push Parity Error\n"); 390 if (reason & MCSR_DCPERR) 391 printk("Data Cache Parity Error\n"); 392 if (reason & MCSR_GL_CI) 393 printk("Guarded Load or Cache-Inhibited stwcx.\n"); 394 if (reason & MCSR_BUS_IAERR) 395 printk("Bus - Instruction Address Error\n"); 396 if (reason & MCSR_BUS_RAERR) 397 printk("Bus - Read Address Error\n"); 398 if (reason & MCSR_BUS_WAERR) 399 printk("Bus - Write Address Error\n"); 400 if (reason & MCSR_BUS_IBERR) 401 printk("Bus - Instruction Data Error\n"); 402 if (reason & MCSR_BUS_RBERR) 403 printk("Bus - Read Data Bus Error\n"); 404 if (reason & MCSR_BUS_WBERR) 405 printk("Bus - Read Data Bus Error\n"); 406 if (reason & MCSR_BUS_IPERR) 407 printk("Bus - Instruction Parity Error\n"); 408 if (reason & MCSR_BUS_RPERR) 409 printk("Bus - Read Parity Error\n"); 410 #elif defined (CONFIG_E200) 411 printk("Machine check in kernel mode.\n"); 412 printk("Caused by (from MCSR=%lx): ", reason); 413 414 if (reason & MCSR_MCP) 415 printk("Machine Check Signal\n"); 416 if (reason & MCSR_CP_PERR) 417 printk("Cache Push Parity Error\n"); 418 if (reason & MCSR_CPERR) 419 printk("Cache Parity Error\n"); 420 if (reason & MCSR_EXCP_ERR) 421 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); 422 if (reason & MCSR_BUS_IRERR) 423 printk("Bus - Read Bus Error on instruction fetch\n"); 424 if (reason & MCSR_BUS_DRERR) 425 printk("Bus - Read Bus Error on data load\n"); 426 if (reason & MCSR_BUS_WRERR) 427 printk("Bus - Write Bus Error on buffered store or cache line push\n"); 428 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ 429 printk("Machine check in kernel mode.\n"); 430 printk("Caused by (from SRR1=%lx): ", reason); 431 switch (reason & 0x601F0000) { 432 case 0x80000: 433 printk("Machine check signal\n"); 434 break; 435 case 0: /* for 601 */ 436 case 0x40000: 437 case 0x140000: /* 7450 MSS error and TEA */ 438 printk("Transfer error ack signal\n"); 439 break; 440 case 0x20000: 441 printk("Data parity error signal\n"); 442 break; 443 case 0x10000: 444 printk("Address parity error signal\n"); 445 break; 446 case 0x20000000: 447 printk("L1 Data Cache error\n"); 448 break; 449 case 0x40000000: 450 printk("L1 Instruction Cache error\n"); 451 break; 452 case 0x00100000: 453 printk("L2 data cache parity error\n"); 454 break; 455 default: 456 printk("Unknown values in msr\n"); 457 } 458 #endif /* CONFIG_4xx */ 459 460 /* 461 * Optional platform-provided routine to print out 462 * additional info, e.g. bus error registers. 463 */ 464 platform_machine_check(regs); 465 #endif /* CONFIG_PPC64 */ 466 467 if (debugger_fault_handler(regs)) 468 return; 469 die("Machine check", regs, SIGBUS); 470 471 /* Must die if the interrupt is not recoverable */ 472 if (!(regs->msr & MSR_RI)) 473 panic("Unrecoverable Machine check"); 474 } 475 476 void SMIException(struct pt_regs *regs) 477 { 478 die("System Management Interrupt", regs, SIGABRT); 479 } 480 481 void unknown_exception(struct pt_regs *regs) 482 { 483 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", 484 regs->nip, regs->msr, regs->trap); 485 486 _exception(SIGTRAP, regs, 0, 0); 487 } 488 489 void instruction_breakpoint_exception(struct pt_regs *regs) 490 { 491 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, 492 5, SIGTRAP) == NOTIFY_STOP) 493 return; 494 if (debugger_iabr_match(regs)) 495 return; 496 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 497 } 498 499 void RunModeException(struct pt_regs *regs) 500 { 501 _exception(SIGTRAP, regs, 0, 0); 502 } 503 504 void __kprobes single_step_exception(struct pt_regs *regs) 505 { 506 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ 507 508 if (notify_die(DIE_SSTEP, "single_step", regs, 5, 509 5, SIGTRAP) == NOTIFY_STOP) 510 return; 511 if (debugger_sstep(regs)) 512 return; 513 514 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 515 } 516 517 /* 518 * After we have successfully emulated an instruction, we have to 519 * check if the instruction was being single-stepped, and if so, 520 * pretend we got a single-step exception. This was pointed out 521 * by Kumar Gala. -- paulus 522 */ 523 static void emulate_single_step(struct pt_regs *regs) 524 { 525 if (single_stepping(regs)) { 526 clear_single_step(regs); 527 _exception(SIGTRAP, regs, TRAP_TRACE, 0); 528 } 529 } 530 531 static void parse_fpe(struct pt_regs *regs) 532 { 533 int code = 0; 534 unsigned long fpscr; 535 536 flush_fp_to_thread(current); 537 538 fpscr = current->thread.fpscr.val; 539 540 /* Invalid operation */ 541 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) 542 code = FPE_FLTINV; 543 544 /* Overflow */ 545 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) 546 code = FPE_FLTOVF; 547 548 /* Underflow */ 549 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) 550 code = FPE_FLTUND; 551 552 /* Divide by zero */ 553 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) 554 code = FPE_FLTDIV; 555 556 /* Inexact result */ 557 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) 558 code = FPE_FLTRES; 559 560 _exception(SIGFPE, regs, code, regs->nip); 561 } 562 563 /* 564 * Illegal instruction emulation support. Originally written to 565 * provide the PVR to user applications using the mfspr rd, PVR. 566 * Return non-zero if we can't emulate, or -EFAULT if the associated 567 * memory access caused an access fault. Return zero on success. 568 * 569 * There are a couple of ways to do this, either "decode" the instruction 570 * or directly match lots of bits. In this case, matching lots of 571 * bits is faster and easier. 572 * 573 */ 574 #define INST_MFSPR_PVR 0x7c1f42a6 575 #define INST_MFSPR_PVR_MASK 0xfc1fffff 576 577 #define INST_DCBA 0x7c0005ec 578 #define INST_DCBA_MASK 0x7c0007fe 579 580 #define INST_MCRXR 0x7c000400 581 #define INST_MCRXR_MASK 0x7c0007fe 582 583 #define INST_STRING 0x7c00042a 584 #define INST_STRING_MASK 0x7c0007fe 585 #define INST_STRING_GEN_MASK 0x7c00067e 586 #define INST_LSWI 0x7c0004aa 587 #define INST_LSWX 0x7c00042a 588 #define INST_STSWI 0x7c0005aa 589 #define INST_STSWX 0x7c00052a 590 591 static int emulate_string_inst(struct pt_regs *regs, u32 instword) 592 { 593 u8 rT = (instword >> 21) & 0x1f; 594 u8 rA = (instword >> 16) & 0x1f; 595 u8 NB_RB = (instword >> 11) & 0x1f; 596 u32 num_bytes; 597 unsigned long EA; 598 int pos = 0; 599 600 /* Early out if we are an invalid form of lswx */ 601 if ((instword & INST_STRING_MASK) == INST_LSWX) 602 if ((rT == rA) || (rT == NB_RB)) 603 return -EINVAL; 604 605 EA = (rA == 0) ? 0 : regs->gpr[rA]; 606 607 switch (instword & INST_STRING_MASK) { 608 case INST_LSWX: 609 case INST_STSWX: 610 EA += NB_RB; 611 num_bytes = regs->xer & 0x7f; 612 break; 613 case INST_LSWI: 614 case INST_STSWI: 615 num_bytes = (NB_RB == 0) ? 32 : NB_RB; 616 break; 617 default: 618 return -EINVAL; 619 } 620 621 while (num_bytes != 0) 622 { 623 u8 val; 624 u32 shift = 8 * (3 - (pos & 0x3)); 625 626 switch ((instword & INST_STRING_MASK)) { 627 case INST_LSWX: 628 case INST_LSWI: 629 if (get_user(val, (u8 __user *)EA)) 630 return -EFAULT; 631 /* first time updating this reg, 632 * zero it out */ 633 if (pos == 0) 634 regs->gpr[rT] = 0; 635 regs->gpr[rT] |= val << shift; 636 break; 637 case INST_STSWI: 638 case INST_STSWX: 639 val = regs->gpr[rT] >> shift; 640 if (put_user(val, (u8 __user *)EA)) 641 return -EFAULT; 642 break; 643 } 644 /* move EA to next address */ 645 EA += 1; 646 num_bytes--; 647 648 /* manage our position within the register */ 649 if (++pos == 4) { 650 pos = 0; 651 if (++rT == 32) 652 rT = 0; 653 } 654 } 655 656 return 0; 657 } 658 659 static int emulate_instruction(struct pt_regs *regs) 660 { 661 u32 instword; 662 u32 rd; 663 664 if (!user_mode(regs)) 665 return -EINVAL; 666 CHECK_FULL_REGS(regs); 667 668 if (get_user(instword, (u32 __user *)(regs->nip))) 669 return -EFAULT; 670 671 /* Emulate the mfspr rD, PVR. */ 672 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { 673 rd = (instword >> 21) & 0x1f; 674 regs->gpr[rd] = mfspr(SPRN_PVR); 675 return 0; 676 } 677 678 /* Emulating the dcba insn is just a no-op. */ 679 if ((instword & INST_DCBA_MASK) == INST_DCBA) 680 return 0; 681 682 /* Emulate the mcrxr insn. */ 683 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { 684 int shift = (instword >> 21) & 0x1c; 685 unsigned long msk = 0xf0000000UL >> shift; 686 687 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); 688 regs->xer &= ~0xf0000000UL; 689 return 0; 690 } 691 692 /* Emulate load/store string insn. */ 693 if ((instword & INST_STRING_GEN_MASK) == INST_STRING) 694 return emulate_string_inst(regs, instword); 695 696 return -EINVAL; 697 } 698 699 /* 700 * Look through the list of trap instructions that are used for BUG(), 701 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know 702 * that the exception was caused by a trap instruction of some kind. 703 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 704 * otherwise. 705 */ 706 extern struct bug_entry __start___bug_table[], __stop___bug_table[]; 707 708 #ifndef CONFIG_MODULES 709 #define module_find_bug(x) NULL 710 #endif 711 712 struct bug_entry *find_bug(unsigned long bugaddr) 713 { 714 struct bug_entry *bug; 715 716 for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) 717 if (bugaddr == bug->bug_addr) 718 return bug; 719 return module_find_bug(bugaddr); 720 } 721 722 static int check_bug_trap(struct pt_regs *regs) 723 { 724 struct bug_entry *bug; 725 unsigned long addr; 726 727 if (regs->msr & MSR_PR) 728 return 0; /* not in kernel */ 729 addr = regs->nip; /* address of trap instruction */ 730 if (addr < PAGE_OFFSET) 731 return 0; 732 bug = find_bug(regs->nip); 733 if (bug == NULL) 734 return 0; 735 if (bug->line & BUG_WARNING_TRAP) { 736 /* this is a WARN_ON rather than BUG/BUG_ON */ 737 printk(KERN_ERR "Badness in %s at %s:%ld\n", 738 bug->function, bug->file, 739 bug->line & ~BUG_WARNING_TRAP); 740 dump_stack(); 741 return 1; 742 } 743 printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n", 744 bug->function, bug->file, bug->line); 745 746 return 0; 747 } 748 749 void __kprobes program_check_exception(struct pt_regs *regs) 750 { 751 unsigned int reason = get_reason(regs); 752 extern int do_mathemu(struct pt_regs *regs); 753 754 #ifdef CONFIG_MATH_EMULATION 755 /* (reason & REASON_ILLEGAL) would be the obvious thing here, 756 * but there seems to be a hardware bug on the 405GP (RevD) 757 * that means ESR is sometimes set incorrectly - either to 758 * ESR_DST (!?) or 0. In the process of chasing this with the 759 * hardware people - not sure if it can happen on any illegal 760 * instruction or only on FP instructions, whether there is a 761 * pattern to occurences etc. -dgibson 31/Mar/2003 */ 762 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { 763 emulate_single_step(regs); 764 return; 765 } 766 #endif /* CONFIG_MATH_EMULATION */ 767 768 if (reason & REASON_FP) { 769 /* IEEE FP exception */ 770 parse_fpe(regs); 771 return; 772 } 773 if (reason & REASON_TRAP) { 774 /* trap exception */ 775 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) 776 == NOTIFY_STOP) 777 return; 778 if (debugger_bpt(regs)) 779 return; 780 if (check_bug_trap(regs)) { 781 regs->nip += 4; 782 return; 783 } 784 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); 785 return; 786 } 787 788 local_irq_enable(); 789 790 /* Try to emulate it if we should. */ 791 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { 792 switch (emulate_instruction(regs)) { 793 case 0: 794 regs->nip += 4; 795 emulate_single_step(regs); 796 return; 797 case -EFAULT: 798 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); 799 return; 800 } 801 } 802 803 if (reason & REASON_PRIVILEGED) 804 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 805 else 806 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 807 } 808 809 void alignment_exception(struct pt_regs *regs) 810 { 811 int fixed; 812 813 fixed = fix_alignment(regs); 814 815 if (fixed == 1) { 816 regs->nip += 4; /* skip over emulated instruction */ 817 emulate_single_step(regs); 818 return; 819 } 820 821 /* Operand address was bad */ 822 if (fixed == -EFAULT) { 823 if (user_mode(regs)) 824 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); 825 else 826 /* Search exception table */ 827 bad_page_fault(regs, regs->dar, SIGSEGV); 828 return; 829 } 830 _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); 831 } 832 833 void StackOverflow(struct pt_regs *regs) 834 { 835 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", 836 current, regs->gpr[1]); 837 debugger(regs); 838 show_regs(regs); 839 panic("kernel stack overflow"); 840 } 841 842 void nonrecoverable_exception(struct pt_regs *regs) 843 { 844 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", 845 regs->nip, regs->msr); 846 debugger(regs); 847 die("nonrecoverable exception", regs, SIGKILL); 848 } 849 850 void trace_syscall(struct pt_regs *regs) 851 { 852 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", 853 current, current->pid, regs->nip, regs->link, regs->gpr[0], 854 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); 855 } 856 857 void kernel_fp_unavailable_exception(struct pt_regs *regs) 858 { 859 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " 860 "%lx at %lx\n", regs->trap, regs->nip); 861 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); 862 } 863 864 void altivec_unavailable_exception(struct pt_regs *regs) 865 { 866 #if !defined(CONFIG_ALTIVEC) 867 if (user_mode(regs)) { 868 /* A user program has executed an altivec instruction, 869 but this kernel doesn't support altivec. */ 870 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 871 return; 872 } 873 #endif 874 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " 875 "%lx at %lx\n", regs->trap, regs->nip); 876 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); 877 } 878 879 void performance_monitor_exception(struct pt_regs *regs) 880 { 881 perf_irq(regs); 882 } 883 884 #ifdef CONFIG_8xx 885 void SoftwareEmulation(struct pt_regs *regs) 886 { 887 extern int do_mathemu(struct pt_regs *); 888 extern int Soft_emulate_8xx(struct pt_regs *); 889 int errcode; 890 891 CHECK_FULL_REGS(regs); 892 893 if (!user_mode(regs)) { 894 debugger(regs); 895 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 896 } 897 898 #ifdef CONFIG_MATH_EMULATION 899 errcode = do_mathemu(regs); 900 #else 901 errcode = Soft_emulate_8xx(regs); 902 #endif 903 if (errcode) { 904 if (errcode > 0) 905 _exception(SIGFPE, regs, 0, 0); 906 else if (errcode == -EFAULT) 907 _exception(SIGSEGV, regs, 0, 0); 908 else 909 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); 910 } else 911 emulate_single_step(regs); 912 } 913 #endif /* CONFIG_8xx */ 914 915 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 916 917 void DebugException(struct pt_regs *regs, unsigned long debug_status) 918 { 919 if (debug_status & DBSR_IC) { /* instruction completion */ 920 regs->msr &= ~MSR_DE; 921 if (user_mode(regs)) { 922 current->thread.dbcr0 &= ~DBCR0_IC; 923 } else { 924 /* Disable instruction completion */ 925 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); 926 /* Clear the instruction completion event */ 927 mtspr(SPRN_DBSR, DBSR_IC); 928 if (debugger_sstep(regs)) 929 return; 930 } 931 _exception(SIGTRAP, regs, TRAP_TRACE, 0); 932 } 933 } 934 #endif /* CONFIG_4xx || CONFIG_BOOKE */ 935 936 #if !defined(CONFIG_TAU_INT) 937 void TAUException(struct pt_regs *regs) 938 { 939 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", 940 regs->nip, regs->msr, regs->trap, print_tainted()); 941 } 942 #endif /* CONFIG_INT_TAU */ 943 944 #ifdef CONFIG_ALTIVEC 945 void altivec_assist_exception(struct pt_regs *regs) 946 { 947 int err; 948 949 if (!user_mode(regs)) { 950 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" 951 " at %lx\n", regs->nip); 952 die("Kernel VMX/Altivec assist exception", regs, SIGILL); 953 } 954 955 flush_altivec_to_thread(current); 956 957 err = emulate_altivec(regs); 958 if (err == 0) { 959 regs->nip += 4; /* skip emulated instruction */ 960 emulate_single_step(regs); 961 return; 962 } 963 964 if (err == -EFAULT) { 965 /* got an error reading the instruction */ 966 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); 967 } else { 968 /* didn't recognize the instruction */ 969 /* XXX quick hack for now: set the non-Java bit in the VSCR */ 970 if (printk_ratelimit()) 971 printk(KERN_ERR "Unrecognized altivec instruction " 972 "in %s at %lx\n", current->comm, regs->nip); 973 current->thread.vscr.u[3] |= 0x10000; 974 } 975 } 976 #endif /* CONFIG_ALTIVEC */ 977 978 #ifdef CONFIG_FSL_BOOKE 979 void CacheLockingException(struct pt_regs *regs, unsigned long address, 980 unsigned long error_code) 981 { 982 /* We treat cache locking instructions from the user 983 * as priv ops, in the future we could try to do 984 * something smarter 985 */ 986 if (error_code & (ESR_DLK|ESR_ILK)) 987 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); 988 return; 989 } 990 #endif /* CONFIG_FSL_BOOKE */ 991 992 #ifdef CONFIG_SPE 993 void SPEFloatingPointException(struct pt_regs *regs) 994 { 995 unsigned long spefscr; 996 int fpexc_mode; 997 int code = 0; 998 999 spefscr = current->thread.spefscr; 1000 fpexc_mode = current->thread.fpexc_mode; 1001 1002 /* Hardware does not neccessarily set sticky 1003 * underflow/overflow/invalid flags */ 1004 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { 1005 code = FPE_FLTOVF; 1006 spefscr |= SPEFSCR_FOVFS; 1007 } 1008 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { 1009 code = FPE_FLTUND; 1010 spefscr |= SPEFSCR_FUNFS; 1011 } 1012 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) 1013 code = FPE_FLTDIV; 1014 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { 1015 code = FPE_FLTINV; 1016 spefscr |= SPEFSCR_FINVS; 1017 } 1018 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) 1019 code = FPE_FLTRES; 1020 1021 current->thread.spefscr = spefscr; 1022 1023 _exception(SIGFPE, regs, code, regs->nip); 1024 return; 1025 } 1026 #endif 1027 1028 /* 1029 * We enter here if we get an unrecoverable exception, that is, one 1030 * that happened at a point where the RI (recoverable interrupt) bit 1031 * in the MSR is 0. This indicates that SRR0/1 are live, and that 1032 * we therefore lost state by taking this exception. 1033 */ 1034 void unrecoverable_exception(struct pt_regs *regs) 1035 { 1036 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", 1037 regs->trap, regs->nip); 1038 die("Unrecoverable exception", regs, SIGABRT); 1039 } 1040 1041 #ifdef CONFIG_BOOKE_WDT 1042 /* 1043 * Default handler for a Watchdog exception, 1044 * spins until a reboot occurs 1045 */ 1046 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) 1047 { 1048 /* Generic WatchdogHandler, implement your own */ 1049 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); 1050 return; 1051 } 1052 1053 void WatchdogException(struct pt_regs *regs) 1054 { 1055 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); 1056 WatchdogHandler(regs); 1057 } 1058 #endif 1059 1060 /* 1061 * We enter here if we discover during exception entry that we are 1062 * running in supervisor mode with a userspace value in the stack pointer. 1063 */ 1064 void kernel_bad_stack(struct pt_regs *regs) 1065 { 1066 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", 1067 regs->gpr[1], regs->nip); 1068 die("Bad kernel stack pointer", regs, SIGABRT); 1069 } 1070 1071 void __init trap_init(void) 1072 { 1073 } 1074