1 /* 2 * Port for PPC64 David Engebretsen, IBM Corp. 3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 4 * 5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 6 * Rework, based on alpha PCI code. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #undef DEBUG 15 16 #include <linux/config.h> 17 #include <linux/kernel.h> 18 #include <linux/pci.h> 19 #include <linux/string.h> 20 #include <linux/init.h> 21 #include <linux/bootmem.h> 22 #include <linux/mm.h> 23 #include <linux/list.h> 24 #include <linux/syscalls.h> 25 26 #include <asm/processor.h> 27 #include <asm/io.h> 28 #include <asm/prom.h> 29 #include <asm/pci-bridge.h> 30 #include <asm/byteorder.h> 31 #include <asm/irq.h> 32 #include <asm/machdep.h> 33 #include <asm/ppc-pci.h> 34 35 #ifdef DEBUG 36 #include <asm/udbg.h> 37 #define DBG(fmt...) udbg_printf(fmt) 38 #else 39 #define DBG(fmt...) 40 #endif 41 42 unsigned long pci_probe_only = 1; 43 int pci_assign_all_buses = 0; 44 45 /* 46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch 47 * devices we don't have access to. 48 */ 49 unsigned long io_page_mask; 50 51 EXPORT_SYMBOL(io_page_mask); 52 53 #ifdef CONFIG_PPC_MULTIPLATFORM 54 static void fixup_resource(struct resource *res, struct pci_dev *dev); 55 static void do_bus_setup(struct pci_bus *bus); 56 #endif 57 58 /* pci_io_base -- the base address from which io bars are offsets. 59 * This is the lowest I/O base address (so bar values are always positive), 60 * and it *must* be the start of ISA space if an ISA bus exists because 61 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy 62 * page is mapped and isa_io_limit prevents access to it. 63 */ 64 unsigned long isa_io_base; /* NULL if no ISA bus */ 65 EXPORT_SYMBOL(isa_io_base); 66 unsigned long pci_io_base; 67 EXPORT_SYMBOL(pci_io_base); 68 69 void iSeries_pcibios_init(void); 70 71 LIST_HEAD(hose_list); 72 73 struct dma_mapping_ops pci_dma_ops; 74 EXPORT_SYMBOL(pci_dma_ops); 75 76 int global_phb_number; /* Global phb counter */ 77 78 /* Cached ISA bridge dev. */ 79 struct pci_dev *ppc64_isabridge_dev = NULL; 80 81 static void fixup_broken_pcnet32(struct pci_dev* dev) 82 { 83 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { 84 dev->vendor = PCI_VENDOR_ID_AMD; 85 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); 86 } 87 } 88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); 89 90 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 91 struct resource *res) 92 { 93 unsigned long offset = 0; 94 struct pci_controller *hose = pci_bus_to_host(dev->bus); 95 96 if (!hose) 97 return; 98 99 if (res->flags & IORESOURCE_IO) 100 offset = (unsigned long)hose->io_base_virt - pci_io_base; 101 102 if (res->flags & IORESOURCE_MEM) 103 offset = hose->pci_mem_offset; 104 105 region->start = res->start - offset; 106 region->end = res->end - offset; 107 } 108 109 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 110 struct pci_bus_region *region) 111 { 112 unsigned long offset = 0; 113 struct pci_controller *hose = pci_bus_to_host(dev->bus); 114 115 if (!hose) 116 return; 117 118 if (res->flags & IORESOURCE_IO) 119 offset = (unsigned long)hose->io_base_virt - pci_io_base; 120 121 if (res->flags & IORESOURCE_MEM) 122 offset = hose->pci_mem_offset; 123 124 res->start = region->start + offset; 125 res->end = region->end + offset; 126 } 127 128 #ifdef CONFIG_HOTPLUG 129 EXPORT_SYMBOL(pcibios_resource_to_bus); 130 EXPORT_SYMBOL(pcibios_bus_to_resource); 131 #endif 132 133 /* 134 * We need to avoid collisions with `mirrored' VGA ports 135 * and other strange ISA hardware, so we always want the 136 * addresses to be allocated in the 0x000-0x0ff region 137 * modulo 0x400. 138 * 139 * Why? Because some silly external IO cards only decode 140 * the low 10 bits of the IO address. The 0x00-0xff region 141 * is reserved for motherboard devices that decode all 16 142 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 143 * but we want to try to avoid allocating at 0x2900-0x2bff 144 * which might have be mirrored at 0x0100-0x03ff.. 145 */ 146 void pcibios_align_resource(void *data, struct resource *res, 147 unsigned long size, unsigned long align) 148 { 149 struct pci_dev *dev = data; 150 struct pci_controller *hose = pci_bus_to_host(dev->bus); 151 unsigned long start = res->start; 152 unsigned long alignto; 153 154 if (res->flags & IORESOURCE_IO) { 155 unsigned long offset = (unsigned long)hose->io_base_virt - 156 pci_io_base; 157 /* Make sure we start at our min on all hoses */ 158 if (start - offset < PCIBIOS_MIN_IO) 159 start = PCIBIOS_MIN_IO + offset; 160 161 /* 162 * Put everything into 0x00-0xff region modulo 0x400 163 */ 164 if (start & 0x300) 165 start = (start + 0x3ff) & ~0x3ff; 166 167 } else if (res->flags & IORESOURCE_MEM) { 168 /* Make sure we start at our min on all hoses */ 169 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) 170 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; 171 172 /* Align to multiple of size of minimum base. */ 173 alignto = max(0x1000UL, align); 174 start = ALIGN(start, alignto); 175 } 176 177 res->start = start; 178 } 179 180 static DEFINE_SPINLOCK(hose_spinlock); 181 182 /* 183 * pci_controller(phb) initialized common variables. 184 */ 185 static void __devinit pci_setup_pci_controller(struct pci_controller *hose) 186 { 187 memset(hose, 0, sizeof(struct pci_controller)); 188 189 spin_lock(&hose_spinlock); 190 hose->global_number = global_phb_number++; 191 list_add_tail(&hose->list_node, &hose_list); 192 spin_unlock(&hose_spinlock); 193 } 194 195 static void add_linux_pci_domain(struct device_node *dev, 196 struct pci_controller *phb) 197 { 198 struct property *of_prop; 199 unsigned int size; 200 201 of_prop = (struct property *) 202 get_property(dev, "linux,pci-domain", &size); 203 if (of_prop != NULL) 204 return; 205 WARN_ON(of_prop && size < sizeof(int)); 206 if (of_prop && size < sizeof(int)) 207 of_prop = NULL; 208 size = sizeof(struct property) + sizeof(int); 209 if (of_prop == NULL) { 210 if (mem_init_done) 211 of_prop = kmalloc(size, GFP_KERNEL); 212 else 213 of_prop = alloc_bootmem(size); 214 } 215 memset(of_prop, 0, sizeof(struct property)); 216 of_prop->name = "linux,pci-domain"; 217 of_prop->length = sizeof(int); 218 of_prop->value = (unsigned char *)&of_prop[1]; 219 *((int *)of_prop->value) = phb->global_number; 220 prom_add_property(dev, of_prop); 221 } 222 223 struct pci_controller * pcibios_alloc_controller(struct device_node *dev) 224 { 225 struct pci_controller *phb; 226 227 if (mem_init_done) 228 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL); 229 else 230 phb = alloc_bootmem(sizeof (struct pci_controller)); 231 if (phb == NULL) 232 return NULL; 233 pci_setup_pci_controller(phb); 234 phb->arch_data = dev; 235 phb->is_dynamic = mem_init_done; 236 if (dev) 237 add_linux_pci_domain(dev, phb); 238 return phb; 239 } 240 241 void pcibios_free_controller(struct pci_controller *phb) 242 { 243 if (phb->arch_data) { 244 struct device_node *np = phb->arch_data; 245 int *domain = (int *)get_property(np, 246 "linux,pci-domain", NULL); 247 if (domain) 248 *domain = -1; 249 } 250 if (phb->is_dynamic) 251 kfree(phb); 252 } 253 254 static void __init pcibios_claim_one_bus(struct pci_bus *b) 255 { 256 struct pci_dev *dev; 257 struct pci_bus *child_bus; 258 259 list_for_each_entry(dev, &b->devices, bus_list) { 260 int i; 261 262 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 263 struct resource *r = &dev->resource[i]; 264 265 if (r->parent || !r->start || !r->flags) 266 continue; 267 pci_claim_resource(dev, i); 268 } 269 } 270 271 list_for_each_entry(child_bus, &b->children, node) 272 pcibios_claim_one_bus(child_bus); 273 } 274 275 #ifndef CONFIG_PPC_ISERIES 276 static void __init pcibios_claim_of_setup(void) 277 { 278 struct pci_bus *b; 279 280 list_for_each_entry(b, &pci_root_buses, node) 281 pcibios_claim_one_bus(b); 282 } 283 #endif 284 285 #ifdef CONFIG_PPC_MULTIPLATFORM 286 static u32 get_int_prop(struct device_node *np, const char *name, u32 def) 287 { 288 u32 *prop; 289 int len; 290 291 prop = (u32 *) get_property(np, name, &len); 292 if (prop && len >= 4) 293 return *prop; 294 return def; 295 } 296 297 static unsigned int pci_parse_of_flags(u32 addr0) 298 { 299 unsigned int flags = 0; 300 301 if (addr0 & 0x02000000) { 302 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; 303 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; 304 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; 305 if (addr0 & 0x40000000) 306 flags |= IORESOURCE_PREFETCH 307 | PCI_BASE_ADDRESS_MEM_PREFETCH; 308 } else if (addr0 & 0x01000000) 309 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 310 return flags; 311 } 312 313 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 314 315 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) 316 { 317 u64 base, size; 318 unsigned int flags; 319 struct resource *res; 320 u32 *addrs, i; 321 int proplen; 322 323 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen); 324 if (!addrs) 325 return; 326 for (; proplen >= 20; proplen -= 20, addrs += 5) { 327 flags = pci_parse_of_flags(addrs[0]); 328 if (!flags) 329 continue; 330 base = GET_64BIT(addrs, 1); 331 size = GET_64BIT(addrs, 3); 332 if (!size) 333 continue; 334 i = addrs[0] & 0xff; 335 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { 336 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; 337 } else if (i == dev->rom_base_reg) { 338 res = &dev->resource[PCI_ROM_RESOURCE]; 339 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; 340 } else { 341 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); 342 continue; 343 } 344 res->start = base; 345 res->end = base + size - 1; 346 res->flags = flags; 347 res->name = pci_name(dev); 348 fixup_resource(res, dev); 349 } 350 } 351 352 struct pci_dev *of_create_pci_dev(struct device_node *node, 353 struct pci_bus *bus, int devfn) 354 { 355 struct pci_dev *dev; 356 const char *type; 357 358 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); 359 if (!dev) 360 return NULL; 361 type = get_property(node, "device_type", NULL); 362 if (type == NULL) 363 type = ""; 364 365 memset(dev, 0, sizeof(struct pci_dev)); 366 dev->bus = bus; 367 dev->sysdata = node; 368 dev->dev.parent = bus->bridge; 369 dev->dev.bus = &pci_bus_type; 370 dev->devfn = devfn; 371 dev->multifunction = 0; /* maybe a lie? */ 372 373 dev->vendor = get_int_prop(node, "vendor-id", 0xffff); 374 dev->device = get_int_prop(node, "device-id", 0xffff); 375 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); 376 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); 377 378 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/ 379 380 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), 381 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 382 dev->class = get_int_prop(node, "class-code", 0); 383 384 dev->current_state = 4; /* unknown power state */ 385 386 if (!strcmp(type, "pci")) { 387 /* a PCI-PCI bridge */ 388 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; 389 dev->rom_base_reg = PCI_ROM_ADDRESS1; 390 } else if (!strcmp(type, "cardbus")) { 391 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; 392 } else { 393 dev->hdr_type = PCI_HEADER_TYPE_NORMAL; 394 dev->rom_base_reg = PCI_ROM_ADDRESS; 395 dev->irq = NO_IRQ; 396 if (node->n_intrs > 0) { 397 dev->irq = node->intrs[0].line; 398 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 399 dev->irq); 400 } 401 } 402 403 pci_parse_of_addrs(node, dev); 404 405 pci_device_add(dev, bus); 406 407 /* XXX pci_scan_msi_device(dev); */ 408 409 return dev; 410 } 411 EXPORT_SYMBOL(of_create_pci_dev); 412 413 void __devinit of_scan_bus(struct device_node *node, 414 struct pci_bus *bus) 415 { 416 struct device_node *child = NULL; 417 u32 *reg; 418 int reglen, devfn; 419 struct pci_dev *dev; 420 421 while ((child = of_get_next_child(node, child)) != NULL) { 422 reg = (u32 *) get_property(child, "reg", ®len); 423 if (reg == NULL || reglen < 20) 424 continue; 425 devfn = (reg[0] >> 8) & 0xff; 426 /* create a new pci_dev for this device */ 427 dev = of_create_pci_dev(child, bus, devfn); 428 if (!dev) 429 continue; 430 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 431 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) 432 of_scan_pci_bridge(child, dev); 433 } 434 435 do_bus_setup(bus); 436 } 437 EXPORT_SYMBOL(of_scan_bus); 438 439 void __devinit of_scan_pci_bridge(struct device_node *node, 440 struct pci_dev *dev) 441 { 442 struct pci_bus *bus; 443 u32 *busrange, *ranges; 444 int len, i, mode; 445 struct resource *res; 446 unsigned int flags; 447 u64 size; 448 449 /* parse bus-range property */ 450 busrange = (u32 *) get_property(node, "bus-range", &len); 451 if (busrange == NULL || len != 8) { 452 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n", 453 node->full_name); 454 return; 455 } 456 ranges = (u32 *) get_property(node, "ranges", &len); 457 if (ranges == NULL) { 458 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n", 459 node->full_name); 460 return; 461 } 462 463 bus = pci_add_new_bus(dev->bus, dev, busrange[0]); 464 if (!bus) { 465 printk(KERN_ERR "Failed to create pci bus for %s\n", 466 node->full_name); 467 return; 468 } 469 470 bus->primary = dev->bus->number; 471 bus->subordinate = busrange[1]; 472 bus->bridge_ctl = 0; 473 bus->sysdata = node; 474 475 /* parse ranges property */ 476 /* PCI #address-cells == 3 and #size-cells == 2 always */ 477 res = &dev->resource[PCI_BRIDGE_RESOURCES]; 478 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { 479 res->flags = 0; 480 bus->resource[i] = res; 481 ++res; 482 } 483 i = 1; 484 for (; len >= 32; len -= 32, ranges += 8) { 485 flags = pci_parse_of_flags(ranges[0]); 486 size = GET_64BIT(ranges, 6); 487 if (flags == 0 || size == 0) 488 continue; 489 if (flags & IORESOURCE_IO) { 490 res = bus->resource[0]; 491 if (res->flags) { 492 printk(KERN_ERR "PCI: ignoring extra I/O range" 493 " for bridge %s\n", node->full_name); 494 continue; 495 } 496 } else { 497 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { 498 printk(KERN_ERR "PCI: too many memory ranges" 499 " for bridge %s\n", node->full_name); 500 continue; 501 } 502 res = bus->resource[i]; 503 ++i; 504 } 505 res->start = GET_64BIT(ranges, 1); 506 res->end = res->start + size - 1; 507 res->flags = flags; 508 fixup_resource(res, dev); 509 } 510 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), 511 bus->number); 512 513 mode = PCI_PROBE_NORMAL; 514 if (ppc_md.pci_probe_mode) 515 mode = ppc_md.pci_probe_mode(bus); 516 if (mode == PCI_PROBE_DEVTREE) 517 of_scan_bus(node, bus); 518 else if (mode == PCI_PROBE_NORMAL) 519 pci_scan_child_bus(bus); 520 } 521 EXPORT_SYMBOL(of_scan_pci_bridge); 522 #endif /* CONFIG_PPC_MULTIPLATFORM */ 523 524 void __devinit scan_phb(struct pci_controller *hose) 525 { 526 struct pci_bus *bus; 527 struct device_node *node = hose->arch_data; 528 int i, mode; 529 struct resource *res; 530 531 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node); 532 if (bus == NULL) { 533 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", 534 hose->global_number); 535 return; 536 } 537 bus->secondary = hose->first_busno; 538 hose->bus = bus; 539 540 bus->resource[0] = res = &hose->io_resource; 541 if (res->flags && request_resource(&ioport_resource, res)) 542 printk(KERN_ERR "Failed to request PCI IO region " 543 "on PCI domain %04x\n", hose->global_number); 544 545 for (i = 0; i < 3; ++i) { 546 res = &hose->mem_resources[i]; 547 bus->resource[i+1] = res; 548 if (res->flags && request_resource(&iomem_resource, res)) 549 printk(KERN_ERR "Failed to request PCI memory region " 550 "on PCI domain %04x\n", hose->global_number); 551 } 552 553 mode = PCI_PROBE_NORMAL; 554 #ifdef CONFIG_PPC_MULTIPLATFORM 555 if (ppc_md.pci_probe_mode) 556 mode = ppc_md.pci_probe_mode(bus); 557 if (mode == PCI_PROBE_DEVTREE) { 558 bus->subordinate = hose->last_busno; 559 of_scan_bus(node, bus); 560 } 561 #endif /* CONFIG_PPC_MULTIPLATFORM */ 562 if (mode == PCI_PROBE_NORMAL) 563 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 564 pci_bus_add_devices(bus); 565 } 566 567 static int __init pcibios_init(void) 568 { 569 struct pci_controller *hose, *tmp; 570 571 /* For now, override phys_mem_access_prot. If we need it, 572 * later, we may move that initialization to each ppc_md 573 */ 574 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; 575 576 #ifdef CONFIG_PPC_ISERIES 577 iSeries_pcibios_init(); 578 #endif 579 580 printk("PCI: Probing PCI hardware\n"); 581 582 /* Scan all of the recorded PCI controllers. */ 583 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 584 scan_phb(hose); 585 586 #ifndef CONFIG_PPC_ISERIES 587 if (pci_probe_only) 588 pcibios_claim_of_setup(); 589 else 590 /* FIXME: `else' will be removed when 591 pci_assign_unassigned_resources() is able to work 592 correctly with [partially] allocated PCI tree. */ 593 pci_assign_unassigned_resources(); 594 #endif /* !CONFIG_PPC_ISERIES */ 595 596 /* Call machine dependent final fixup */ 597 if (ppc_md.pcibios_fixup) 598 ppc_md.pcibios_fixup(); 599 600 /* Cache the location of the ISA bridge (if we have one) */ 601 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); 602 if (ppc64_isabridge_dev != NULL) 603 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev)); 604 605 #ifdef CONFIG_PPC_MULTIPLATFORM 606 /* map in PCI I/O space */ 607 phbs_remap_io(); 608 #endif 609 610 printk("PCI: Probing PCI hardware done\n"); 611 612 return 0; 613 } 614 615 subsys_initcall(pcibios_init); 616 617 char __init *pcibios_setup(char *str) 618 { 619 return str; 620 } 621 622 int pcibios_enable_device(struct pci_dev *dev, int mask) 623 { 624 u16 cmd, oldcmd; 625 int i; 626 627 pci_read_config_word(dev, PCI_COMMAND, &cmd); 628 oldcmd = cmd; 629 630 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 631 struct resource *res = &dev->resource[i]; 632 633 /* Only set up the requested stuff */ 634 if (!(mask & (1<<i))) 635 continue; 636 637 if (res->flags & IORESOURCE_IO) 638 cmd |= PCI_COMMAND_IO; 639 if (res->flags & IORESOURCE_MEM) 640 cmd |= PCI_COMMAND_MEMORY; 641 } 642 643 if (cmd != oldcmd) { 644 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", 645 pci_name(dev), cmd); 646 /* Enable the appropriate bits in the PCI command register. */ 647 pci_write_config_word(dev, PCI_COMMAND, cmd); 648 } 649 return 0; 650 } 651 652 /* 653 * Return the domain number for this bus. 654 */ 655 int pci_domain_nr(struct pci_bus *bus) 656 { 657 #ifdef CONFIG_PPC_ISERIES 658 return 0; 659 #else 660 struct pci_controller *hose = pci_bus_to_host(bus); 661 662 return hose->global_number; 663 #endif 664 } 665 666 EXPORT_SYMBOL(pci_domain_nr); 667 668 /* Decide whether to display the domain number in /proc */ 669 int pci_proc_domain(struct pci_bus *bus) 670 { 671 #ifdef CONFIG_PPC_ISERIES 672 return 0; 673 #else 674 struct pci_controller *hose = pci_bus_to_host(bus); 675 return hose->buid; 676 #endif 677 } 678 679 /* 680 * Platform support for /proc/bus/pci/X/Y mmap()s, 681 * modelled on the sparc64 implementation by Dave Miller. 682 * -- paulus. 683 */ 684 685 /* 686 * Adjust vm_pgoff of VMA such that it is the physical page offset 687 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 688 * 689 * Basically, the user finds the base address for his device which he wishes 690 * to mmap. They read the 32-bit value from the config space base register, 691 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 692 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 693 * 694 * Returns negative error code on failure, zero on success. 695 */ 696 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 697 unsigned long *offset, 698 enum pci_mmap_state mmap_state) 699 { 700 struct pci_controller *hose = pci_bus_to_host(dev->bus); 701 unsigned long io_offset = 0; 702 int i, res_bit; 703 704 if (hose == 0) 705 return NULL; /* should never happen */ 706 707 /* If memory, add on the PCI bridge address offset */ 708 if (mmap_state == pci_mmap_mem) { 709 *offset += hose->pci_mem_offset; 710 res_bit = IORESOURCE_MEM; 711 } else { 712 io_offset = (unsigned long)hose->io_base_virt - pci_io_base; 713 *offset += io_offset; 714 res_bit = IORESOURCE_IO; 715 } 716 717 /* 718 * Check that the offset requested corresponds to one of the 719 * resources of the device. 720 */ 721 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 722 struct resource *rp = &dev->resource[i]; 723 int flags = rp->flags; 724 725 /* treat ROM as memory (should be already) */ 726 if (i == PCI_ROM_RESOURCE) 727 flags |= IORESOURCE_MEM; 728 729 /* Active and same type? */ 730 if ((flags & res_bit) == 0) 731 continue; 732 733 /* In the range of this resource? */ 734 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 735 continue; 736 737 /* found it! construct the final physical address */ 738 if (mmap_state == pci_mmap_io) 739 *offset += hose->io_base_phys - io_offset; 740 return rp; 741 } 742 743 return NULL; 744 } 745 746 /* 747 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 748 * device mapping. 749 */ 750 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 751 pgprot_t protection, 752 enum pci_mmap_state mmap_state, 753 int write_combine) 754 { 755 unsigned long prot = pgprot_val(protection); 756 757 /* Write combine is always 0 on non-memory space mappings. On 758 * memory space, if the user didn't pass 1, we check for a 759 * "prefetchable" resource. This is a bit hackish, but we use 760 * this to workaround the inability of /sysfs to provide a write 761 * combine bit 762 */ 763 if (mmap_state != pci_mmap_mem) 764 write_combine = 0; 765 else if (write_combine == 0) { 766 if (rp->flags & IORESOURCE_PREFETCH) 767 write_combine = 1; 768 } 769 770 /* XXX would be nice to have a way to ask for write-through */ 771 prot |= _PAGE_NO_CACHE; 772 if (write_combine) 773 prot &= ~_PAGE_GUARDED; 774 else 775 prot |= _PAGE_GUARDED; 776 777 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, 778 prot); 779 780 return __pgprot(prot); 781 } 782 783 /* 784 * This one is used by /dev/mem and fbdev who have no clue about the 785 * PCI device, it tries to find the PCI device first and calls the 786 * above routine 787 */ 788 pgprot_t pci_phys_mem_access_prot(struct file *file, 789 unsigned long pfn, 790 unsigned long size, 791 pgprot_t protection) 792 { 793 struct pci_dev *pdev = NULL; 794 struct resource *found = NULL; 795 unsigned long prot = pgprot_val(protection); 796 unsigned long offset = pfn << PAGE_SHIFT; 797 int i; 798 799 if (page_is_ram(pfn)) 800 return __pgprot(prot); 801 802 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; 803 804 for_each_pci_dev(pdev) { 805 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 806 struct resource *rp = &pdev->resource[i]; 807 int flags = rp->flags; 808 809 /* Active and same type? */ 810 if ((flags & IORESOURCE_MEM) == 0) 811 continue; 812 /* In the range of this resource? */ 813 if (offset < (rp->start & PAGE_MASK) || 814 offset > rp->end) 815 continue; 816 found = rp; 817 break; 818 } 819 if (found) 820 break; 821 } 822 if (found) { 823 if (found->flags & IORESOURCE_PREFETCH) 824 prot &= ~_PAGE_GUARDED; 825 pci_dev_put(pdev); 826 } 827 828 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); 829 830 return __pgprot(prot); 831 } 832 833 834 /* 835 * Perform the actual remap of the pages for a PCI device mapping, as 836 * appropriate for this architecture. The region in the process to map 837 * is described by vm_start and vm_end members of VMA, the base physical 838 * address is found in vm_pgoff. 839 * The pci device structure is provided so that architectures may make mapping 840 * decisions on a per-device or per-bus basis. 841 * 842 * Returns a negative error code on failure, zero on success. 843 */ 844 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 845 enum pci_mmap_state mmap_state, 846 int write_combine) 847 { 848 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 849 struct resource *rp; 850 int ret; 851 852 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 853 if (rp == NULL) 854 return -EINVAL; 855 856 vma->vm_pgoff = offset >> PAGE_SHIFT; 857 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO; 858 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 859 vma->vm_page_prot, 860 mmap_state, write_combine); 861 862 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 863 vma->vm_end - vma->vm_start, vma->vm_page_prot); 864 865 return ret; 866 } 867 868 #ifdef CONFIG_PPC_MULTIPLATFORM 869 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf) 870 { 871 struct pci_dev *pdev; 872 struct device_node *np; 873 874 pdev = to_pci_dev (dev); 875 np = pci_device_to_OF_node(pdev); 876 if (np == NULL || np->full_name == NULL) 877 return 0; 878 return sprintf(buf, "%s", np->full_name); 879 } 880 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 881 #endif /* CONFIG_PPC_MULTIPLATFORM */ 882 883 void pcibios_add_platform_entries(struct pci_dev *pdev) 884 { 885 #ifdef CONFIG_PPC_MULTIPLATFORM 886 device_create_file(&pdev->dev, &dev_attr_devspec); 887 #endif /* CONFIG_PPC_MULTIPLATFORM */ 888 } 889 890 #ifdef CONFIG_PPC_MULTIPLATFORM 891 892 #define ISA_SPACE_MASK 0x1 893 #define ISA_SPACE_IO 0x1 894 895 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node, 896 unsigned long phb_io_base_phys, 897 void __iomem * phb_io_base_virt) 898 { 899 struct isa_range *range; 900 unsigned long pci_addr; 901 unsigned int isa_addr; 902 unsigned int size; 903 int rlen = 0; 904 905 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen); 906 if (range == NULL || (rlen < sizeof(struct isa_range))) { 907 printk(KERN_ERR "no ISA ranges or unexpected isa range size," 908 "mapping 64k\n"); 909 __ioremap_explicit(phb_io_base_phys, 910 (unsigned long)phb_io_base_virt, 911 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED); 912 return; 913 } 914 915 /* From "ISA Binding to 1275" 916 * The ranges property is laid out as an array of elements, 917 * each of which comprises: 918 * cells 0 - 1: an ISA address 919 * cells 2 - 4: a PCI address 920 * (size depending on dev->n_addr_cells) 921 * cell 5: the size of the range 922 */ 923 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) { 924 isa_addr = range->isa_addr.a_lo; 925 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 | 926 range->pci_addr.a_lo; 927 928 /* Assume these are both zero */ 929 if ((pci_addr != 0) || (isa_addr != 0)) { 930 printk(KERN_ERR "unexpected isa to pci mapping: %s\n", 931 __FUNCTION__); 932 return; 933 } 934 935 size = PAGE_ALIGN(range->size); 936 937 __ioremap_explicit(phb_io_base_phys, 938 (unsigned long) phb_io_base_virt, 939 size, _PAGE_NO_CACHE | _PAGE_GUARDED); 940 } 941 } 942 943 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, 944 struct device_node *dev, int prim) 945 { 946 unsigned int *ranges, pci_space; 947 unsigned long size; 948 int rlen = 0; 949 int memno = 0; 950 struct resource *res; 951 int np, na = prom_n_addr_cells(dev); 952 unsigned long pci_addr, cpu_phys_addr; 953 954 np = na + 5; 955 956 /* From "PCI Binding to 1275" 957 * The ranges property is laid out as an array of elements, 958 * each of which comprises: 959 * cells 0 - 2: a PCI address 960 * cells 3 or 3+4: a CPU physical address 961 * (size depending on dev->n_addr_cells) 962 * cells 4+5 or 5+6: the size of the range 963 */ 964 ranges = (unsigned int *) get_property(dev, "ranges", &rlen); 965 if (ranges == NULL) 966 return; 967 hose->io_base_phys = 0; 968 while ((rlen -= np * sizeof(unsigned int)) >= 0) { 969 res = NULL; 970 pci_space = ranges[0]; 971 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2]; 972 973 cpu_phys_addr = ranges[3]; 974 if (na >= 2) 975 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4]; 976 977 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4]; 978 ranges += np; 979 if (size == 0) 980 continue; 981 982 /* Now consume following elements while they are contiguous */ 983 while (rlen >= np * sizeof(unsigned int)) { 984 unsigned long addr, phys; 985 986 if (ranges[0] != pci_space) 987 break; 988 addr = ((unsigned long)ranges[1] << 32) | ranges[2]; 989 phys = ranges[3]; 990 if (na >= 2) 991 phys = (phys << 32) | ranges[4]; 992 if (addr != pci_addr + size || 993 phys != cpu_phys_addr + size) 994 break; 995 996 size += ((unsigned long)ranges[na+3] << 32) 997 | ranges[na+4]; 998 ranges += np; 999 rlen -= np * sizeof(unsigned int); 1000 } 1001 1002 switch ((pci_space >> 24) & 0x3) { 1003 case 1: /* I/O space */ 1004 hose->io_base_phys = cpu_phys_addr; 1005 hose->pci_io_size = size; 1006 1007 res = &hose->io_resource; 1008 res->flags = IORESOURCE_IO; 1009 res->start = pci_addr; 1010 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number, 1011 res->start, res->start + size - 1); 1012 break; 1013 case 2: /* memory space */ 1014 memno = 0; 1015 while (memno < 3 && hose->mem_resources[memno].flags) 1016 ++memno; 1017 1018 if (memno == 0) 1019 hose->pci_mem_offset = cpu_phys_addr - pci_addr; 1020 if (memno < 3) { 1021 res = &hose->mem_resources[memno]; 1022 res->flags = IORESOURCE_MEM; 1023 res->start = cpu_phys_addr; 1024 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number, 1025 res->start, res->start + size - 1); 1026 } 1027 break; 1028 } 1029 if (res != NULL) { 1030 res->name = dev->full_name; 1031 res->end = res->start + size - 1; 1032 res->parent = NULL; 1033 res->sibling = NULL; 1034 res->child = NULL; 1035 } 1036 } 1037 } 1038 1039 void __init pci_setup_phb_io(struct pci_controller *hose, int primary) 1040 { 1041 unsigned long size = hose->pci_io_size; 1042 unsigned long io_virt_offset; 1043 struct resource *res; 1044 struct device_node *isa_dn; 1045 1046 hose->io_base_virt = reserve_phb_iospace(size); 1047 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", 1048 hose->global_number, hose->io_base_phys, 1049 (unsigned long) hose->io_base_virt); 1050 1051 if (primary) { 1052 pci_io_base = (unsigned long)hose->io_base_virt; 1053 isa_dn = of_find_node_by_type(NULL, "isa"); 1054 if (isa_dn) { 1055 isa_io_base = pci_io_base; 1056 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys, 1057 hose->io_base_virt); 1058 of_node_put(isa_dn); 1059 /* Allow all IO */ 1060 io_page_mask = -1; 1061 } 1062 } 1063 1064 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; 1065 res = &hose->io_resource; 1066 res->start += io_virt_offset; 1067 res->end += io_virt_offset; 1068 } 1069 1070 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose, 1071 int primary) 1072 { 1073 unsigned long size = hose->pci_io_size; 1074 unsigned long io_virt_offset; 1075 struct resource *res; 1076 1077 hose->io_base_virt = __ioremap(hose->io_base_phys, size, 1078 _PAGE_NO_CACHE | _PAGE_GUARDED); 1079 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", 1080 hose->global_number, hose->io_base_phys, 1081 (unsigned long) hose->io_base_virt); 1082 1083 if (primary) 1084 pci_io_base = (unsigned long)hose->io_base_virt; 1085 1086 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; 1087 res = &hose->io_resource; 1088 res->start += io_virt_offset; 1089 res->end += io_virt_offset; 1090 } 1091 1092 1093 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys, 1094 unsigned long *start_virt, unsigned long *size) 1095 { 1096 struct pci_controller *hose = pci_bus_to_host(bus); 1097 struct pci_bus_region region; 1098 struct resource *res; 1099 1100 if (bus->self) { 1101 res = bus->resource[0]; 1102 pcibios_resource_to_bus(bus->self, ®ion, res); 1103 *start_phys = hose->io_base_phys + region.start; 1104 *start_virt = (unsigned long) hose->io_base_virt + 1105 region.start; 1106 if (region.end > region.start) 1107 *size = region.end - region.start + 1; 1108 else { 1109 printk("%s(): unexpected region 0x%lx->0x%lx\n", 1110 __FUNCTION__, region.start, region.end); 1111 return 1; 1112 } 1113 1114 } else { 1115 /* Root Bus */ 1116 res = &hose->io_resource; 1117 *start_phys = hose->io_base_phys; 1118 *start_virt = (unsigned long) hose->io_base_virt; 1119 if (res->end > res->start) 1120 *size = res->end - res->start + 1; 1121 else { 1122 printk("%s(): unexpected region 0x%lx->0x%lx\n", 1123 __FUNCTION__, res->start, res->end); 1124 return 1; 1125 } 1126 } 1127 1128 return 0; 1129 } 1130 1131 int unmap_bus_range(struct pci_bus *bus) 1132 { 1133 unsigned long start_phys; 1134 unsigned long start_virt; 1135 unsigned long size; 1136 1137 if (!bus) { 1138 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); 1139 return 1; 1140 } 1141 1142 if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) 1143 return 1; 1144 if (iounmap_explicit((void __iomem *) start_virt, size)) 1145 return 1; 1146 1147 return 0; 1148 } 1149 EXPORT_SYMBOL(unmap_bus_range); 1150 1151 int remap_bus_range(struct pci_bus *bus) 1152 { 1153 unsigned long start_phys; 1154 unsigned long start_virt; 1155 unsigned long size; 1156 1157 if (!bus) { 1158 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); 1159 return 1; 1160 } 1161 1162 1163 if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) 1164 return 1; 1165 if (start_phys == 0) 1166 return 1; 1167 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size); 1168 if (__ioremap_explicit(start_phys, start_virt, size, 1169 _PAGE_NO_CACHE | _PAGE_GUARDED)) 1170 return 1; 1171 1172 return 0; 1173 } 1174 EXPORT_SYMBOL(remap_bus_range); 1175 1176 void phbs_remap_io(void) 1177 { 1178 struct pci_controller *hose, *tmp; 1179 1180 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1181 remap_bus_range(hose->bus); 1182 } 1183 1184 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) 1185 { 1186 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1187 unsigned long start, end, mask, offset; 1188 1189 if (res->flags & IORESOURCE_IO) { 1190 offset = (unsigned long)hose->io_base_virt - pci_io_base; 1191 1192 start = res->start += offset; 1193 end = res->end += offset; 1194 1195 /* Need to allow IO access to pages that are in the 1196 ISA range */ 1197 if (start < MAX_ISA_PORT) { 1198 if (end > MAX_ISA_PORT) 1199 end = MAX_ISA_PORT; 1200 1201 start >>= PAGE_SHIFT; 1202 end >>= PAGE_SHIFT; 1203 1204 /* get the range of pages for the map */ 1205 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1); 1206 io_page_mask |= mask; 1207 } 1208 } else if (res->flags & IORESOURCE_MEM) { 1209 res->start += hose->pci_mem_offset; 1210 res->end += hose->pci_mem_offset; 1211 } 1212 } 1213 1214 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, 1215 struct pci_bus *bus) 1216 { 1217 /* Update device resources. */ 1218 int i; 1219 1220 for (i = 0; i < PCI_NUM_RESOURCES; i++) 1221 if (dev->resource[i].flags) 1222 fixup_resource(&dev->resource[i], dev); 1223 } 1224 EXPORT_SYMBOL(pcibios_fixup_device_resources); 1225 1226 static void __devinit do_bus_setup(struct pci_bus *bus) 1227 { 1228 struct pci_dev *dev; 1229 1230 ppc_md.iommu_bus_setup(bus); 1231 1232 list_for_each_entry(dev, &bus->devices, bus_list) 1233 ppc_md.iommu_dev_setup(dev); 1234 1235 if (ppc_md.irq_bus_setup) 1236 ppc_md.irq_bus_setup(bus); 1237 } 1238 1239 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1240 { 1241 struct pci_dev *dev = bus->self; 1242 1243 if (dev && pci_probe_only && 1244 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 1245 /* This is a subordinate bridge */ 1246 1247 pci_read_bridge_bases(bus); 1248 pcibios_fixup_device_resources(dev, bus); 1249 } 1250 1251 do_bus_setup(bus); 1252 1253 if (!pci_probe_only) 1254 return; 1255 1256 list_for_each_entry(dev, &bus->devices, bus_list) 1257 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1258 pcibios_fixup_device_resources(dev, bus); 1259 } 1260 EXPORT_SYMBOL(pcibios_fixup_bus); 1261 1262 /* 1263 * Reads the interrupt pin to determine if interrupt is use by card. 1264 * If the interrupt is used, then gets the interrupt line from the 1265 * openfirmware and sets it in the pci_dev and pci_config line. 1266 */ 1267 int pci_read_irq_line(struct pci_dev *pci_dev) 1268 { 1269 u8 intpin; 1270 struct device_node *node; 1271 1272 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin); 1273 if (intpin == 0) 1274 return 0; 1275 1276 node = pci_device_to_OF_node(pci_dev); 1277 if (node == NULL) 1278 return -1; 1279 1280 if (node->n_intrs == 0) 1281 return -1; 1282 1283 pci_dev->irq = node->intrs[0].line; 1284 1285 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq); 1286 1287 return 0; 1288 } 1289 EXPORT_SYMBOL(pci_read_irq_line); 1290 1291 void pci_resource_to_user(const struct pci_dev *dev, int bar, 1292 const struct resource *rsrc, 1293 u64 *start, u64 *end) 1294 { 1295 struct pci_controller *hose = pci_bus_to_host(dev->bus); 1296 unsigned long offset = 0; 1297 1298 if (hose == NULL) 1299 return; 1300 1301 if (rsrc->flags & IORESOURCE_IO) 1302 offset = pci_io_base - (unsigned long)hose->io_base_virt + 1303 hose->io_base_phys; 1304 1305 *start = rsrc->start + offset; 1306 *end = rsrc->end + offset; 1307 } 1308 1309 #endif /* CONFIG_PPC_MULTIPLATFORM */ 1310 1311 1312 #define IOBASE_BRIDGE_NUMBER 0 1313 #define IOBASE_MEMORY 1 1314 #define IOBASE_IO 2 1315 #define IOBASE_ISA_IO 3 1316 #define IOBASE_ISA_MEM 4 1317 1318 long sys_pciconfig_iobase(long which, unsigned long in_bus, 1319 unsigned long in_devfn) 1320 { 1321 struct pci_controller* hose; 1322 struct list_head *ln; 1323 struct pci_bus *bus = NULL; 1324 struct device_node *hose_node; 1325 1326 /* Argh ! Please forgive me for that hack, but that's the 1327 * simplest way to get existing XFree to not lockup on some 1328 * G5 machines... So when something asks for bus 0 io base 1329 * (bus 0 is HT root), we return the AGP one instead. 1330 */ 1331 if (machine_is_compatible("MacRISC4")) 1332 if (in_bus == 0) 1333 in_bus = 0xf0; 1334 1335 /* That syscall isn't quite compatible with PCI domains, but it's 1336 * used on pre-domains setup. We return the first match 1337 */ 1338 1339 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { 1340 bus = pci_bus_b(ln); 1341 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate)) 1342 break; 1343 bus = NULL; 1344 } 1345 if (bus == NULL || bus->sysdata == NULL) 1346 return -ENODEV; 1347 1348 hose_node = (struct device_node *)bus->sysdata; 1349 hose = PCI_DN(hose_node)->phb; 1350 1351 switch (which) { 1352 case IOBASE_BRIDGE_NUMBER: 1353 return (long)hose->first_busno; 1354 case IOBASE_MEMORY: 1355 return (long)hose->pci_mem_offset; 1356 case IOBASE_IO: 1357 return (long)hose->io_base_phys; 1358 case IOBASE_ISA_IO: 1359 return (long)isa_io_base; 1360 case IOBASE_ISA_MEM: 1361 return -EINVAL; 1362 } 1363 1364 return -EOPNOTSUPP; 1365 } 1366