1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com) 8 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 * 15 */ 16 17#include <linux/config.h> 18#include <linux/sys.h> 19#include <asm/unistd.h> 20#include <asm/errno.h> 21#include <asm/processor.h> 22#include <asm/page.h> 23#include <asm/cache.h> 24#include <asm/ppc_asm.h> 25#include <asm/asm-offsets.h> 26#include <asm/cputable.h> 27#include <asm/thread_info.h> 28 29 .text 30 31_GLOBAL(get_msr) 32 mfmsr r3 33 blr 34 35_GLOBAL(get_srr0) 36 mfsrr0 r3 37 blr 38 39_GLOBAL(get_srr1) 40 mfsrr1 r3 41 blr 42 43#ifdef CONFIG_IRQSTACKS 44_GLOBAL(call_do_softirq) 45 mflr r0 46 std r0,16(r1) 47 stdu r1,THREAD_SIZE-112(r3) 48 mr r1,r3 49 bl .__do_softirq 50 ld r1,0(r1) 51 ld r0,16(r1) 52 mtlr r0 53 blr 54 55_GLOBAL(call___do_IRQ) 56 mflr r0 57 std r0,16(r1) 58 stdu r1,THREAD_SIZE-112(r5) 59 mr r1,r5 60 bl .__do_IRQ 61 ld r1,0(r1) 62 ld r0,16(r1) 63 mtlr r0 64 blr 65#endif /* CONFIG_IRQSTACKS */ 66 67 .section ".toc","aw" 68PPC64_CACHES: 69 .tc ppc64_caches[TC],ppc64_caches 70 .section ".text" 71 72/* 73 * Write any modified data cache blocks out to memory 74 * and invalidate the corresponding instruction cache blocks. 75 * 76 * flush_icache_range(unsigned long start, unsigned long stop) 77 * 78 * flush all bytes from start through stop-1 inclusive 79 */ 80 81_KPROBE(__flush_icache_range) 82 83/* 84 * Flush the data cache to memory 85 * 86 * Different systems have different cache line sizes 87 * and in some cases i-cache and d-cache line sizes differ from 88 * each other. 89 */ 90 ld r10,PPC64_CACHES@toc(r2) 91 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */ 92 addi r5,r7,-1 93 andc r6,r3,r5 /* round low to line bdy */ 94 subf r8,r6,r4 /* compute length */ 95 add r8,r8,r5 /* ensure we get enough */ 96 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */ 97 srw. r8,r8,r9 /* compute line count */ 98 beqlr /* nothing to do? */ 99 mtctr r8 1001: dcbst 0,r6 101 add r6,r6,r7 102 bdnz 1b 103 sync 104 105/* Now invalidate the instruction cache */ 106 107 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */ 108 addi r5,r7,-1 109 andc r6,r3,r5 /* round low to line bdy */ 110 subf r8,r6,r4 /* compute length */ 111 add r8,r8,r5 112 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */ 113 srw. r8,r8,r9 /* compute line count */ 114 beqlr /* nothing to do? */ 115 mtctr r8 1162: icbi 0,r6 117 add r6,r6,r7 118 bdnz 2b 119 isync 120 blr 121 .previous .text 122/* 123 * Like above, but only do the D-cache. 124 * 125 * flush_dcache_range(unsigned long start, unsigned long stop) 126 * 127 * flush all bytes from start to stop-1 inclusive 128 */ 129_GLOBAL(flush_dcache_range) 130 131/* 132 * Flush the data cache to memory 133 * 134 * Different systems have different cache line sizes 135 */ 136 ld r10,PPC64_CACHES@toc(r2) 137 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ 138 addi r5,r7,-1 139 andc r6,r3,r5 /* round low to line bdy */ 140 subf r8,r6,r4 /* compute length */ 141 add r8,r8,r5 /* ensure we get enough */ 142 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ 143 srw. r8,r8,r9 /* compute line count */ 144 beqlr /* nothing to do? */ 145 mtctr r8 1460: dcbst 0,r6 147 add r6,r6,r7 148 bdnz 0b 149 sync 150 blr 151 152/* 153 * Like above, but works on non-mapped physical addresses. 154 * Use only for non-LPAR setups ! It also assumes real mode 155 * is cacheable. Used for flushing out the DART before using 156 * it as uncacheable memory 157 * 158 * flush_dcache_phys_range(unsigned long start, unsigned long stop) 159 * 160 * flush all bytes from start to stop-1 inclusive 161 */ 162_GLOBAL(flush_dcache_phys_range) 163 ld r10,PPC64_CACHES@toc(r2) 164 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ 165 addi r5,r7,-1 166 andc r6,r3,r5 /* round low to line bdy */ 167 subf r8,r6,r4 /* compute length */ 168 add r8,r8,r5 /* ensure we get enough */ 169 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ 170 srw. r8,r8,r9 /* compute line count */ 171 beqlr /* nothing to do? */ 172 mfmsr r5 /* Disable MMU Data Relocation */ 173 ori r0,r5,MSR_DR 174 xori r0,r0,MSR_DR 175 sync 176 mtmsr r0 177 sync 178 isync 179 mtctr r8 1800: dcbst 0,r6 181 add r6,r6,r7 182 bdnz 0b 183 sync 184 isync 185 mtmsr r5 /* Re-enable MMU Data Relocation */ 186 sync 187 isync 188 blr 189 190_GLOBAL(flush_inval_dcache_range) 191 ld r10,PPC64_CACHES@toc(r2) 192 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ 193 addi r5,r7,-1 194 andc r6,r3,r5 /* round low to line bdy */ 195 subf r8,r6,r4 /* compute length */ 196 add r8,r8,r5 /* ensure we get enough */ 197 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */ 198 srw. r8,r8,r9 /* compute line count */ 199 beqlr /* nothing to do? */ 200 sync 201 isync 202 mtctr r8 2030: dcbf 0,r6 204 add r6,r6,r7 205 bdnz 0b 206 sync 207 isync 208 blr 209 210 211/* 212 * Flush a particular page from the data cache to RAM. 213 * Note: this is necessary because the instruction cache does *not* 214 * snoop from the data cache. 215 * 216 * void __flush_dcache_icache(void *page) 217 */ 218_GLOBAL(__flush_dcache_icache) 219/* 220 * Flush the data cache to memory 221 * 222 * Different systems have different cache line sizes 223 */ 224 225/* Flush the dcache */ 226 ld r7,PPC64_CACHES@toc(r2) 227 clrrdi r3,r3,PAGE_SHIFT /* Page align */ 228 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */ 229 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */ 230 mr r6,r3 231 mtctr r4 2320: dcbst 0,r6 233 add r6,r6,r5 234 bdnz 0b 235 sync 236 237/* Now invalidate the icache */ 238 239 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */ 240 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */ 241 mtctr r4 2421: icbi 0,r3 243 add r3,r3,r5 244 bdnz 1b 245 isync 246 blr 247 248/* 249 * identify_cpu and calls setup_cpu 250 * In: r3 = base of the cpu_specs array 251 * r4 = address of cur_cpu_spec 252 * r5 = relocation offset 253 */ 254_GLOBAL(identify_cpu) 255 mfpvr r7 2561: 257 lwz r8,CPU_SPEC_PVR_MASK(r3) 258 and r8,r8,r7 259 lwz r9,CPU_SPEC_PVR_VALUE(r3) 260 cmplw 0,r9,r8 261 beq 1f 262 addi r3,r3,CPU_SPEC_ENTRY_SIZE 263 b 1b 2641: 265 sub r0,r3,r5 266 std r0,0(r4) 267 ld r4,CPU_SPEC_SETUP(r3) 268 cmpdi 0,r4,0 269 add r4,r4,r5 270 beqlr 271 ld r4,0(r4) 272 add r4,r4,r5 273 mtctr r4 274 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */ 275 mr r4,r3 276 mr r3,r5 277 bctr 278 279/* 280 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups 281 * and writes nop's over sections of code that don't apply for this cpu. 282 * r3 = data offset (not changed) 283 */ 284_GLOBAL(do_cpu_ftr_fixups) 285 /* Get CPU 0 features */ 286 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec) 287 sub r6,r6,r3 288 ld r4,0(r6) 289 sub r4,r4,r3 290 ld r4,CPU_SPEC_FEATURES(r4) 291 /* Get the fixup table */ 292 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup) 293 sub r6,r6,r3 294 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup) 295 sub r7,r7,r3 296 /* Do the fixup */ 2971: cmpld r6,r7 298 bgelr 299 addi r6,r6,32 300 ld r8,-32(r6) /* mask */ 301 and r8,r8,r4 302 ld r9,-24(r6) /* value */ 303 cmpld r8,r9 304 beq 1b 305 ld r8,-16(r6) /* section begin */ 306 ld r9,-8(r6) /* section end */ 307 subf. r9,r8,r9 308 beq 1b 309 /* write nops over the section of code */ 310 /* todo: if large section, add a branch at the start of it */ 311 srwi r9,r9,2 312 mtctr r9 313 sub r8,r8,r3 314 lis r0,0x60000000@h /* nop */ 3153: stw r0,0(r8) 316 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l 317 beq 2f 318 dcbst 0,r8 /* suboptimal, but simpler */ 319 sync 320 icbi 0,r8 3212: addi r8,r8,4 322 bdnz 3b 323 sync /* additional sync needed on g4 */ 324 isync 325 b 1b 326 327#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) 328/* 329 * Do an IO access in real mode 330 */ 331_GLOBAL(real_readb) 332 mfmsr r7 333 ori r0,r7,MSR_DR 334 xori r0,r0,MSR_DR 335 sync 336 mtmsrd r0 337 sync 338 isync 339 mfspr r6,SPRN_HID4 340 rldicl r5,r6,32,0 341 ori r5,r5,0x100 342 rldicl r5,r5,32,0 343 sync 344 mtspr SPRN_HID4,r5 345 isync 346 slbia 347 isync 348 lbz r3,0(r3) 349 sync 350 mtspr SPRN_HID4,r6 351 isync 352 slbia 353 isync 354 mtmsrd r7 355 sync 356 isync 357 blr 358 359 /* 360 * Do an IO access in real mode 361 */ 362_GLOBAL(real_writeb) 363 mfmsr r7 364 ori r0,r7,MSR_DR 365 xori r0,r0,MSR_DR 366 sync 367 mtmsrd r0 368 sync 369 isync 370 mfspr r6,SPRN_HID4 371 rldicl r5,r6,32,0 372 ori r5,r5,0x100 373 rldicl r5,r5,32,0 374 sync 375 mtspr SPRN_HID4,r5 376 isync 377 slbia 378 isync 379 stb r3,0(r4) 380 sync 381 mtspr SPRN_HID4,r6 382 isync 383 slbia 384 isync 385 mtmsrd r7 386 sync 387 isync 388 blr 389#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ 390 391#ifdef CONFIG_CPU_FREQ_PMAC64 392/* 393 * SCOM access functions for 970 (FX only for now) 394 * 395 * unsigned long scom970_read(unsigned int address); 396 * void scom970_write(unsigned int address, unsigned long value); 397 * 398 * The address passed in is the 24 bits register address. This code 399 * is 970 specific and will not check the status bits, so you should 400 * know what you are doing. 401 */ 402_GLOBAL(scom970_read) 403 /* interrupts off */ 404 mfmsr r4 405 ori r0,r4,MSR_EE 406 xori r0,r0,MSR_EE 407 mtmsrd r0,1 408 409 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits 410 * (including parity). On current CPUs they must be 0'd, 411 * and finally or in RW bit 412 */ 413 rlwinm r3,r3,8,0,15 414 ori r3,r3,0x8000 415 416 /* do the actual scom read */ 417 sync 418 mtspr SPRN_SCOMC,r3 419 isync 420 mfspr r3,SPRN_SCOMD 421 isync 422 mfspr r0,SPRN_SCOMC 423 isync 424 425 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah 426 * that's the best we can do). Not implemented yet as we don't use 427 * the scom on any of the bogus CPUs yet, but may have to be done 428 * ultimately 429 */ 430 431 /* restore interrupts */ 432 mtmsrd r4,1 433 blr 434 435 436_GLOBAL(scom970_write) 437 /* interrupts off */ 438 mfmsr r5 439 ori r0,r5,MSR_EE 440 xori r0,r0,MSR_EE 441 mtmsrd r0,1 442 443 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits 444 * (including parity). On current CPUs they must be 0'd. 445 */ 446 447 rlwinm r3,r3,8,0,15 448 449 sync 450 mtspr SPRN_SCOMD,r4 /* write data */ 451 isync 452 mtspr SPRN_SCOMC,r3 /* write command */ 453 isync 454 mfspr 3,SPRN_SCOMC 455 isync 456 457 /* restore interrupts */ 458 mtmsrd r5,1 459 blr 460#endif /* CONFIG_CPU_FREQ_PMAC64 */ 461 462 463/* 464 * Create a kernel thread 465 * kernel_thread(fn, arg, flags) 466 */ 467_GLOBAL(kernel_thread) 468 std r29,-24(r1) 469 std r30,-16(r1) 470 stdu r1,-STACK_FRAME_OVERHEAD(r1) 471 mr r29,r3 472 mr r30,r4 473 ori r3,r5,CLONE_VM /* flags */ 474 oris r3,r3,(CLONE_UNTRACED>>16) 475 li r4,0 /* new sp (unused) */ 476 li r0,__NR_clone 477 sc 478 cmpdi 0,r3,0 /* parent or child? */ 479 bne 1f /* return if parent */ 480 li r0,0 481 stdu r0,-STACK_FRAME_OVERHEAD(r1) 482 ld r2,8(r29) 483 ld r29,0(r29) 484 mtlr r29 /* fn addr in lr */ 485 mr r3,r30 /* load arg and call fn */ 486 blrl 487 li r0,__NR_exit /* exit after child exits */ 488 li r3,0 489 sc 4901: addi r1,r1,STACK_FRAME_OVERHEAD 491 ld r29,-24(r1) 492 ld r30,-16(r1) 493 blr 494 495/* 496 * disable_kernel_fp() 497 * Disable the FPU. 498 */ 499_GLOBAL(disable_kernel_fp) 500 mfmsr r3 501 rldicl r0,r3,(63-MSR_FP_LG),1 502 rldicl r3,r0,(MSR_FP_LG+1),0 503 mtmsrd r3 /* disable use of fpu now */ 504 isync 505 blr 506 507#ifdef CONFIG_ALTIVEC 508 509#if 0 /* this has no callers for now */ 510/* 511 * disable_kernel_altivec() 512 * Disable the VMX. 513 */ 514_GLOBAL(disable_kernel_altivec) 515 mfmsr r3 516 rldicl r0,r3,(63-MSR_VEC_LG),1 517 rldicl r3,r0,(MSR_VEC_LG+1),0 518 mtmsrd r3 /* disable use of VMX now */ 519 isync 520 blr 521#endif /* 0 */ 522 523/* 524 * giveup_altivec(tsk) 525 * Disable VMX for the task given as the argument, 526 * and save the vector registers in its thread_struct. 527 * Enables the VMX for use in the kernel on return. 528 */ 529_GLOBAL(giveup_altivec) 530 mfmsr r5 531 oris r5,r5,MSR_VEC@h 532 mtmsrd r5 /* enable use of VMX now */ 533 isync 534 cmpdi 0,r3,0 535 beqlr- /* if no previous owner, done */ 536 addi r3,r3,THREAD /* want THREAD of task */ 537 ld r5,PT_REGS(r3) 538 cmpdi 0,r5,0 539 SAVE_32VRS(0,r4,r3) 540 mfvscr vr0 541 li r4,THREAD_VSCR 542 stvx vr0,r4,r3 543 beq 1f 544 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 545 lis r3,MSR_VEC@h 546 andc r4,r4,r3 /* disable FP for previous task */ 547 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 5481: 549#ifndef CONFIG_SMP 550 li r5,0 551 ld r4,last_task_used_altivec@got(r2) 552 std r5,0(r4) 553#endif /* CONFIG_SMP */ 554 blr 555 556#endif /* CONFIG_ALTIVEC */ 557 558_GLOBAL(execve) 559 li r0,__NR_execve 560 sc 561 bnslr 562 neg r3,r3 563 blr 564 565/* kexec_wait(phys_cpu) 566 * 567 * wait for the flag to change, indicating this kernel is going away but 568 * the slave code for the next one is at addresses 0 to 100. 569 * 570 * This is used by all slaves. 571 * 572 * Physical (hardware) cpu id should be in r3. 573 */ 574_GLOBAL(kexec_wait) 575 bl 1f 5761: mflr r5 577 addi r5,r5,kexec_flag-1b 578 57999: HMT_LOW 580#ifdef CONFIG_KEXEC /* use no memory without kexec */ 581 lwz r4,0(r5) 582 cmpwi 0,r4,0 583 bnea 0x60 584#endif 585 b 99b 586 587/* this can be in text because we won't change it until we are 588 * running in real anyways 589 */ 590kexec_flag: 591 .long 0 592 593 594#ifdef CONFIG_KEXEC 595 596/* kexec_smp_wait(void) 597 * 598 * call with interrupts off 599 * note: this is a terminal routine, it does not save lr 600 * 601 * get phys id from paca 602 * set paca id to -1 to say we got here 603 * switch to real mode 604 * join other cpus in kexec_wait(phys_id) 605 */ 606_GLOBAL(kexec_smp_wait) 607 lhz r3,PACAHWCPUID(r13) 608 li r4,-1 609 sth r4,PACAHWCPUID(r13) /* let others know we left */ 610 bl real_mode 611 b .kexec_wait 612 613/* 614 * switch to real mode (turn mmu off) 615 * we use the early kernel trick that the hardware ignores bits 616 * 0 and 1 (big endian) of the effective address in real mode 617 * 618 * don't overwrite r3 here, it is live for kexec_wait above. 619 */ 620real_mode: /* assume normal blr return */ 6211: li r9,MSR_RI 622 li r10,MSR_DR|MSR_IR 623 mflr r11 /* return address to SRR0 */ 624 mfmsr r12 625 andc r9,r12,r9 626 andc r10,r12,r10 627 628 mtmsrd r9,1 629 mtspr SPRN_SRR1,r10 630 mtspr SPRN_SRR0,r11 631 rfid 632 633 634/* 635 * kexec_sequence(newstack, start, image, control, clear_all()) 636 * 637 * does the grungy work with stack switching and real mode switches 638 * also does simple calls to other code 639 */ 640 641_GLOBAL(kexec_sequence) 642 mflr r0 643 std r0,16(r1) 644 645 /* switch stacks to newstack -- &kexec_stack.stack */ 646 stdu r1,THREAD_SIZE-112(r3) 647 mr r1,r3 648 649 li r0,0 650 std r0,16(r1) 651 652 /* save regs for local vars on new stack. 653 * yes, we won't go back, but ... 654 */ 655 std r31,-8(r1) 656 std r30,-16(r1) 657 std r29,-24(r1) 658 std r28,-32(r1) 659 std r27,-40(r1) 660 std r26,-48(r1) 661 std r25,-56(r1) 662 663 stdu r1,-112-64(r1) 664 665 /* save args into preserved regs */ 666 mr r31,r3 /* newstack (both) */ 667 mr r30,r4 /* start (real) */ 668 mr r29,r5 /* image (virt) */ 669 mr r28,r6 /* control, unused */ 670 mr r27,r7 /* clear_all() fn desc */ 671 mr r26,r8 /* spare */ 672 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */ 673 674 /* disable interrupts, we are overwriting kernel data next */ 675 mfmsr r3 676 rlwinm r3,r3,0,17,15 677 mtmsrd r3,1 678 679 /* copy dest pages, flush whole dest image */ 680 mr r3,r29 681 bl .kexec_copy_flush /* (image) */ 682 683 /* turn off mmu */ 684 bl real_mode 685 686 /* clear out hardware hash page table and tlb */ 687 ld r5,0(r27) /* deref function descriptor */ 688 mtctr r5 689 bctrl /* ppc_md.hash_clear_all(void); */ 690 691/* 692 * kexec image calling is: 693 * the first 0x100 bytes of the entry point are copied to 0 694 * 695 * all slaves branch to slave = 0x60 (absolute) 696 * slave(phys_cpu_id); 697 * 698 * master goes to start = entry point 699 * start(phys_cpu_id, start, 0); 700 * 701 * 702 * a wrapper is needed to call existing kernels, here is an approximate 703 * description of one method: 704 * 705 * v2: (2.6.10) 706 * start will be near the boot_block (maybe 0x100 bytes before it?) 707 * it will have a 0x60, which will b to boot_block, where it will wait 708 * and 0 will store phys into struct boot-block and load r3 from there, 709 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again 710 * 711 * v1: (2.6.9) 712 * boot block will have all cpus scanning device tree to see if they 713 * are the boot cpu ????? 714 * other device tree differences (prop sizes, va vs pa, etc)... 715 */ 716 717 /* copy 0x100 bytes starting at start to 0 */ 718 li r3,0 719 mr r4,r30 720 li r5,0x100 721 li r6,0 722 bl .copy_and_flush /* (dest, src, copy limit, start offset) */ 7231: /* assume normal blr return */ 724 725 /* release other cpus to the new kernel secondary start at 0x60 */ 726 mflr r5 727 li r6,1 728 stw r6,kexec_flag-1b(5) 729 mr r3,r25 # my phys cpu 730 mr r4,r30 # start, aka phys mem offset 731 mtlr 4 732 li r5,0 733 blr /* image->start(physid, image->start, 0); */ 734#endif /* CONFIG_KEXEC */ 735