1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * 12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 14 * 15 * This file contains the low-level support and setup for the 16 * PowerPC-64 platform, including trap and interrupt dispatch. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/config.h> 25#include <linux/threads.h> 26#include <asm/reg.h> 27#include <asm/page.h> 28#include <asm/mmu.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> 31#include <asm/bug.h> 32#include <asm/cputable.h> 33#include <asm/setup.h> 34#include <asm/hvcall.h> 35#include <asm/iseries/lpar_map.h> 36#include <asm/thread_info.h> 37 38#ifdef CONFIG_PPC_ISERIES 39#define DO_SOFT_DISABLE 40#endif 41 42/* 43 * We layout physical memory as follows: 44 * 0x0000 - 0x00ff : Secondary processor spin code 45 * 0x0100 - 0x2fff : pSeries Interrupt prologs 46 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs 47 * 0x6000 - 0x6fff : Initial (CPU0) segment table 48 * 0x7000 - 0x7fff : FWNMI data area 49 * 0x8000 - : Early init and support code 50 */ 51 52/* 53 * SPRG Usage 54 * 55 * Register Definition 56 * 57 * SPRG0 reserved for hypervisor 58 * SPRG1 temp - used to save gpr 59 * SPRG2 temp - used to save gpr 60 * SPRG3 virt addr of paca 61 */ 62 63/* 64 * Entering into this code we make the following assumptions: 65 * For pSeries: 66 * 1. The MMU is off & open firmware is running in real mode. 67 * 2. The kernel is entered at __start 68 * 69 * For iSeries: 70 * 1. The MMU is on (as it always is for iSeries) 71 * 2. The kernel is entered at system_reset_iSeries 72 */ 73 74 .text 75 .globl _stext 76_stext: 77#ifdef CONFIG_PPC_MULTIPLATFORM 78_GLOBAL(__start) 79 /* NOP this out unconditionally */ 80BEGIN_FTR_SECTION 81 b .__start_initialization_multiplatform 82END_FTR_SECTION(0, 1) 83#endif /* CONFIG_PPC_MULTIPLATFORM */ 84 85 /* Catch branch to 0 in real mode */ 86 trap 87 88#ifdef CONFIG_PPC_ISERIES 89 /* 90 * At offset 0x20, there is a pointer to iSeries LPAR data. 91 * This is required by the hypervisor 92 */ 93 . = 0x20 94 .llong hvReleaseData-KERNELBASE 95 96 /* 97 * At offset 0x28 and 0x30 are offsets to the mschunks_map 98 * array (used by the iSeries LPAR debugger to do translation 99 * between physical addresses and absolute addresses) and 100 * to the pidhash table (also used by the debugger) 101 */ 102 .llong mschunks_map-KERNELBASE 103 .llong 0 /* pidhash-KERNELBASE SFRXXX */ 104 105 /* Offset 0x38 - Pointer to start of embedded System.map */ 106 .globl embedded_sysmap_start 107embedded_sysmap_start: 108 .llong 0 109 /* Offset 0x40 - Pointer to end of embedded System.map */ 110 .globl embedded_sysmap_end 111embedded_sysmap_end: 112 .llong 0 113 114#endif /* CONFIG_PPC_ISERIES */ 115 116 /* Secondary processors spin on this value until it goes to 1. */ 117 .globl __secondary_hold_spinloop 118__secondary_hold_spinloop: 119 .llong 0x0 120 121 /* Secondary processors write this value with their cpu # */ 122 /* after they enter the spin loop immediately below. */ 123 .globl __secondary_hold_acknowledge 124__secondary_hold_acknowledge: 125 .llong 0x0 126 127 . = 0x60 128/* 129 * The following code is used on pSeries to hold secondary processors 130 * in a spin loop after they have been freed from OpenFirmware, but 131 * before the bulk of the kernel has been relocated. This code 132 * is relocated to physical address 0x60 before prom_init is run. 133 * All of it must fit below the first exception vector at 0x100. 134 */ 135_GLOBAL(__secondary_hold) 136 mfmsr r24 137 ori r24,r24,MSR_RI 138 mtmsrd r24 /* RI on */ 139 140 /* Grab our physical cpu number */ 141 mr r24,r3 142 143 /* Tell the master cpu we're here */ 144 /* Relocation is off & we are located at an address less */ 145 /* than 0x100, so only need to grab low order offset. */ 146 std r24,__secondary_hold_acknowledge@l(0) 147 sync 148 149 /* All secondary cpus wait here until told to start. */ 150100: ld r4,__secondary_hold_spinloop@l(0) 151 cmpdi 0,r4,1 152 bne 100b 153 154#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 155 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init) 156 mtctr r4 157 mr r3,r24 158 bctr 159#else 160 BUG_OPCODE 161#endif 162 163/* This value is used to mark exception frames on the stack. */ 164 .section ".toc","aw" 165exception_marker: 166 .tc ID_72656773_68657265[TC],0x7265677368657265 167 .text 168 169/* 170 * The following macros define the code that appears as 171 * the prologue to each of the exception handlers. They 172 * are split into two parts to allow a single kernel binary 173 * to be used for pSeries and iSeries. 174 * LOL. One day... - paulus 175 */ 176 177/* 178 * We make as much of the exception code common between native 179 * exception handlers (including pSeries LPAR) and iSeries LPAR 180 * implementations as possible. 181 */ 182 183/* 184 * This is the start of the interrupt handlers for pSeries 185 * This code runs with relocation off. 186 */ 187#define EX_R9 0 188#define EX_R10 8 189#define EX_R11 16 190#define EX_R12 24 191#define EX_R13 32 192#define EX_SRR0 40 193#define EX_DAR 48 194#define EX_DSISR 56 195#define EX_CCR 60 196#define EX_R3 64 197#define EX_LR 72 198 199/* 200 * We're short on space and time in the exception prolog, so we can't 201 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the 202 * low halfword of the address, but for Kdump we need the whole low 203 * word. 204 */ 205#ifdef CONFIG_CRASH_DUMP 206#define LOAD_HANDLER(reg, label) \ 207 oris reg,reg,(label)@h; /* virt addr of handler ... */ \ 208 ori reg,reg,(label)@l; /* .. and the rest */ 209#else 210#define LOAD_HANDLER(reg, label) \ 211 ori reg,reg,(label)@l; /* virt addr of handler ... */ 212#endif 213 214#define EXCEPTION_PROLOG_PSERIES(area, label) \ 215 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 216 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 217 std r10,area+EX_R10(r13); \ 218 std r11,area+EX_R11(r13); \ 219 std r12,area+EX_R12(r13); \ 220 mfspr r9,SPRN_SPRG1; \ 221 std r9,area+EX_R13(r13); \ 222 mfcr r9; \ 223 clrrdi r12,r13,32; /* get high part of &label */ \ 224 mfmsr r10; \ 225 mfspr r11,SPRN_SRR0; /* save SRR0 */ \ 226 LOAD_HANDLER(r12,label) \ 227 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ 228 mtspr SPRN_SRR0,r12; \ 229 mfspr r12,SPRN_SRR1; /* and SRR1 */ \ 230 mtspr SPRN_SRR1,r10; \ 231 rfid; \ 232 b . /* prevent speculative execution */ 233 234/* 235 * This is the start of the interrupt handlers for iSeries 236 * This code runs with relocation on. 237 */ 238#define EXCEPTION_PROLOG_ISERIES_1(area) \ 239 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ 240 std r9,area+EX_R9(r13); /* save r9 - r12 */ \ 241 std r10,area+EX_R10(r13); \ 242 std r11,area+EX_R11(r13); \ 243 std r12,area+EX_R12(r13); \ 244 mfspr r9,SPRN_SPRG1; \ 245 std r9,area+EX_R13(r13); \ 246 mfcr r9 247 248#define EXCEPTION_PROLOG_ISERIES_2 \ 249 mfmsr r10; \ 250 ld r12,PACALPPACAPTR(r13); \ 251 ld r11,LPPACASRR0(r12); \ 252 ld r12,LPPACASRR1(r12); \ 253 ori r10,r10,MSR_RI; \ 254 mtmsrd r10,1 255 256/* 257 * The common exception prolog is used for all except a few exceptions 258 * such as a segment miss on a kernel address. We have to be prepared 259 * to take another exception from the point where we first touch the 260 * kernel stack onwards. 261 * 262 * On entry r13 points to the paca, r9-r13 are saved in the paca, 263 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 264 * SRR1, and relocation is on. 265 */ 266#define EXCEPTION_PROLOG_COMMON(n, area) \ 267 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 268 mr r10,r1; /* Save r1 */ \ 269 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 270 beq- 1f; \ 271 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 2721: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ 273 bge- cr1,bad_stack; /* abort if it is */ \ 274 std r9,_CCR(r1); /* save CR in stackframe */ \ 275 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 276 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 277 std r10,0(r1); /* make stack chain pointer */ \ 278 std r0,GPR0(r1); /* save r0 in stackframe */ \ 279 std r10,GPR1(r1); /* save r1 in stackframe */ \ 280 ACCOUNT_CPU_USER_ENTRY(r9, r10); \ 281 std r2,GPR2(r1); /* save r2 in stackframe */ \ 282 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 283 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 284 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 285 ld r10,area+EX_R10(r13); \ 286 std r9,GPR9(r1); \ 287 std r10,GPR10(r1); \ 288 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 289 ld r10,area+EX_R12(r13); \ 290 ld r11,area+EX_R13(r13); \ 291 std r9,GPR11(r1); \ 292 std r10,GPR12(r1); \ 293 std r11,GPR13(r1); \ 294 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 295 mflr r9; /* save LR in stackframe */ \ 296 std r9,_LINK(r1); \ 297 mfctr r10; /* save CTR in stackframe */ \ 298 std r10,_CTR(r1); \ 299 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 300 std r11,_XER(r1); \ 301 li r9,(n)+1; \ 302 std r9,_TRAP(r1); /* set trap number */ \ 303 li r10,0; \ 304 ld r11,exception_marker@toc(r2); \ 305 std r10,RESULT(r1); /* clear regs->result */ \ 306 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 307 308/* 309 * Exception vectors. 310 */ 311#define STD_EXCEPTION_PSERIES(n, label) \ 312 . = n; \ 313 .globl label##_pSeries; \ 314label##_pSeries: \ 315 HMT_MEDIUM; \ 316 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 317 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) 318 319#define STD_EXCEPTION_ISERIES(n, label, area) \ 320 .globl label##_iSeries; \ 321label##_iSeries: \ 322 HMT_MEDIUM; \ 323 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 324 EXCEPTION_PROLOG_ISERIES_1(area); \ 325 EXCEPTION_PROLOG_ISERIES_2; \ 326 b label##_common 327 328#define MASKABLE_EXCEPTION_ISERIES(n, label) \ 329 .globl label##_iSeries; \ 330label##_iSeries: \ 331 HMT_MEDIUM; \ 332 mtspr SPRN_SPRG1,r13; /* save r13 */ \ 333 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ 334 lbz r10,PACAPROCENABLED(r13); \ 335 cmpwi 0,r10,0; \ 336 beq- label##_iSeries_masked; \ 337 EXCEPTION_PROLOG_ISERIES_2; \ 338 b label##_common; \ 339 340#ifdef DO_SOFT_DISABLE 341#define DISABLE_INTS \ 342 lbz r10,PACAPROCENABLED(r13); \ 343 li r11,0; \ 344 std r10,SOFTE(r1); \ 345 mfmsr r10; \ 346 stb r11,PACAPROCENABLED(r13); \ 347 ori r10,r10,MSR_EE; \ 348 mtmsrd r10,1 349 350#define ENABLE_INTS \ 351 lbz r10,PACAPROCENABLED(r13); \ 352 mfmsr r11; \ 353 std r10,SOFTE(r1); \ 354 ori r11,r11,MSR_EE; \ 355 mtmsrd r11,1 356 357#else /* hard enable/disable interrupts */ 358#define DISABLE_INTS 359 360#define ENABLE_INTS \ 361 ld r12,_MSR(r1); \ 362 mfmsr r11; \ 363 rlwimi r11,r12,0,MSR_EE; \ 364 mtmsrd r11,1 365 366#endif 367 368#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 369 .align 7; \ 370 .globl label##_common; \ 371label##_common: \ 372 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 373 DISABLE_INTS; \ 374 bl .save_nvgprs; \ 375 addi r3,r1,STACK_FRAME_OVERHEAD; \ 376 bl hdlr; \ 377 b .ret_from_except 378 379#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ 380 .align 7; \ 381 .globl label##_common; \ 382label##_common: \ 383 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 384 DISABLE_INTS; \ 385 bl .ppc64_runlatch_on; \ 386 addi r3,r1,STACK_FRAME_OVERHEAD; \ 387 bl hdlr; \ 388 b .ret_from_except_lite 389 390/* 391 * Start of pSeries system interrupt routines 392 */ 393 . = 0x100 394 .globl __start_interrupts 395__start_interrupts: 396 397 STD_EXCEPTION_PSERIES(0x100, system_reset) 398 399 . = 0x200 400_machine_check_pSeries: 401 HMT_MEDIUM 402 mtspr SPRN_SPRG1,r13 /* save r13 */ 403 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 404 405 . = 0x300 406 .globl data_access_pSeries 407data_access_pSeries: 408 HMT_MEDIUM 409 mtspr SPRN_SPRG1,r13 410BEGIN_FTR_SECTION 411 mtspr SPRN_SPRG2,r12 412 mfspr r13,SPRN_DAR 413 mfspr r12,SPRN_DSISR 414 srdi r13,r13,60 415 rlwimi r13,r12,16,0x20 416 mfcr r12 417 cmpwi r13,0x2c 418 beq .do_stab_bolted_pSeries 419 mtcrf 0x80,r12 420 mfspr r12,SPRN_SPRG2 421END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 422 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 423 424 . = 0x380 425 .globl data_access_slb_pSeries 426data_access_slb_pSeries: 427 HMT_MEDIUM 428 mtspr SPRN_SPRG1,r13 429 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 430 std r3,PACA_EXSLB+EX_R3(r13) 431 mfspr r3,SPRN_DAR 432 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 433 mfcr r9 434#ifdef __DISABLED__ 435 /* Keep that around for when we re-implement dynamic VSIDs */ 436 cmpdi r3,0 437 bge slb_miss_user_pseries 438#endif /* __DISABLED__ */ 439 std r10,PACA_EXSLB+EX_R10(r13) 440 std r11,PACA_EXSLB+EX_R11(r13) 441 std r12,PACA_EXSLB+EX_R12(r13) 442 mfspr r10,SPRN_SPRG1 443 std r10,PACA_EXSLB+EX_R13(r13) 444 mfspr r12,SPRN_SRR1 /* and SRR1 */ 445 b .slb_miss_realmode /* Rel. branch works in real mode */ 446 447 STD_EXCEPTION_PSERIES(0x400, instruction_access) 448 449 . = 0x480 450 .globl instruction_access_slb_pSeries 451instruction_access_slb_pSeries: 452 HMT_MEDIUM 453 mtspr SPRN_SPRG1,r13 454 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 455 std r3,PACA_EXSLB+EX_R3(r13) 456 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ 457 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ 458 mfcr r9 459#ifdef __DISABLED__ 460 /* Keep that around for when we re-implement dynamic VSIDs */ 461 cmpdi r3,0 462 bge slb_miss_user_pseries 463#endif /* __DISABLED__ */ 464 std r10,PACA_EXSLB+EX_R10(r13) 465 std r11,PACA_EXSLB+EX_R11(r13) 466 std r12,PACA_EXSLB+EX_R12(r13) 467 mfspr r10,SPRN_SPRG1 468 std r10,PACA_EXSLB+EX_R13(r13) 469 mfspr r12,SPRN_SRR1 /* and SRR1 */ 470 b .slb_miss_realmode /* Rel. branch works in real mode */ 471 472 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) 473 STD_EXCEPTION_PSERIES(0x600, alignment) 474 STD_EXCEPTION_PSERIES(0x700, program_check) 475 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 476 STD_EXCEPTION_PSERIES(0x900, decrementer) 477 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 478 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 479 480 . = 0xc00 481 .globl system_call_pSeries 482system_call_pSeries: 483 HMT_MEDIUM 484 mr r9,r13 485 mfmsr r10 486 mfspr r13,SPRN_SPRG3 487 mfspr r11,SPRN_SRR0 488 clrrdi r12,r13,32 489 oris r12,r12,system_call_common@h 490 ori r12,r12,system_call_common@l 491 mtspr SPRN_SRR0,r12 492 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 493 mfspr r12,SPRN_SRR1 494 mtspr SPRN_SRR1,r10 495 rfid 496 b . /* prevent speculative execution */ 497 498 STD_EXCEPTION_PSERIES(0xd00, single_step) 499 STD_EXCEPTION_PSERIES(0xe00, trap_0e) 500 501 /* We need to deal with the Altivec unavailable exception 502 * here which is at 0xf20, thus in the middle of the 503 * prolog code of the PerformanceMonitor one. A little 504 * trickery is thus necessary 505 */ 506 . = 0xf00 507 b performance_monitor_pSeries 508 509 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) 510 511 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 512 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 513 514 . = 0x3000 515 516/*** pSeries interrupt support ***/ 517 518 /* moved from 0xf00 */ 519 STD_EXCEPTION_PSERIES(., performance_monitor) 520 521 .align 7 522_GLOBAL(do_stab_bolted_pSeries) 523 mtcrf 0x80,r12 524 mfspr r12,SPRN_SPRG2 525 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 526 527/* 528 * We have some room here we use that to put 529 * the peries slb miss user trampoline code so it's reasonably 530 * away from slb_miss_user_common to avoid problems with rfid 531 * 532 * This is used for when the SLB miss handler has to go virtual, 533 * which doesn't happen for now anymore but will once we re-implement 534 * dynamic VSIDs for shared page tables 535 */ 536#ifdef __DISABLED__ 537slb_miss_user_pseries: 538 std r10,PACA_EXGEN+EX_R10(r13) 539 std r11,PACA_EXGEN+EX_R11(r13) 540 std r12,PACA_EXGEN+EX_R12(r13) 541 mfspr r10,SPRG1 542 ld r11,PACA_EXSLB+EX_R9(r13) 543 ld r12,PACA_EXSLB+EX_R3(r13) 544 std r10,PACA_EXGEN+EX_R13(r13) 545 std r11,PACA_EXGEN+EX_R9(r13) 546 std r12,PACA_EXGEN+EX_R3(r13) 547 clrrdi r12,r13,32 548 mfmsr r10 549 mfspr r11,SRR0 /* save SRR0 */ 550 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ 551 ori r10,r10,MSR_IR|MSR_DR|MSR_RI 552 mtspr SRR0,r12 553 mfspr r12,SRR1 /* and SRR1 */ 554 mtspr SRR1,r10 555 rfid 556 b . /* prevent spec. execution */ 557#endif /* __DISABLED__ */ 558 559/* 560 * Vectors for the FWNMI option. Share common code. 561 */ 562 .globl system_reset_fwnmi 563 .align 7 564system_reset_fwnmi: 565 HMT_MEDIUM 566 mtspr SPRN_SPRG1,r13 /* save r13 */ 567 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) 568 569 .globl machine_check_fwnmi 570 .align 7 571machine_check_fwnmi: 572 HMT_MEDIUM 573 mtspr SPRN_SPRG1,r13 /* save r13 */ 574 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 575 576#ifdef CONFIG_PPC_ISERIES 577/*** ISeries-LPAR interrupt handlers ***/ 578 579 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) 580 581 .globl data_access_iSeries 582data_access_iSeries: 583 mtspr SPRN_SPRG1,r13 584BEGIN_FTR_SECTION 585 mtspr SPRN_SPRG2,r12 586 mfspr r13,SPRN_DAR 587 mfspr r12,SPRN_DSISR 588 srdi r13,r13,60 589 rlwimi r13,r12,16,0x20 590 mfcr r12 591 cmpwi r13,0x2c 592 beq .do_stab_bolted_iSeries 593 mtcrf 0x80,r12 594 mfspr r12,SPRN_SPRG2 595END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 596 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) 597 EXCEPTION_PROLOG_ISERIES_2 598 b data_access_common 599 600.do_stab_bolted_iSeries: 601 mtcrf 0x80,r12 602 mfspr r12,SPRN_SPRG2 603 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) 604 EXCEPTION_PROLOG_ISERIES_2 605 b .do_stab_bolted 606 607 .globl data_access_slb_iSeries 608data_access_slb_iSeries: 609 mtspr SPRN_SPRG1,r13 /* save r13 */ 610 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 611 std r3,PACA_EXSLB+EX_R3(r13) 612 mfspr r3,SPRN_DAR 613 std r9,PACA_EXSLB+EX_R9(r13) 614 mfcr r9 615#ifdef __DISABLED__ 616 cmpdi r3,0 617 bge slb_miss_user_iseries 618#endif 619 std r10,PACA_EXSLB+EX_R10(r13) 620 std r11,PACA_EXSLB+EX_R11(r13) 621 std r12,PACA_EXSLB+EX_R12(r13) 622 mfspr r10,SPRN_SPRG1 623 std r10,PACA_EXSLB+EX_R13(r13) 624 ld r12,PACALPPACAPTR(r13) 625 ld r12,LPPACASRR1(r12) 626 b .slb_miss_realmode 627 628 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) 629 630 .globl instruction_access_slb_iSeries 631instruction_access_slb_iSeries: 632 mtspr SPRN_SPRG1,r13 /* save r13 */ 633 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ 634 std r3,PACA_EXSLB+EX_R3(r13) 635 ld r3,PACALPPACAPTR(r13) 636 ld r3,LPPACASRR0(r3) /* get SRR0 value */ 637 std r9,PACA_EXSLB+EX_R9(r13) 638 mfcr r9 639#ifdef __DISABLED__ 640 cmpdi r3,0 641 bge .slb_miss_user_iseries 642#endif 643 std r10,PACA_EXSLB+EX_R10(r13) 644 std r11,PACA_EXSLB+EX_R11(r13) 645 std r12,PACA_EXSLB+EX_R12(r13) 646 mfspr r10,SPRN_SPRG1 647 std r10,PACA_EXSLB+EX_R13(r13) 648 ld r12,PACALPPACAPTR(r13) 649 ld r12,LPPACASRR1(r12) 650 b .slb_miss_realmode 651 652#ifdef __DISABLED__ 653slb_miss_user_iseries: 654 std r10,PACA_EXGEN+EX_R10(r13) 655 std r11,PACA_EXGEN+EX_R11(r13) 656 std r12,PACA_EXGEN+EX_R12(r13) 657 mfspr r10,SPRG1 658 ld r11,PACA_EXSLB+EX_R9(r13) 659 ld r12,PACA_EXSLB+EX_R3(r13) 660 std r10,PACA_EXGEN+EX_R13(r13) 661 std r11,PACA_EXGEN+EX_R9(r13) 662 std r12,PACA_EXGEN+EX_R3(r13) 663 EXCEPTION_PROLOG_ISERIES_2 664 b slb_miss_user_common 665#endif 666 667 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) 668 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) 669 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) 670 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) 671 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) 672 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) 673 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) 674 675 .globl system_call_iSeries 676system_call_iSeries: 677 mr r9,r13 678 mfspr r13,SPRN_SPRG3 679 EXCEPTION_PROLOG_ISERIES_2 680 b system_call_common 681 682 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) 683 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) 684 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) 685 686 .globl system_reset_iSeries 687system_reset_iSeries: 688 mfspr r13,SPRN_SPRG3 /* Get paca address */ 689 mfmsr r24 690 ori r24,r24,MSR_RI 691 mtmsrd r24 /* RI on */ 692 lhz r24,PACAPACAINDEX(r13) /* Get processor # */ 693 cmpwi 0,r24,0 /* Are we processor 0? */ 694 beq .__start_initialization_iSeries /* Start up the first processor */ 695 mfspr r4,SPRN_CTRLF 696 li r5,CTRL_RUNLATCH /* Turn off the run light */ 697 andc r4,r4,r5 698 mtspr SPRN_CTRLT,r4 699 7001: 701 HMT_LOW 702#ifdef CONFIG_SMP 703 lbz r23,PACAPROCSTART(r13) /* Test if this processor 704 * should start */ 705 sync 706 LOAD_REG_IMMEDIATE(r3,current_set) 707 sldi r28,r24,3 /* get current_set[cpu#] */ 708 ldx r3,r3,r28 709 addi r1,r3,THREAD_SIZE 710 subi r1,r1,STACK_FRAME_OVERHEAD 711 712 cmpwi 0,r23,0 713 beq iSeries_secondary_smp_loop /* Loop until told to go */ 714 bne .__secondary_start /* Loop until told to go */ 715iSeries_secondary_smp_loop: 716 /* Let the Hypervisor know we are alive */ 717 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ 718 lis r3,0x8002 719 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ 720#else /* CONFIG_SMP */ 721 /* Yield the processor. This is required for non-SMP kernels 722 which are running on multi-threaded machines. */ 723 lis r3,0x8000 724 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ 725 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ 726 li r4,0 /* "yield timed" */ 727 li r5,-1 /* "yield forever" */ 728#endif /* CONFIG_SMP */ 729 li r0,-1 /* r0=-1 indicates a Hypervisor call */ 730 sc /* Invoke the hypervisor via a system call */ 731 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ 732 b 1b /* If SMP not configured, secondaries 733 * loop forever */ 734 735 .globl decrementer_iSeries_masked 736decrementer_iSeries_masked: 737 /* We may not have a valid TOC pointer in here. */ 738 li r11,1 739 ld r12,PACALPPACAPTR(r13) 740 stb r11,LPPACADECRINT(r12) 741 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) 742 lwz r12,0(r12) 743 mtspr SPRN_DEC,r12 744 /* fall through */ 745 746 .globl hardware_interrupt_iSeries_masked 747hardware_interrupt_iSeries_masked: 748 mtcrf 0x80,r9 /* Restore regs */ 749 ld r12,PACALPPACAPTR(r13) 750 ld r11,LPPACASRR0(r12) 751 ld r12,LPPACASRR1(r12) 752 mtspr SPRN_SRR0,r11 753 mtspr SPRN_SRR1,r12 754 ld r9,PACA_EXGEN+EX_R9(r13) 755 ld r10,PACA_EXGEN+EX_R10(r13) 756 ld r11,PACA_EXGEN+EX_R11(r13) 757 ld r12,PACA_EXGEN+EX_R12(r13) 758 ld r13,PACA_EXGEN+EX_R13(r13) 759 rfid 760 b . /* prevent speculative execution */ 761#endif /* CONFIG_PPC_ISERIES */ 762 763/*** Common interrupt handlers ***/ 764 765 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) 766 767 /* 768 * Machine check is different because we use a different 769 * save area: PACA_EXMC instead of PACA_EXGEN. 770 */ 771 .align 7 772 .globl machine_check_common 773machine_check_common: 774 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) 775 DISABLE_INTS 776 bl .save_nvgprs 777 addi r3,r1,STACK_FRAME_OVERHEAD 778 bl .machine_check_exception 779 b .ret_from_except 780 781 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) 782 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) 783 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 784 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 785 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 786 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) 787 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) 788#ifdef CONFIG_ALTIVEC 789 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) 790#else 791 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) 792#endif 793 794/* 795 * Here we have detected that the kernel stack pointer is bad. 796 * R9 contains the saved CR, r13 points to the paca, 797 * r10 contains the (bad) kernel stack pointer, 798 * r11 and r12 contain the saved SRR0 and SRR1. 799 * We switch to using an emergency stack, save the registers there, 800 * and call kernel_bad_stack(), which panics. 801 */ 802bad_stack: 803 ld r1,PACAEMERGSP(r13) 804 subi r1,r1,64+INT_FRAME_SIZE 805 std r9,_CCR(r1) 806 std r10,GPR1(r1) 807 std r11,_NIP(r1) 808 std r12,_MSR(r1) 809 mfspr r11,SPRN_DAR 810 mfspr r12,SPRN_DSISR 811 std r11,_DAR(r1) 812 std r12,_DSISR(r1) 813 mflr r10 814 mfctr r11 815 mfxer r12 816 std r10,_LINK(r1) 817 std r11,_CTR(r1) 818 std r12,_XER(r1) 819 SAVE_GPR(0,r1) 820 SAVE_GPR(2,r1) 821 SAVE_4GPRS(3,r1) 822 SAVE_2GPRS(7,r1) 823 SAVE_10GPRS(12,r1) 824 SAVE_10GPRS(22,r1) 825 addi r11,r1,INT_FRAME_SIZE 826 std r11,0(r1) 827 li r12,0 828 std r12,0(r11) 829 ld r2,PACATOC(r13) 8301: addi r3,r1,STACK_FRAME_OVERHEAD 831 bl .kernel_bad_stack 832 b 1b 833 834/* 835 * Return from an exception with minimal checks. 836 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. 837 * If interrupts have been enabled, or anything has been 838 * done that might have changed the scheduling status of 839 * any task or sent any task a signal, you should use 840 * ret_from_except or ret_from_except_lite instead of this. 841 */ 842 .globl fast_exception_return 843fast_exception_return: 844 ld r12,_MSR(r1) 845 ld r11,_NIP(r1) 846 andi. r3,r12,MSR_RI /* check if RI is set */ 847 beq- unrecov_fer 848 849#ifdef CONFIG_VIRT_CPU_ACCOUNTING 850 andi. r3,r12,MSR_PR 851 beq 2f 852 ACCOUNT_CPU_USER_EXIT(r3, r4) 8532: 854#endif 855 856 ld r3,_CCR(r1) 857 ld r4,_LINK(r1) 858 ld r5,_CTR(r1) 859 ld r6,_XER(r1) 860 mtcr r3 861 mtlr r4 862 mtctr r5 863 mtxer r6 864 REST_GPR(0, r1) 865 REST_8GPRS(2, r1) 866 867 mfmsr r10 868 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ 869 mtmsrd r10,1 870 871 mtspr SPRN_SRR1,r12 872 mtspr SPRN_SRR0,r11 873 REST_4GPRS(10, r1) 874 ld r1,GPR1(r1) 875 rfid 876 b . /* prevent speculative execution */ 877 878unrecov_fer: 879 bl .save_nvgprs 8801: addi r3,r1,STACK_FRAME_OVERHEAD 881 bl .unrecoverable_exception 882 b 1b 883 884/* 885 * Here r13 points to the paca, r9 contains the saved CR, 886 * SRR0 and SRR1 are saved in r11 and r12, 887 * r9 - r13 are saved in paca->exgen. 888 */ 889 .align 7 890 .globl data_access_common 891data_access_common: 892 mfspr r10,SPRN_DAR 893 std r10,PACA_EXGEN+EX_DAR(r13) 894 mfspr r10,SPRN_DSISR 895 stw r10,PACA_EXGEN+EX_DSISR(r13) 896 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) 897 ld r3,PACA_EXGEN+EX_DAR(r13) 898 lwz r4,PACA_EXGEN+EX_DSISR(r13) 899 li r5,0x300 900 b .do_hash_page /* Try to handle as hpte fault */ 901 902 .align 7 903 .globl instruction_access_common 904instruction_access_common: 905 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) 906 ld r3,_NIP(r1) 907 andis. r4,r12,0x5820 908 li r5,0x400 909 b .do_hash_page /* Try to handle as hpte fault */ 910 911/* 912 * Here is the common SLB miss user that is used when going to virtual 913 * mode for SLB misses, that is currently not used 914 */ 915#ifdef __DISABLED__ 916 .align 7 917 .globl slb_miss_user_common 918slb_miss_user_common: 919 mflr r10 920 std r3,PACA_EXGEN+EX_DAR(r13) 921 stw r9,PACA_EXGEN+EX_CCR(r13) 922 std r10,PACA_EXGEN+EX_LR(r13) 923 std r11,PACA_EXGEN+EX_SRR0(r13) 924 bl .slb_allocate_user 925 926 ld r10,PACA_EXGEN+EX_LR(r13) 927 ld r3,PACA_EXGEN+EX_R3(r13) 928 lwz r9,PACA_EXGEN+EX_CCR(r13) 929 ld r11,PACA_EXGEN+EX_SRR0(r13) 930 mtlr r10 931 beq- slb_miss_fault 932 933 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 934 beq- unrecov_user_slb 935 mfmsr r10 936 937.machine push 938.machine "power4" 939 mtcrf 0x80,r9 940.machine pop 941 942 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ 943 mtmsrd r10,1 944 945 mtspr SRR0,r11 946 mtspr SRR1,r12 947 948 ld r9,PACA_EXGEN+EX_R9(r13) 949 ld r10,PACA_EXGEN+EX_R10(r13) 950 ld r11,PACA_EXGEN+EX_R11(r13) 951 ld r12,PACA_EXGEN+EX_R12(r13) 952 ld r13,PACA_EXGEN+EX_R13(r13) 953 rfid 954 b . 955 956slb_miss_fault: 957 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) 958 ld r4,PACA_EXGEN+EX_DAR(r13) 959 li r5,0 960 std r4,_DAR(r1) 961 std r5,_DSISR(r1) 962 b .handle_page_fault 963 964unrecov_user_slb: 965 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) 966 DISABLE_INTS 967 bl .save_nvgprs 9681: addi r3,r1,STACK_FRAME_OVERHEAD 969 bl .unrecoverable_exception 970 b 1b 971 972#endif /* __DISABLED__ */ 973 974 975/* 976 * r13 points to the PACA, r9 contains the saved CR, 977 * r12 contain the saved SRR1, SRR0 is still ready for return 978 * r3 has the faulting address 979 * r9 - r13 are saved in paca->exslb. 980 * r3 is saved in paca->slb_r3 981 * We assume we aren't going to take any exceptions during this procedure. 982 */ 983_GLOBAL(slb_miss_realmode) 984 mflr r10 985 986 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 987 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ 988 989 bl .slb_allocate_realmode 990 991 /* All done -- return from exception. */ 992 993 ld r10,PACA_EXSLB+EX_LR(r13) 994 ld r3,PACA_EXSLB+EX_R3(r13) 995 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 996#ifdef CONFIG_PPC_ISERIES 997 ld r11,PACALPPACAPTR(r13) 998 ld r11,LPPACASRR0(r11) /* get SRR0 value */ 999#endif /* CONFIG_PPC_ISERIES */ 1000 1001 mtlr r10 1002 1003 andi. r10,r12,MSR_RI /* check for unrecoverable exception */ 1004 beq- unrecov_slb 1005 1006.machine push 1007.machine "power4" 1008 mtcrf 0x80,r9 1009 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ 1010.machine pop 1011 1012#ifdef CONFIG_PPC_ISERIES 1013 mtspr SPRN_SRR0,r11 1014 mtspr SPRN_SRR1,r12 1015#endif /* CONFIG_PPC_ISERIES */ 1016 ld r9,PACA_EXSLB+EX_R9(r13) 1017 ld r10,PACA_EXSLB+EX_R10(r13) 1018 ld r11,PACA_EXSLB+EX_R11(r13) 1019 ld r12,PACA_EXSLB+EX_R12(r13) 1020 ld r13,PACA_EXSLB+EX_R13(r13) 1021 rfid 1022 b . /* prevent speculative execution */ 1023 1024unrecov_slb: 1025 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) 1026 DISABLE_INTS 1027 bl .save_nvgprs 10281: addi r3,r1,STACK_FRAME_OVERHEAD 1029 bl .unrecoverable_exception 1030 b 1b 1031 1032 .align 7 1033 .globl hardware_interrupt_common 1034 .globl hardware_interrupt_entry 1035hardware_interrupt_common: 1036 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) 1037hardware_interrupt_entry: 1038 DISABLE_INTS 1039 bl .ppc64_runlatch_on 1040 addi r3,r1,STACK_FRAME_OVERHEAD 1041 bl .do_IRQ 1042 b .ret_from_except_lite 1043 1044 .align 7 1045 .globl alignment_common 1046alignment_common: 1047 mfspr r10,SPRN_DAR 1048 std r10,PACA_EXGEN+EX_DAR(r13) 1049 mfspr r10,SPRN_DSISR 1050 stw r10,PACA_EXGEN+EX_DSISR(r13) 1051 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) 1052 ld r3,PACA_EXGEN+EX_DAR(r13) 1053 lwz r4,PACA_EXGEN+EX_DSISR(r13) 1054 std r3,_DAR(r1) 1055 std r4,_DSISR(r1) 1056 bl .save_nvgprs 1057 addi r3,r1,STACK_FRAME_OVERHEAD 1058 ENABLE_INTS 1059 bl .alignment_exception 1060 b .ret_from_except 1061 1062 .align 7 1063 .globl program_check_common 1064program_check_common: 1065 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) 1066 bl .save_nvgprs 1067 addi r3,r1,STACK_FRAME_OVERHEAD 1068 ENABLE_INTS 1069 bl .program_check_exception 1070 b .ret_from_except 1071 1072 .align 7 1073 .globl fp_unavailable_common 1074fp_unavailable_common: 1075 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) 1076 bne .load_up_fpu /* if from user, just load it up */ 1077 bl .save_nvgprs 1078 addi r3,r1,STACK_FRAME_OVERHEAD 1079 ENABLE_INTS 1080 bl .kernel_fp_unavailable_exception 1081 BUG_OPCODE 1082 1083 .align 7 1084 .globl altivec_unavailable_common 1085altivec_unavailable_common: 1086 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) 1087#ifdef CONFIG_ALTIVEC 1088BEGIN_FTR_SECTION 1089 bne .load_up_altivec /* if from user, just load it up */ 1090END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1091#endif 1092 bl .save_nvgprs 1093 addi r3,r1,STACK_FRAME_OVERHEAD 1094 ENABLE_INTS 1095 bl .altivec_unavailable_exception 1096 b .ret_from_except 1097 1098#ifdef CONFIG_ALTIVEC 1099/* 1100 * load_up_altivec(unused, unused, tsk) 1101 * Disable VMX for the task which had it previously, 1102 * and save its vector registers in its thread_struct. 1103 * Enables the VMX for use in the kernel on return. 1104 * On SMP we know the VMX is free, since we give it up every 1105 * switch (ie, no lazy save of the vector registers). 1106 * On entry: r13 == 'current' && last_task_used_altivec != 'current' 1107 */ 1108_STATIC(load_up_altivec) 1109 mfmsr r5 /* grab the current MSR */ 1110 oris r5,r5,MSR_VEC@h 1111 mtmsrd r5 /* enable use of VMX now */ 1112 isync 1113 1114/* 1115 * For SMP, we don't do lazy VMX switching because it just gets too 1116 * horrendously complex, especially when a task switches from one CPU 1117 * to another. Instead we call giveup_altvec in switch_to. 1118 * VRSAVE isn't dealt with here, that is done in the normal context 1119 * switch code. Note that we could rely on vrsave value to eventually 1120 * avoid saving all of the VREGs here... 1121 */ 1122#ifndef CONFIG_SMP 1123 ld r3,last_task_used_altivec@got(r2) 1124 ld r4,0(r3) 1125 cmpdi 0,r4,0 1126 beq 1f 1127 /* Save VMX state to last_task_used_altivec's THREAD struct */ 1128 addi r4,r4,THREAD 1129 SAVE_32VRS(0,r5,r4) 1130 mfvscr vr0 1131 li r10,THREAD_VSCR 1132 stvx vr0,r10,r4 1133 /* Disable VMX for last_task_used_altivec */ 1134 ld r5,PT_REGS(r4) 1135 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1136 lis r6,MSR_VEC@h 1137 andc r4,r4,r6 1138 std r4,_MSR-STACK_FRAME_OVERHEAD(r5) 11391: 1140#endif /* CONFIG_SMP */ 1141 /* Hack: if we get an altivec unavailable trap with VRSAVE 1142 * set to all zeros, we assume this is a broken application 1143 * that fails to set it properly, and thus we switch it to 1144 * all 1's 1145 */ 1146 mfspr r4,SPRN_VRSAVE 1147 cmpdi 0,r4,0 1148 bne+ 1f 1149 li r4,-1 1150 mtspr SPRN_VRSAVE,r4 11511: 1152 /* enable use of VMX after return */ 1153 ld r4,PACACURRENT(r13) 1154 addi r5,r4,THREAD /* Get THREAD */ 1155 oris r12,r12,MSR_VEC@h 1156 std r12,_MSR(r1) 1157 li r4,1 1158 li r10,THREAD_VSCR 1159 stw r4,THREAD_USED_VR(r5) 1160 lvx vr0,r10,r5 1161 mtvscr vr0 1162 REST_32VRS(0,r4,r5) 1163#ifndef CONFIG_SMP 1164 /* Update last_task_used_math to 'current' */ 1165 subi r4,r5,THREAD /* Back to 'current' */ 1166 std r4,0(r3) 1167#endif /* CONFIG_SMP */ 1168 /* restore registers and return */ 1169 b fast_exception_return 1170#endif /* CONFIG_ALTIVEC */ 1171 1172/* 1173 * Hash table stuff 1174 */ 1175 .align 7 1176_GLOBAL(do_hash_page) 1177 std r3,_DAR(r1) 1178 std r4,_DSISR(r1) 1179 1180 andis. r0,r4,0xa450 /* weird error? */ 1181 bne- .handle_page_fault /* if not, try to insert a HPTE */ 1182BEGIN_FTR_SECTION 1183 andis. r0,r4,0x0020 /* Is it a segment table fault? */ 1184 bne- .do_ste_alloc /* If so handle it */ 1185END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 1186 1187 /* 1188 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are 1189 * accessing a userspace segment (even from the kernel). We assume 1190 * kernel addresses always have the high bit set. 1191 */ 1192 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ 1193 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ 1194 orc r0,r12,r0 /* MSR_PR | ~high_bit */ 1195 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ 1196 ori r4,r4,1 /* add _PAGE_PRESENT */ 1197 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ 1198 1199 /* 1200 * On iSeries, we soft-disable interrupts here, then 1201 * hard-enable interrupts so that the hash_page code can spin on 1202 * the hash_table_lock without problems on a shared processor. 1203 */ 1204 DISABLE_INTS 1205 1206 /* 1207 * r3 contains the faulting address 1208 * r4 contains the required access permissions 1209 * r5 contains the trap number 1210 * 1211 * at return r3 = 0 for success 1212 */ 1213 bl .hash_page /* build HPTE if possible */ 1214 cmpdi r3,0 /* see if hash_page succeeded */ 1215 1216#ifdef DO_SOFT_DISABLE 1217 /* 1218 * If we had interrupts soft-enabled at the point where the 1219 * DSI/ISI occurred, and an interrupt came in during hash_page, 1220 * handle it now. 1221 * We jump to ret_from_except_lite rather than fast_exception_return 1222 * because ret_from_except_lite will check for and handle pending 1223 * interrupts if necessary. 1224 */ 1225 beq .ret_from_except_lite 1226 /* For a hash failure, we don't bother re-enabling interrupts */ 1227 ble- 12f 1228 1229 /* 1230 * hash_page couldn't handle it, set soft interrupt enable back 1231 * to what it was before the trap. Note that .local_irq_restore 1232 * handles any interrupts pending at this point. 1233 */ 1234 ld r3,SOFTE(r1) 1235 bl .local_irq_restore 1236 b 11f 1237#else 1238 beq fast_exception_return /* Return from exception on success */ 1239 ble- 12f /* Failure return from hash_page */ 1240 1241 /* fall through */ 1242#endif 1243 1244/* Here we have a page fault that hash_page can't handle. */ 1245_GLOBAL(handle_page_fault) 1246 ENABLE_INTS 124711: ld r4,_DAR(r1) 1248 ld r5,_DSISR(r1) 1249 addi r3,r1,STACK_FRAME_OVERHEAD 1250 bl .do_page_fault 1251 cmpdi r3,0 1252 beq+ .ret_from_except_lite 1253 bl .save_nvgprs 1254 mr r5,r3 1255 addi r3,r1,STACK_FRAME_OVERHEAD 1256 lwz r4,_DAR(r1) 1257 bl .bad_page_fault 1258 b .ret_from_except 1259 1260/* We have a page fault that hash_page could handle but HV refused 1261 * the PTE insertion 1262 */ 126312: bl .save_nvgprs 1264 addi r3,r1,STACK_FRAME_OVERHEAD 1265 lwz r4,_DAR(r1) 1266 bl .low_hash_fault 1267 b .ret_from_except 1268 1269 /* here we have a segment miss */ 1270_GLOBAL(do_ste_alloc) 1271 bl .ste_allocate /* try to insert stab entry */ 1272 cmpdi r3,0 1273 beq+ fast_exception_return 1274 b .handle_page_fault 1275 1276/* 1277 * r13 points to the PACA, r9 contains the saved CR, 1278 * r11 and r12 contain the saved SRR0 and SRR1. 1279 * r9 - r13 are saved in paca->exslb. 1280 * We assume we aren't going to take any exceptions during this procedure. 1281 * We assume (DAR >> 60) == 0xc. 1282 */ 1283 .align 7 1284_GLOBAL(do_stab_bolted) 1285 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ 1286 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ 1287 1288 /* Hash to the primary group */ 1289 ld r10,PACASTABVIRT(r13) 1290 mfspr r11,SPRN_DAR 1291 srdi r11,r11,28 1292 rldimi r10,r11,7,52 /* r10 = first ste of the group */ 1293 1294 /* Calculate VSID */ 1295 /* This is a kernel address, so protovsid = ESID */ 1296 ASM_VSID_SCRAMBLE(r11, r9) 1297 rldic r9,r11,12,16 /* r9 = vsid << 12 */ 1298 1299 /* Search the primary group for a free entry */ 13001: ld r11,0(r10) /* Test valid bit of the current ste */ 1301 andi. r11,r11,0x80 1302 beq 2f 1303 addi r10,r10,16 1304 andi. r11,r10,0x70 1305 bne 1b 1306 1307 /* Stick for only searching the primary group for now. */ 1308 /* At least for now, we use a very simple random castout scheme */ 1309 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ 1310 mftb r11 1311 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ 1312 ori r11,r11,0x10 1313 1314 /* r10 currently points to an ste one past the group of interest */ 1315 /* make it point to the randomly selected entry */ 1316 subi r10,r10,128 1317 or r10,r10,r11 /* r10 is the entry to invalidate */ 1318 1319 isync /* mark the entry invalid */ 1320 ld r11,0(r10) 1321 rldicl r11,r11,56,1 /* clear the valid bit */ 1322 rotldi r11,r11,8 1323 std r11,0(r10) 1324 sync 1325 1326 clrrdi r11,r11,28 /* Get the esid part of the ste */ 1327 slbie r11 1328 13292: std r9,8(r10) /* Store the vsid part of the ste */ 1330 eieio 1331 1332 mfspr r11,SPRN_DAR /* Get the new esid */ 1333 clrrdi r11,r11,28 /* Permits a full 32b of ESID */ 1334 ori r11,r11,0x90 /* Turn on valid and kp */ 1335 std r11,0(r10) /* Put new entry back into the stab */ 1336 1337 sync 1338 1339 /* All done -- return from exception. */ 1340 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ 1341 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ 1342 1343 andi. r10,r12,MSR_RI 1344 beq- unrecov_slb 1345 1346 mtcrf 0x80,r9 /* restore CR */ 1347 1348 mfmsr r10 1349 clrrdi r10,r10,2 1350 mtmsrd r10,1 1351 1352 mtspr SPRN_SRR0,r11 1353 mtspr SPRN_SRR1,r12 1354 ld r9,PACA_EXSLB+EX_R9(r13) 1355 ld r10,PACA_EXSLB+EX_R10(r13) 1356 ld r11,PACA_EXSLB+EX_R11(r13) 1357 ld r12,PACA_EXSLB+EX_R12(r13) 1358 ld r13,PACA_EXSLB+EX_R13(r13) 1359 rfid 1360 b . /* prevent speculative execution */ 1361 1362/* 1363 * Space for CPU0's segment table. 1364 * 1365 * On iSeries, the hypervisor must fill in at least one entry before 1366 * we get control (with relocate on). The address is give to the hv 1367 * as a page number (see xLparMap in lpardata.c), so this must be at a 1368 * fixed address (the linker can't compute (u64)&initial_stab >> 1369 * PAGE_SHIFT). 1370 */ 1371 . = STAB0_OFFSET /* 0x6000 */ 1372 .globl initial_stab 1373initial_stab: 1374 .space 4096 1375 1376/* 1377 * Data area reserved for FWNMI option. 1378 * This address (0x7000) is fixed by the RPA. 1379 */ 1380 .= 0x7000 1381 .globl fwnmi_data_area 1382fwnmi_data_area: 1383 1384 /* iSeries does not use the FWNMI stuff, so it is safe to put 1385 * this here, even if we later allow kernels that will boot on 1386 * both pSeries and iSeries */ 1387#ifdef CONFIG_PPC_ISERIES 1388 . = LPARMAP_PHYS 1389#include "lparmap.s" 1390/* 1391 * This ".text" is here for old compilers that generate a trailing 1392 * .note section when compiling .c files to .s 1393 */ 1394 .text 1395#endif /* CONFIG_PPC_ISERIES */ 1396 1397 . = 0x8000 1398 1399/* 1400 * On pSeries, secondary processors spin in the following code. 1401 * At entry, r3 = this processor's number (physical cpu id) 1402 */ 1403_GLOBAL(pSeries_secondary_smp_init) 1404 mr r24,r3 1405 1406 /* turn on 64-bit mode */ 1407 bl .enable_64b_mode 1408 isync 1409 1410 /* Copy some CPU settings from CPU 0 */ 1411 bl .__restore_cpu_setup 1412 1413 /* Set up a paca value for this processor. Since we have the 1414 * physical cpu id in r24, we need to search the pacas to find 1415 * which logical id maps to our physical one. 1416 */ 1417 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ 1418 li r5,0 /* logical cpu id */ 14191: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 1420 cmpw r6,r24 /* Compare to our id */ 1421 beq 2f 1422 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ 1423 addi r5,r5,1 1424 cmpwi r5,NR_CPUS 1425 blt 1b 1426 1427 mr r3,r24 /* not found, copy phys to r3 */ 1428 b .kexec_wait /* next kernel might do better */ 1429 14302: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1431 /* From now on, r24 is expected to be logical cpuid */ 1432 mr r24,r5 14333: HMT_LOW 1434 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 1435 /* start. */ 1436 sync 1437 1438 /* Create a temp kernel stack for use before relocation is on. */ 1439 ld r1,PACAEMERGSP(r13) 1440 subi r1,r1,STACK_FRAME_OVERHEAD 1441 1442 cmpwi 0,r23,0 1443#ifdef CONFIG_SMP 1444 bne .__secondary_start 1445#endif 1446 b 3b /* Loop until told to go */ 1447 1448#ifdef CONFIG_PPC_ISERIES 1449_STATIC(__start_initialization_iSeries) 1450 /* Clear out the BSS */ 1451 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1452 LOAD_REG_IMMEDIATE(r8,__bss_start) 1453 sub r11,r11,r8 /* bss size */ 1454 addi r11,r11,7 /* round up to an even double word */ 1455 rldicl. r11,r11,61,3 /* shift right by 3 */ 1456 beq 4f 1457 addi r8,r8,-8 1458 li r0,0 1459 mtctr r11 /* zero this many doublewords */ 14603: stdu r0,8(r8) 1461 bdnz 3b 14624: 1463 LOAD_REG_IMMEDIATE(r1,init_thread_union) 1464 addi r1,r1,THREAD_SIZE 1465 li r0,0 1466 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1467 1468 LOAD_REG_IMMEDIATE(r3,cpu_specs) 1469 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) 1470 li r5,0 1471 bl .identify_cpu 1472 1473 LOAD_REG_IMMEDIATE(r2,__toc_start) 1474 addi r2,r2,0x4000 1475 addi r2,r2,0x4000 1476 1477 bl .iSeries_early_setup 1478 bl .early_setup 1479 1480 /* relocation is on at this point */ 1481 1482 b .start_here_common 1483#endif /* CONFIG_PPC_ISERIES */ 1484 1485#ifdef CONFIG_PPC_MULTIPLATFORM 1486 1487_STATIC(__mmu_off) 1488 mfmsr r3 1489 andi. r0,r3,MSR_IR|MSR_DR 1490 beqlr 1491 andc r3,r3,r0 1492 mtspr SPRN_SRR0,r4 1493 mtspr SPRN_SRR1,r3 1494 sync 1495 rfid 1496 b . /* prevent speculative execution */ 1497 1498 1499/* 1500 * Here is our main kernel entry point. We support currently 2 kind of entries 1501 * depending on the value of r5. 1502 * 1503 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 1504 * in r3...r7 1505 * 1506 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 1507 * DT block, r4 is a physical pointer to the kernel itself 1508 * 1509 */ 1510_GLOBAL(__start_initialization_multiplatform) 1511#ifdef CONFIG_PPC_MULTIPLATFORM 1512 /* 1513 * Are we booted from a PROM Of-type client-interface ? 1514 */ 1515 cmpldi cr0,r5,0 1516 bne .__boot_from_prom /* yes -> prom */ 1517#endif 1518 1519 /* Save parameters */ 1520 mr r31,r3 1521 mr r30,r4 1522 1523 /* Make sure we are running in 64 bits mode */ 1524 bl .enable_64b_mode 1525 1526 /* Setup some critical 970 SPRs before switching MMU off */ 1527 bl .__970_cpu_preinit 1528 1529 /* cpu # */ 1530 li r24,0 1531 1532 /* Switch off MMU if not already */ 1533 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) 1534 add r4,r4,r30 1535 bl .__mmu_off 1536 b .__after_prom_start 1537 1538#ifdef CONFIG_PPC_MULTIPLATFORM 1539_STATIC(__boot_from_prom) 1540 /* Save parameters */ 1541 mr r31,r3 1542 mr r30,r4 1543 mr r29,r5 1544 mr r28,r6 1545 mr r27,r7 1546 1547 /* 1548 * Align the stack to 16-byte boundary 1549 * Depending on the size and layout of the ELF sections in the initial 1550 * boot binary, the stack pointer will be unalignet on PowerMac 1551 */ 1552 rldicr r1,r1,0,59 1553 1554 /* Make sure we are running in 64 bits mode */ 1555 bl .enable_64b_mode 1556 1557 /* put a relocation offset into r3 */ 1558 bl .reloc_offset 1559 1560 LOAD_REG_IMMEDIATE(r2,__toc_start) 1561 addi r2,r2,0x4000 1562 addi r2,r2,0x4000 1563 1564 /* Relocate the TOC from a virt addr to a real addr */ 1565 add r2,r2,r3 1566 1567 /* Restore parameters */ 1568 mr r3,r31 1569 mr r4,r30 1570 mr r5,r29 1571 mr r6,r28 1572 mr r7,r27 1573 1574 /* Do all of the interaction with OF client interface */ 1575 bl .prom_init 1576 /* We never return */ 1577 trap 1578#endif 1579 1580/* 1581 * At this point, r3 contains the physical address we are running at, 1582 * returned by prom_init() 1583 */ 1584_STATIC(__after_prom_start) 1585 1586/* 1587 * We need to run with __start at physical address PHYSICAL_START. 1588 * This will leave some code in the first 256B of 1589 * real memory, which are reserved for software use. 1590 * The remainder of the first page is loaded with the fixed 1591 * interrupt vectors. The next two pages are filled with 1592 * unknown exception placeholders. 1593 * 1594 * Note: This process overwrites the OF exception vectors. 1595 * r26 == relocation offset 1596 * r27 == KERNELBASE 1597 */ 1598 bl .reloc_offset 1599 mr r26,r3 1600 LOAD_REG_IMMEDIATE(r27, KERNELBASE) 1601 1602 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ 1603 1604 // XXX FIXME: Use phys returned by OF (r30) 1605 add r4,r27,r26 /* source addr */ 1606 /* current address of _start */ 1607 /* i.e. where we are running */ 1608 /* the source addr */ 1609 1610 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ 1611 sub r5,r5,r27 1612 1613 li r6,0x100 /* Start offset, the first 0x100 */ 1614 /* bytes were copied earlier. */ 1615 1616 bl .copy_and_flush /* copy the first n bytes */ 1617 /* this includes the code being */ 1618 /* executed here. */ 1619 1620 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ 1621 mtctr r0 /* that we just made/relocated */ 1622 bctr 1623 16244: LOAD_REG_IMMEDIATE(r5,klimit) 1625 add r5,r5,r26 1626 ld r5,0(r5) /* get the value of klimit */ 1627 sub r5,r5,r27 1628 bl .copy_and_flush /* copy the rest */ 1629 b .start_here_multiplatform 1630 1631#endif /* CONFIG_PPC_MULTIPLATFORM */ 1632 1633/* 1634 * Copy routine used to copy the kernel to start at physical address 0 1635 * and flush and invalidate the caches as needed. 1636 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 1637 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 1638 * 1639 * Note: this routine *only* clobbers r0, r6 and lr 1640 */ 1641_GLOBAL(copy_and_flush) 1642 addi r5,r5,-8 1643 addi r6,r6,-8 16444: li r0,16 /* Use the least common */ 1645 /* denominator cache line */ 1646 /* size. This results in */ 1647 /* extra cache line flushes */ 1648 /* but operation is correct. */ 1649 /* Can't get cache line size */ 1650 /* from NACA as it is being */ 1651 /* moved too. */ 1652 1653 mtctr r0 /* put # words/line in ctr */ 16543: addi r6,r6,8 /* copy a cache line */ 1655 ldx r0,r6,r4 1656 stdx r0,r6,r3 1657 bdnz 3b 1658 dcbst r6,r3 /* write it to memory */ 1659 sync 1660 icbi r6,r3 /* flush the icache line */ 1661 cmpld 0,r6,r5 1662 blt 4b 1663 sync 1664 addi r5,r5,8 1665 addi r6,r6,8 1666 blr 1667 1668.align 8 1669copy_to_here: 1670 1671#ifdef CONFIG_SMP 1672#ifdef CONFIG_PPC_PMAC 1673/* 1674 * On PowerMac, secondary processors starts from the reset vector, which 1675 * is temporarily turned into a call to one of the functions below. 1676 */ 1677 .section ".text"; 1678 .align 2 ; 1679 1680 .globl __secondary_start_pmac_0 1681__secondary_start_pmac_0: 1682 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 1683 li r24,0 1684 b 1f 1685 li r24,1 1686 b 1f 1687 li r24,2 1688 b 1f 1689 li r24,3 16901: 1691 1692_GLOBAL(pmac_secondary_start) 1693 /* turn on 64-bit mode */ 1694 bl .enable_64b_mode 1695 isync 1696 1697 /* Copy some CPU settings from CPU 0 */ 1698 bl .__restore_cpu_setup 1699 1700 /* pSeries do that early though I don't think we really need it */ 1701 mfmsr r3 1702 ori r3,r3,MSR_RI 1703 mtmsrd r3 /* RI on */ 1704 1705 /* Set up a paca value for this processor. */ 1706 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 1707 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ 1708 add r13,r13,r4 /* for this processor. */ 1709 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ 1710 1711 /* Create a temp kernel stack for use before relocation is on. */ 1712 ld r1,PACAEMERGSP(r13) 1713 subi r1,r1,STACK_FRAME_OVERHEAD 1714 1715 b .__secondary_start 1716 1717#endif /* CONFIG_PPC_PMAC */ 1718 1719/* 1720 * This function is called after the master CPU has released the 1721 * secondary processors. The execution environment is relocation off. 1722 * The paca for this processor has the following fields initialized at 1723 * this point: 1724 * 1. Processor number 1725 * 2. Segment table pointer (virtual address) 1726 * On entry the following are set: 1727 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries 1728 * r24 = cpu# (in Linux terms) 1729 * r13 = paca virtual address 1730 * SPRG3 = paca virtual address 1731 */ 1732_GLOBAL(__secondary_start) 1733 /* Set thread priority to MEDIUM */ 1734 HMT_MEDIUM 1735 1736 /* Load TOC */ 1737 ld r2,PACATOC(r13) 1738 1739 /* Do early setup for that CPU (stab, slb, hash table pointer) */ 1740 bl .early_setup_secondary 1741 1742 /* Initialize the kernel stack. Just a repeat for iSeries. */ 1743 LOAD_REG_ADDR(r3, current_set) 1744 sldi r28,r24,3 /* get current_set[cpu#] */ 1745 ldx r1,r3,r28 1746 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1747 std r1,PACAKSAVE(r13) 1748 1749 /* Clear backchain so we get nice backtraces */ 1750 li r7,0 1751 mtlr r7 1752 1753 /* enable MMU and jump to start_secondary */ 1754 LOAD_REG_ADDR(r3, .start_secondary_prolog) 1755 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1756#ifdef DO_SOFT_DISABLE 1757 ori r4,r4,MSR_EE 1758#endif 1759 mtspr SPRN_SRR0,r3 1760 mtspr SPRN_SRR1,r4 1761 rfid 1762 b . /* prevent speculative execution */ 1763 1764/* 1765 * Running with relocation on at this point. All we want to do is 1766 * zero the stack back-chain pointer before going into C code. 1767 */ 1768_GLOBAL(start_secondary_prolog) 1769 li r3,0 1770 std r3,0(r1) /* Zero the stack frame pointer */ 1771 bl .start_secondary 1772 b . 1773#endif 1774 1775/* 1776 * This subroutine clobbers r11 and r12 1777 */ 1778_GLOBAL(enable_64b_mode) 1779 mfmsr r11 /* grab the current MSR */ 1780 li r12,1 1781 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) 1782 or r11,r11,r12 1783 li r12,1 1784 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) 1785 or r11,r11,r12 1786 mtmsrd r11 1787 isync 1788 blr 1789 1790#ifdef CONFIG_PPC_MULTIPLATFORM 1791/* 1792 * This is where the main kernel code starts. 1793 */ 1794_STATIC(start_here_multiplatform) 1795 /* get a new offset, now that the kernel has moved. */ 1796 bl .reloc_offset 1797 mr r26,r3 1798 1799 /* Clear out the BSS. It may have been done in prom_init, 1800 * already but that's irrelevant since prom_init will soon 1801 * be detached from the kernel completely. Besides, we need 1802 * to clear it now for kexec-style entry. 1803 */ 1804 LOAD_REG_IMMEDIATE(r11,__bss_stop) 1805 LOAD_REG_IMMEDIATE(r8,__bss_start) 1806 sub r11,r11,r8 /* bss size */ 1807 addi r11,r11,7 /* round up to an even double word */ 1808 rldicl. r11,r11,61,3 /* shift right by 3 */ 1809 beq 4f 1810 addi r8,r8,-8 1811 li r0,0 1812 mtctr r11 /* zero this many doublewords */ 18133: stdu r0,8(r8) 1814 bdnz 3b 18154: 1816 1817 mfmsr r6 1818 ori r6,r6,MSR_RI 1819 mtmsrd r6 /* RI on */ 1820 1821 /* The following gets the stack and TOC set up with the regs */ 1822 /* pointing to the real addr of the kernel stack. This is */ 1823 /* all done to support the C function call below which sets */ 1824 /* up the htab. This is done because we have relocated the */ 1825 /* kernel but are still running in real mode. */ 1826 1827 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1828 add r3,r3,r26 1829 1830 /* set up a stack pointer (physical address) */ 1831 addi r1,r3,THREAD_SIZE 1832 li r0,0 1833 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1834 1835 /* set up the TOC (physical address) */ 1836 LOAD_REG_IMMEDIATE(r2,__toc_start) 1837 addi r2,r2,0x4000 1838 addi r2,r2,0x4000 1839 add r2,r2,r26 1840 1841 LOAD_REG_IMMEDIATE(r3, cpu_specs) 1842 add r3,r3,r26 1843 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) 1844 add r4,r4,r26 1845 mr r5,r26 1846 bl .identify_cpu 1847 1848 /* Save some low level config HIDs of CPU0 to be copied to 1849 * other CPUs later on, or used for suspend/resume 1850 */ 1851 bl .__save_cpu_setup 1852 sync 1853 1854 /* Do very early kernel initializations, including initial hash table, 1855 * stab and slb setup before we turn on relocation. */ 1856 1857 /* Restore parameters passed from prom_init/kexec */ 1858 mr r3,r31 1859 bl .early_setup 1860 1861 LOAD_REG_IMMEDIATE(r3, .start_here_common) 1862 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 1863 mtspr SPRN_SRR0,r3 1864 mtspr SPRN_SRR1,r4 1865 rfid 1866 b . /* prevent speculative execution */ 1867#endif /* CONFIG_PPC_MULTIPLATFORM */ 1868 1869 /* This is where all platforms converge execution */ 1870_STATIC(start_here_common) 1871 /* relocation is on at this point */ 1872 1873 /* The following code sets up the SP and TOC now that we are */ 1874 /* running with translation enabled. */ 1875 1876 LOAD_REG_IMMEDIATE(r3,init_thread_union) 1877 1878 /* set up the stack */ 1879 addi r1,r3,THREAD_SIZE 1880 li r0,0 1881 stdu r0,-STACK_FRAME_OVERHEAD(r1) 1882 1883 /* Apply the CPUs-specific fixups (nop out sections not relevant 1884 * to this CPU 1885 */ 1886 li r3,0 1887 bl .do_cpu_ftr_fixups 1888 1889 LOAD_REG_IMMEDIATE(r26, boot_cpuid) 1890 lwz r26,0(r26) 1891 1892 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */ 1893 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ 1894 add r13,r13,r24 /* for this processor. */ 1895 mtspr SPRN_SPRG3,r13 1896 1897 /* ptr to current */ 1898 LOAD_REG_IMMEDIATE(r4, init_task) 1899 std r4,PACACURRENT(r13) 1900 1901 /* Load the TOC */ 1902 ld r2,PACATOC(r13) 1903 std r1,PACAKSAVE(r13) 1904 1905 bl .setup_system 1906 1907 /* Load up the kernel context */ 19085: 1909#ifdef DO_SOFT_DISABLE 1910 li r5,0 1911 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ 1912 mfmsr r5 1913 ori r5,r5,MSR_EE /* Hard Enabled */ 1914 mtmsrd r5 1915#endif 1916 1917 bl .start_kernel 1918 1919 /* Not reached */ 1920 BUG_OPCODE 1921 1922/* Put the paca pointer into r13 and SPRG3 */ 1923_GLOBAL(setup_boot_paca) 1924 LOAD_REG_IMMEDIATE(r3, boot_cpuid) 1925 lwz r3,0(r3) 1926 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ 1927 mulli r3,r3,PACA_SIZE /* Calculate vaddr of right paca */ 1928 add r13,r3,r4 /* for this processor. */ 1929 mtspr SPRN_SPRG3,r13 1930 1931 blr 1932 1933/* 1934 * We put a few things here that have to be page-aligned. 1935 * This stuff goes at the beginning of the bss, which is page-aligned. 1936 */ 1937 .section ".bss" 1938 1939 .align PAGE_SHIFT 1940 1941 .globl empty_zero_page 1942empty_zero_page: 1943 .space PAGE_SIZE 1944 1945 .globl swapper_pg_dir 1946swapper_pg_dir: 1947 .space PAGE_SIZE 1948 1949/* 1950 * This space gets a copy of optional info passed to us by the bootstrap 1951 * Used to pass parameters into the kernel like root=/dev/sda1, etc. 1952 */ 1953 .globl cmd_line 1954cmd_line: 1955 .space COMMAND_LINE_SIZE 1956