1 /* 2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 3 * 4 * Modifications for ppc64: 5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/config.h> 14 #include <linux/string.h> 15 #include <linux/sched.h> 16 #include <linux/threads.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 20 #include <asm/oprofile_impl.h> 21 #include <asm/cputable.h> 22 23 struct cpu_spec* cur_cpu_spec = NULL; 24 EXPORT_SYMBOL(cur_cpu_spec); 25 26 /* NOTE: 27 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's 28 * the responsibility of the appropriate CPU save/restore functions to 29 * eventually copy these settings over. Those save/restore aren't yet 30 * part of the cputable though. That has to be fixed for both ppc32 31 * and ppc64 32 */ 33 #ifdef CONFIG_PPC64 34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec); 35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec); 36 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); 37 #else 38 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); 39 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); 40 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); 41 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec); 42 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec); 43 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec); 44 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec); 45 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); 46 #endif /* CONFIG_PPC32 */ 47 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 48 49 /* This table only contains "desktop" CPUs, it need to be filled with embedded 50 * ones as well... 51 */ 52 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 53 PPC_FEATURE_HAS_MMU) 54 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64) 55 56 57 /* We only set the spe features if the kernel was compiled with 58 * spe support 59 */ 60 #ifdef CONFIG_SPE 61 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE 62 #else 63 #define PPC_FEATURE_SPE_COMP 0 64 #endif 65 66 struct cpu_spec cpu_specs[] = { 67 #ifdef CONFIG_PPC64 68 { /* Power3 */ 69 .pvr_mask = 0xffff0000, 70 .pvr_value = 0x00400000, 71 .cpu_name = "POWER3 (630)", 72 .cpu_features = CPU_FTRS_POWER3, 73 .cpu_user_features = COMMON_USER_PPC64, 74 .icache_bsize = 128, 75 .dcache_bsize = 128, 76 .num_pmcs = 8, 77 .cpu_setup = __setup_cpu_power3, 78 #ifdef CONFIG_OPROFILE 79 .oprofile_cpu_type = "ppc64/power3", 80 .oprofile_model = &op_model_rs64, 81 #endif 82 }, 83 { /* Power3+ */ 84 .pvr_mask = 0xffff0000, 85 .pvr_value = 0x00410000, 86 .cpu_name = "POWER3 (630+)", 87 .cpu_features = CPU_FTRS_POWER3, 88 .cpu_user_features = COMMON_USER_PPC64, 89 .icache_bsize = 128, 90 .dcache_bsize = 128, 91 .num_pmcs = 8, 92 .cpu_setup = __setup_cpu_power3, 93 #ifdef CONFIG_OPROFILE 94 .oprofile_cpu_type = "ppc64/power3", 95 .oprofile_model = &op_model_rs64, 96 #endif 97 }, 98 { /* Northstar */ 99 .pvr_mask = 0xffff0000, 100 .pvr_value = 0x00330000, 101 .cpu_name = "RS64-II (northstar)", 102 .cpu_features = CPU_FTRS_RS64, 103 .cpu_user_features = COMMON_USER_PPC64, 104 .icache_bsize = 128, 105 .dcache_bsize = 128, 106 .num_pmcs = 8, 107 .cpu_setup = __setup_cpu_power3, 108 #ifdef CONFIG_OPROFILE 109 .oprofile_cpu_type = "ppc64/rs64", 110 .oprofile_model = &op_model_rs64, 111 #endif 112 }, 113 { /* Pulsar */ 114 .pvr_mask = 0xffff0000, 115 .pvr_value = 0x00340000, 116 .cpu_name = "RS64-III (pulsar)", 117 .cpu_features = CPU_FTRS_RS64, 118 .cpu_user_features = COMMON_USER_PPC64, 119 .icache_bsize = 128, 120 .dcache_bsize = 128, 121 .num_pmcs = 8, 122 .cpu_setup = __setup_cpu_power3, 123 #ifdef CONFIG_OPROFILE 124 .oprofile_cpu_type = "ppc64/rs64", 125 .oprofile_model = &op_model_rs64, 126 #endif 127 }, 128 { /* I-star */ 129 .pvr_mask = 0xffff0000, 130 .pvr_value = 0x00360000, 131 .cpu_name = "RS64-III (icestar)", 132 .cpu_features = CPU_FTRS_RS64, 133 .cpu_user_features = COMMON_USER_PPC64, 134 .icache_bsize = 128, 135 .dcache_bsize = 128, 136 .num_pmcs = 8, 137 .cpu_setup = __setup_cpu_power3, 138 #ifdef CONFIG_OPROFILE 139 .oprofile_cpu_type = "ppc64/rs64", 140 .oprofile_model = &op_model_rs64, 141 #endif 142 }, 143 { /* S-star */ 144 .pvr_mask = 0xffff0000, 145 .pvr_value = 0x00370000, 146 .cpu_name = "RS64-IV (sstar)", 147 .cpu_features = CPU_FTRS_RS64, 148 .cpu_user_features = COMMON_USER_PPC64, 149 .icache_bsize = 128, 150 .dcache_bsize = 128, 151 .num_pmcs = 8, 152 .cpu_setup = __setup_cpu_power3, 153 #ifdef CONFIG_OPROFILE 154 .oprofile_cpu_type = "ppc64/rs64", 155 .oprofile_model = &op_model_rs64, 156 #endif 157 }, 158 { /* Power4 */ 159 .pvr_mask = 0xffff0000, 160 .pvr_value = 0x00350000, 161 .cpu_name = "POWER4 (gp)", 162 .cpu_features = CPU_FTRS_POWER4, 163 .cpu_user_features = COMMON_USER_PPC64, 164 .icache_bsize = 128, 165 .dcache_bsize = 128, 166 .num_pmcs = 8, 167 .cpu_setup = __setup_cpu_power4, 168 #ifdef CONFIG_OPROFILE 169 .oprofile_cpu_type = "ppc64/power4", 170 .oprofile_model = &op_model_rs64, 171 #endif 172 }, 173 { /* Power4+ */ 174 .pvr_mask = 0xffff0000, 175 .pvr_value = 0x00380000, 176 .cpu_name = "POWER4+ (gq)", 177 .cpu_features = CPU_FTRS_POWER4, 178 .cpu_user_features = COMMON_USER_PPC64, 179 .icache_bsize = 128, 180 .dcache_bsize = 128, 181 .num_pmcs = 8, 182 .cpu_setup = __setup_cpu_power4, 183 #ifdef CONFIG_OPROFILE 184 .oprofile_cpu_type = "ppc64/power4", 185 .oprofile_model = &op_model_power4, 186 #endif 187 }, 188 { /* PPC970 */ 189 .pvr_mask = 0xffff0000, 190 .pvr_value = 0x00390000, 191 .cpu_name = "PPC970", 192 .cpu_features = CPU_FTRS_PPC970, 193 .cpu_user_features = COMMON_USER_PPC64 | 194 PPC_FEATURE_HAS_ALTIVEC_COMP, 195 .icache_bsize = 128, 196 .dcache_bsize = 128, 197 .num_pmcs = 8, 198 .cpu_setup = __setup_cpu_ppc970, 199 #ifdef CONFIG_OPROFILE 200 .oprofile_cpu_type = "ppc64/970", 201 .oprofile_model = &op_model_power4, 202 #endif 203 }, 204 #endif /* CONFIG_PPC64 */ 205 #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4) 206 { /* PPC970FX */ 207 .pvr_mask = 0xffff0000, 208 .pvr_value = 0x003c0000, 209 .cpu_name = "PPC970FX", 210 #ifdef CONFIG_PPC32 211 .cpu_features = CPU_FTRS_970_32, 212 #else 213 .cpu_features = CPU_FTRS_PPC970, 214 #endif 215 .cpu_user_features = COMMON_USER_PPC64 | 216 PPC_FEATURE_HAS_ALTIVEC_COMP, 217 .icache_bsize = 128, 218 .dcache_bsize = 128, 219 .num_pmcs = 8, 220 .cpu_setup = __setup_cpu_ppc970, 221 #ifdef CONFIG_OPROFILE 222 .oprofile_cpu_type = "ppc64/970", 223 .oprofile_model = &op_model_power4, 224 #endif 225 }, 226 #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */ 227 #ifdef CONFIG_PPC64 228 { /* PPC970MP */ 229 .pvr_mask = 0xffff0000, 230 .pvr_value = 0x00440000, 231 .cpu_name = "PPC970MP", 232 .cpu_features = CPU_FTRS_PPC970, 233 .cpu_user_features = COMMON_USER_PPC64 | 234 PPC_FEATURE_HAS_ALTIVEC_COMP, 235 .icache_bsize = 128, 236 .dcache_bsize = 128, 237 .cpu_setup = __setup_cpu_ppc970, 238 #ifdef CONFIG_OPROFILE 239 .oprofile_cpu_type = "ppc64/970", 240 .oprofile_model = &op_model_power4, 241 #endif 242 }, 243 { /* Power5 GR */ 244 .pvr_mask = 0xffff0000, 245 .pvr_value = 0x003a0000, 246 .cpu_name = "POWER5 (gr)", 247 .cpu_features = CPU_FTRS_POWER5, 248 .cpu_user_features = COMMON_USER_PPC64, 249 .icache_bsize = 128, 250 .dcache_bsize = 128, 251 .num_pmcs = 6, 252 .cpu_setup = __setup_cpu_power4, 253 #ifdef CONFIG_OPROFILE 254 .oprofile_cpu_type = "ppc64/power5", 255 .oprofile_model = &op_model_power4, 256 #endif 257 }, 258 { /* Power5 GS */ 259 .pvr_mask = 0xffff0000, 260 .pvr_value = 0x003b0000, 261 .cpu_name = "POWER5 (gs)", 262 .cpu_features = CPU_FTRS_POWER5, 263 .cpu_user_features = COMMON_USER_PPC64, 264 .icache_bsize = 128, 265 .dcache_bsize = 128, 266 .num_pmcs = 6, 267 .cpu_setup = __setup_cpu_power4, 268 #ifdef CONFIG_OPROFILE 269 .oprofile_cpu_type = "ppc64/power5", 270 .oprofile_model = &op_model_power4, 271 #endif 272 }, 273 { /* BE DD1.x */ 274 .pvr_mask = 0xffff0000, 275 .pvr_value = 0x00700000, 276 .cpu_name = "Cell Broadband Engine", 277 .cpu_features = CPU_FTRS_CELL, 278 .cpu_user_features = COMMON_USER_PPC64 | 279 PPC_FEATURE_HAS_ALTIVEC_COMP, 280 .icache_bsize = 128, 281 .dcache_bsize = 128, 282 .cpu_setup = __setup_cpu_be, 283 }, 284 { /* default match */ 285 .pvr_mask = 0x00000000, 286 .pvr_value = 0x00000000, 287 .cpu_name = "POWER4 (compatible)", 288 .cpu_features = CPU_FTRS_COMPATIBLE, 289 .cpu_user_features = COMMON_USER_PPC64, 290 .icache_bsize = 128, 291 .dcache_bsize = 128, 292 .num_pmcs = 6, 293 .cpu_setup = __setup_cpu_power4, 294 } 295 #endif /* CONFIG_PPC64 */ 296 #ifdef CONFIG_PPC32 297 #if CLASSIC_PPC 298 { /* 601 */ 299 .pvr_mask = 0xffff0000, 300 .pvr_value = 0x00010000, 301 .cpu_name = "601", 302 .cpu_features = CPU_FTRS_PPC601, 303 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR | 304 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, 305 .icache_bsize = 32, 306 .dcache_bsize = 32, 307 }, 308 { /* 603 */ 309 .pvr_mask = 0xffff0000, 310 .pvr_value = 0x00030000, 311 .cpu_name = "603", 312 .cpu_features = CPU_FTRS_603, 313 .cpu_user_features = COMMON_USER, 314 .icache_bsize = 32, 315 .dcache_bsize = 32, 316 .cpu_setup = __setup_cpu_603 317 }, 318 { /* 603e */ 319 .pvr_mask = 0xffff0000, 320 .pvr_value = 0x00060000, 321 .cpu_name = "603e", 322 .cpu_features = CPU_FTRS_603, 323 .cpu_user_features = COMMON_USER, 324 .icache_bsize = 32, 325 .dcache_bsize = 32, 326 .cpu_setup = __setup_cpu_603 327 }, 328 { /* 603ev */ 329 .pvr_mask = 0xffff0000, 330 .pvr_value = 0x00070000, 331 .cpu_name = "603ev", 332 .cpu_features = CPU_FTRS_603, 333 .cpu_user_features = COMMON_USER, 334 .icache_bsize = 32, 335 .dcache_bsize = 32, 336 .cpu_setup = __setup_cpu_603 337 }, 338 { /* 604 */ 339 .pvr_mask = 0xffff0000, 340 .pvr_value = 0x00040000, 341 .cpu_name = "604", 342 .cpu_features = CPU_FTRS_604, 343 .cpu_user_features = COMMON_USER, 344 .icache_bsize = 32, 345 .dcache_bsize = 32, 346 .num_pmcs = 2, 347 .cpu_setup = __setup_cpu_604 348 }, 349 { /* 604e */ 350 .pvr_mask = 0xfffff000, 351 .pvr_value = 0x00090000, 352 .cpu_name = "604e", 353 .cpu_features = CPU_FTRS_604, 354 .cpu_user_features = COMMON_USER, 355 .icache_bsize = 32, 356 .dcache_bsize = 32, 357 .num_pmcs = 4, 358 .cpu_setup = __setup_cpu_604 359 }, 360 { /* 604r */ 361 .pvr_mask = 0xffff0000, 362 .pvr_value = 0x00090000, 363 .cpu_name = "604r", 364 .cpu_features = CPU_FTRS_604, 365 .cpu_user_features = COMMON_USER, 366 .icache_bsize = 32, 367 .dcache_bsize = 32, 368 .num_pmcs = 4, 369 .cpu_setup = __setup_cpu_604 370 }, 371 { /* 604ev */ 372 .pvr_mask = 0xffff0000, 373 .pvr_value = 0x000a0000, 374 .cpu_name = "604ev", 375 .cpu_features = CPU_FTRS_604, 376 .cpu_user_features = COMMON_USER, 377 .icache_bsize = 32, 378 .dcache_bsize = 32, 379 .num_pmcs = 4, 380 .cpu_setup = __setup_cpu_604 381 }, 382 { /* 740/750 (0x4202, don't support TAU ?) */ 383 .pvr_mask = 0xffffffff, 384 .pvr_value = 0x00084202, 385 .cpu_name = "740/750", 386 .cpu_features = CPU_FTRS_740_NOTAU, 387 .cpu_user_features = COMMON_USER, 388 .icache_bsize = 32, 389 .dcache_bsize = 32, 390 .num_pmcs = 4, 391 .cpu_setup = __setup_cpu_750 392 }, 393 { /* 750CX (80100 and 8010x?) */ 394 .pvr_mask = 0xfffffff0, 395 .pvr_value = 0x00080100, 396 .cpu_name = "750CX", 397 .cpu_features = CPU_FTRS_750, 398 .cpu_user_features = COMMON_USER, 399 .icache_bsize = 32, 400 .dcache_bsize = 32, 401 .num_pmcs = 4, 402 .cpu_setup = __setup_cpu_750cx 403 }, 404 { /* 750CX (82201 and 82202) */ 405 .pvr_mask = 0xfffffff0, 406 .pvr_value = 0x00082200, 407 .cpu_name = "750CX", 408 .cpu_features = CPU_FTRS_750, 409 .cpu_user_features = COMMON_USER, 410 .icache_bsize = 32, 411 .dcache_bsize = 32, 412 .num_pmcs = 4, 413 .cpu_setup = __setup_cpu_750cx 414 }, 415 { /* 750CXe (82214) */ 416 .pvr_mask = 0xfffffff0, 417 .pvr_value = 0x00082210, 418 .cpu_name = "750CXe", 419 .cpu_features = CPU_FTRS_750, 420 .cpu_user_features = COMMON_USER, 421 .icache_bsize = 32, 422 .dcache_bsize = 32, 423 .num_pmcs = 4, 424 .cpu_setup = __setup_cpu_750cx 425 }, 426 { /* 750CXe "Gekko" (83214) */ 427 .pvr_mask = 0xffffffff, 428 .pvr_value = 0x00083214, 429 .cpu_name = "750CXe", 430 .cpu_features = CPU_FTRS_750, 431 .cpu_user_features = COMMON_USER, 432 .icache_bsize = 32, 433 .dcache_bsize = 32, 434 .num_pmcs = 4, 435 .cpu_setup = __setup_cpu_750cx 436 }, 437 { /* 745/755 */ 438 .pvr_mask = 0xfffff000, 439 .pvr_value = 0x00083000, 440 .cpu_name = "745/755", 441 .cpu_features = CPU_FTRS_750, 442 .cpu_user_features = COMMON_USER, 443 .icache_bsize = 32, 444 .dcache_bsize = 32, 445 .num_pmcs = 4, 446 .cpu_setup = __setup_cpu_750 447 }, 448 { /* 750FX rev 1.x */ 449 .pvr_mask = 0xffffff00, 450 .pvr_value = 0x70000100, 451 .cpu_name = "750FX", 452 .cpu_features = CPU_FTRS_750FX1, 453 .cpu_user_features = COMMON_USER, 454 .icache_bsize = 32, 455 .dcache_bsize = 32, 456 .num_pmcs = 4, 457 .cpu_setup = __setup_cpu_750 458 }, 459 { /* 750FX rev 2.0 must disable HID0[DPM] */ 460 .pvr_mask = 0xffffffff, 461 .pvr_value = 0x70000200, 462 .cpu_name = "750FX", 463 .cpu_features = CPU_FTRS_750FX2, 464 .cpu_user_features = COMMON_USER, 465 .icache_bsize = 32, 466 .dcache_bsize = 32, 467 .num_pmcs = 4, 468 .cpu_setup = __setup_cpu_750 469 }, 470 { /* 750FX (All revs except 2.0) */ 471 .pvr_mask = 0xffff0000, 472 .pvr_value = 0x70000000, 473 .cpu_name = "750FX", 474 .cpu_features = CPU_FTRS_750FX, 475 .cpu_user_features = COMMON_USER, 476 .icache_bsize = 32, 477 .dcache_bsize = 32, 478 .num_pmcs = 4, 479 .cpu_setup = __setup_cpu_750fx 480 }, 481 { /* 750GX */ 482 .pvr_mask = 0xffff0000, 483 .pvr_value = 0x70020000, 484 .cpu_name = "750GX", 485 .cpu_features = CPU_FTRS_750GX, 486 .cpu_user_features = COMMON_USER, 487 .icache_bsize = 32, 488 .dcache_bsize = 32, 489 .num_pmcs = 4, 490 .cpu_setup = __setup_cpu_750fx 491 }, 492 { /* 740/750 (L2CR bit need fixup for 740) */ 493 .pvr_mask = 0xffff0000, 494 .pvr_value = 0x00080000, 495 .cpu_name = "740/750", 496 .cpu_features = CPU_FTRS_740, 497 .cpu_user_features = COMMON_USER, 498 .icache_bsize = 32, 499 .dcache_bsize = 32, 500 .num_pmcs = 4, 501 .cpu_setup = __setup_cpu_750 502 }, 503 { /* 7400 rev 1.1 ? (no TAU) */ 504 .pvr_mask = 0xffffffff, 505 .pvr_value = 0x000c1101, 506 .cpu_name = "7400 (1.1)", 507 .cpu_features = CPU_FTRS_7400_NOTAU, 508 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 509 .icache_bsize = 32, 510 .dcache_bsize = 32, 511 .num_pmcs = 4, 512 .cpu_setup = __setup_cpu_7400 513 }, 514 { /* 7400 */ 515 .pvr_mask = 0xffff0000, 516 .pvr_value = 0x000c0000, 517 .cpu_name = "7400", 518 .cpu_features = CPU_FTRS_7400, 519 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 520 .icache_bsize = 32, 521 .dcache_bsize = 32, 522 .num_pmcs = 4, 523 .cpu_setup = __setup_cpu_7400 524 }, 525 { /* 7410 */ 526 .pvr_mask = 0xffff0000, 527 .pvr_value = 0x800c0000, 528 .cpu_name = "7410", 529 .cpu_features = CPU_FTRS_7400, 530 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 531 .icache_bsize = 32, 532 .dcache_bsize = 32, 533 .num_pmcs = 4, 534 .cpu_setup = __setup_cpu_7410 535 }, 536 { /* 7450 2.0 - no doze/nap */ 537 .pvr_mask = 0xffffffff, 538 .pvr_value = 0x80000200, 539 .cpu_name = "7450", 540 .cpu_features = CPU_FTRS_7450_20, 541 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 542 .icache_bsize = 32, 543 .dcache_bsize = 32, 544 .num_pmcs = 6, 545 .cpu_setup = __setup_cpu_745x 546 }, 547 { /* 7450 2.1 */ 548 .pvr_mask = 0xffffffff, 549 .pvr_value = 0x80000201, 550 .cpu_name = "7450", 551 .cpu_features = CPU_FTRS_7450_21, 552 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 553 .icache_bsize = 32, 554 .dcache_bsize = 32, 555 .num_pmcs = 6, 556 .cpu_setup = __setup_cpu_745x 557 }, 558 { /* 7450 2.3 and newer */ 559 .pvr_mask = 0xffff0000, 560 .pvr_value = 0x80000000, 561 .cpu_name = "7450", 562 .cpu_features = CPU_FTRS_7450_23, 563 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 564 .icache_bsize = 32, 565 .dcache_bsize = 32, 566 .num_pmcs = 6, 567 .cpu_setup = __setup_cpu_745x 568 }, 569 { /* 7455 rev 1.x */ 570 .pvr_mask = 0xffffff00, 571 .pvr_value = 0x80010100, 572 .cpu_name = "7455", 573 .cpu_features = CPU_FTRS_7455_1, 574 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 575 .icache_bsize = 32, 576 .dcache_bsize = 32, 577 .num_pmcs = 6, 578 .cpu_setup = __setup_cpu_745x 579 }, 580 { /* 7455 rev 2.0 */ 581 .pvr_mask = 0xffffffff, 582 .pvr_value = 0x80010200, 583 .cpu_name = "7455", 584 .cpu_features = CPU_FTRS_7455_20, 585 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 586 .icache_bsize = 32, 587 .dcache_bsize = 32, 588 .num_pmcs = 6, 589 .cpu_setup = __setup_cpu_745x 590 }, 591 { /* 7455 others */ 592 .pvr_mask = 0xffff0000, 593 .pvr_value = 0x80010000, 594 .cpu_name = "7455", 595 .cpu_features = CPU_FTRS_7455, 596 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 597 .icache_bsize = 32, 598 .dcache_bsize = 32, 599 .num_pmcs = 6, 600 .cpu_setup = __setup_cpu_745x 601 }, 602 { /* 7447/7457 Rev 1.0 */ 603 .pvr_mask = 0xffffffff, 604 .pvr_value = 0x80020100, 605 .cpu_name = "7447/7457", 606 .cpu_features = CPU_FTRS_7447_10, 607 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 608 .icache_bsize = 32, 609 .dcache_bsize = 32, 610 .num_pmcs = 6, 611 .cpu_setup = __setup_cpu_745x 612 }, 613 { /* 7447/7457 Rev 1.1 */ 614 .pvr_mask = 0xffffffff, 615 .pvr_value = 0x80020101, 616 .cpu_name = "7447/7457", 617 .cpu_features = CPU_FTRS_7447_10, 618 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 619 .icache_bsize = 32, 620 .dcache_bsize = 32, 621 .num_pmcs = 6, 622 .cpu_setup = __setup_cpu_745x 623 }, 624 { /* 7447/7457 Rev 1.2 and later */ 625 .pvr_mask = 0xffff0000, 626 .pvr_value = 0x80020000, 627 .cpu_name = "7447/7457", 628 .cpu_features = CPU_FTRS_7447, 629 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 630 .icache_bsize = 32, 631 .dcache_bsize = 32, 632 .num_pmcs = 6, 633 .cpu_setup = __setup_cpu_745x 634 }, 635 { /* 7447A */ 636 .pvr_mask = 0xffff0000, 637 .pvr_value = 0x80030000, 638 .cpu_name = "7447A", 639 .cpu_features = CPU_FTRS_7447A, 640 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 641 .icache_bsize = 32, 642 .dcache_bsize = 32, 643 .num_pmcs = 6, 644 .cpu_setup = __setup_cpu_745x 645 }, 646 { /* 7448 */ 647 .pvr_mask = 0xffff0000, 648 .pvr_value = 0x80040000, 649 .cpu_name = "7448", 650 .cpu_features = CPU_FTRS_7447A, 651 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP, 652 .icache_bsize = 32, 653 .dcache_bsize = 32, 654 .num_pmcs = 6, 655 .cpu_setup = __setup_cpu_745x 656 }, 657 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 658 .pvr_mask = 0x7fff0000, 659 .pvr_value = 0x00810000, 660 .cpu_name = "82xx", 661 .cpu_features = CPU_FTRS_82XX, 662 .cpu_user_features = COMMON_USER, 663 .icache_bsize = 32, 664 .dcache_bsize = 32, 665 .cpu_setup = __setup_cpu_603 666 }, 667 { /* All G2_LE (603e core, plus some) have the same pvr */ 668 .pvr_mask = 0x7fff0000, 669 .pvr_value = 0x00820000, 670 .cpu_name = "G2_LE", 671 .cpu_features = CPU_FTRS_G2_LE, 672 .cpu_user_features = COMMON_USER, 673 .icache_bsize = 32, 674 .dcache_bsize = 32, 675 .cpu_setup = __setup_cpu_603 676 }, 677 { /* e300 (a 603e core, plus some) on 83xx */ 678 .pvr_mask = 0x7fff0000, 679 .pvr_value = 0x00830000, 680 .cpu_name = "e300", 681 .cpu_features = CPU_FTRS_E300, 682 .cpu_user_features = COMMON_USER, 683 .icache_bsize = 32, 684 .dcache_bsize = 32, 685 .cpu_setup = __setup_cpu_603 686 }, 687 { /* default match, we assume split I/D cache & TB (non-601)... */ 688 .pvr_mask = 0x00000000, 689 .pvr_value = 0x00000000, 690 .cpu_name = "(generic PPC)", 691 .cpu_features = CPU_FTRS_CLASSIC32, 692 .cpu_user_features = COMMON_USER, 693 .icache_bsize = 32, 694 .dcache_bsize = 32, 695 }, 696 #endif /* CLASSIC_PPC */ 697 #ifdef CONFIG_8xx 698 { /* 8xx */ 699 .pvr_mask = 0xffff0000, 700 .pvr_value = 0x00500000, 701 .cpu_name = "8xx", 702 /* CPU_FTR_MAYBE_CAN_DOZE is possible, 703 * if the 8xx code is there.... */ 704 .cpu_features = CPU_FTRS_8XX, 705 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 706 .icache_bsize = 16, 707 .dcache_bsize = 16, 708 }, 709 #endif /* CONFIG_8xx */ 710 #ifdef CONFIG_40x 711 { /* 403GC */ 712 .pvr_mask = 0xffffff00, 713 .pvr_value = 0x00200200, 714 .cpu_name = "403GC", 715 .cpu_features = CPU_FTRS_40X, 716 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 717 .icache_bsize = 16, 718 .dcache_bsize = 16, 719 }, 720 { /* 403GCX */ 721 .pvr_mask = 0xffffff00, 722 .pvr_value = 0x00201400, 723 .cpu_name = "403GCX", 724 .cpu_features = CPU_FTRS_40X, 725 .cpu_user_features = PPC_FEATURE_32 | 726 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, 727 .icache_bsize = 16, 728 .dcache_bsize = 16, 729 }, 730 { /* 403G ?? */ 731 .pvr_mask = 0xffff0000, 732 .pvr_value = 0x00200000, 733 .cpu_name = "403G ??", 734 .cpu_features = CPU_FTRS_40X, 735 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 736 .icache_bsize = 16, 737 .dcache_bsize = 16, 738 }, 739 { /* 405GP */ 740 .pvr_mask = 0xffff0000, 741 .pvr_value = 0x40110000, 742 .cpu_name = "405GP", 743 .cpu_features = CPU_FTRS_40X, 744 .cpu_user_features = PPC_FEATURE_32 | 745 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 746 .icache_bsize = 32, 747 .dcache_bsize = 32, 748 }, 749 { /* STB 03xxx */ 750 .pvr_mask = 0xffff0000, 751 .pvr_value = 0x40130000, 752 .cpu_name = "STB03xxx", 753 .cpu_features = CPU_FTRS_40X, 754 .cpu_user_features = PPC_FEATURE_32 | 755 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 756 .icache_bsize = 32, 757 .dcache_bsize = 32, 758 }, 759 { /* STB 04xxx */ 760 .pvr_mask = 0xffff0000, 761 .pvr_value = 0x41810000, 762 .cpu_name = "STB04xxx", 763 .cpu_features = CPU_FTRS_40X, 764 .cpu_user_features = PPC_FEATURE_32 | 765 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 766 .icache_bsize = 32, 767 .dcache_bsize = 32, 768 }, 769 { /* NP405L */ 770 .pvr_mask = 0xffff0000, 771 .pvr_value = 0x41610000, 772 .cpu_name = "NP405L", 773 .cpu_features = CPU_FTRS_40X, 774 .cpu_user_features = PPC_FEATURE_32 | 775 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 776 .icache_bsize = 32, 777 .dcache_bsize = 32, 778 }, 779 { /* NP4GS3 */ 780 .pvr_mask = 0xffff0000, 781 .pvr_value = 0x40B10000, 782 .cpu_name = "NP4GS3", 783 .cpu_features = CPU_FTRS_40X, 784 .cpu_user_features = PPC_FEATURE_32 | 785 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 786 .icache_bsize = 32, 787 .dcache_bsize = 32, 788 }, 789 { /* NP405H */ 790 .pvr_mask = 0xffff0000, 791 .pvr_value = 0x41410000, 792 .cpu_name = "NP405H", 793 .cpu_features = CPU_FTRS_40X, 794 .cpu_user_features = PPC_FEATURE_32 | 795 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 796 .icache_bsize = 32, 797 .dcache_bsize = 32, 798 }, 799 { /* 405GPr */ 800 .pvr_mask = 0xffff0000, 801 .pvr_value = 0x50910000, 802 .cpu_name = "405GPr", 803 .cpu_features = CPU_FTRS_40X, 804 .cpu_user_features = PPC_FEATURE_32 | 805 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 806 .icache_bsize = 32, 807 .dcache_bsize = 32, 808 }, 809 { /* STBx25xx */ 810 .pvr_mask = 0xffff0000, 811 .pvr_value = 0x51510000, 812 .cpu_name = "STBx25xx", 813 .cpu_features = CPU_FTRS_40X, 814 .cpu_user_features = PPC_FEATURE_32 | 815 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 816 .icache_bsize = 32, 817 .dcache_bsize = 32, 818 }, 819 { /* 405LP */ 820 .pvr_mask = 0xffff0000, 821 .pvr_value = 0x41F10000, 822 .cpu_name = "405LP", 823 .cpu_features = CPU_FTRS_40X, 824 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 825 .icache_bsize = 32, 826 .dcache_bsize = 32, 827 }, 828 { /* Xilinx Virtex-II Pro */ 829 .pvr_mask = 0xffff0000, 830 .pvr_value = 0x20010000, 831 .cpu_name = "Virtex-II Pro", 832 .cpu_features = CPU_FTRS_40X, 833 .cpu_user_features = PPC_FEATURE_32 | 834 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 835 .icache_bsize = 32, 836 .dcache_bsize = 32, 837 }, 838 { /* 405EP */ 839 .pvr_mask = 0xffff0000, 840 .pvr_value = 0x51210000, 841 .cpu_name = "405EP", 842 .cpu_features = CPU_FTRS_40X, 843 .cpu_user_features = PPC_FEATURE_32 | 844 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 845 .icache_bsize = 32, 846 .dcache_bsize = 32, 847 }, 848 849 #endif /* CONFIG_40x */ 850 #ifdef CONFIG_44x 851 { 852 .pvr_mask = 0xf0000fff, 853 .pvr_value = 0x40000850, 854 .cpu_name = "440EP Rev. A", 855 .cpu_features = CPU_FTRS_44X, 856 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 857 .icache_bsize = 32, 858 .dcache_bsize = 32, 859 }, 860 { 861 .pvr_mask = 0xf0000fff, 862 .pvr_value = 0x400008d3, 863 .cpu_name = "440EP Rev. B", 864 .cpu_features = CPU_FTRS_44X, 865 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */ 866 .icache_bsize = 32, 867 .dcache_bsize = 32, 868 }, 869 { /* 440GP Rev. B */ 870 .pvr_mask = 0xf0000fff, 871 .pvr_value = 0x40000440, 872 .cpu_name = "440GP Rev. B", 873 .cpu_features = CPU_FTRS_44X, 874 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 875 .icache_bsize = 32, 876 .dcache_bsize = 32, 877 }, 878 { /* 440GP Rev. C */ 879 .pvr_mask = 0xf0000fff, 880 .pvr_value = 0x40000481, 881 .cpu_name = "440GP Rev. C", 882 .cpu_features = CPU_FTRS_44X, 883 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 884 .icache_bsize = 32, 885 .dcache_bsize = 32, 886 }, 887 { /* 440GX Rev. A */ 888 .pvr_mask = 0xf0000fff, 889 .pvr_value = 0x50000850, 890 .cpu_name = "440GX Rev. A", 891 .cpu_features = CPU_FTRS_44X, 892 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 893 .icache_bsize = 32, 894 .dcache_bsize = 32, 895 }, 896 { /* 440GX Rev. B */ 897 .pvr_mask = 0xf0000fff, 898 .pvr_value = 0x50000851, 899 .cpu_name = "440GX Rev. B", 900 .cpu_features = CPU_FTRS_44X, 901 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 902 .icache_bsize = 32, 903 .dcache_bsize = 32, 904 }, 905 { /* 440GX Rev. C */ 906 .pvr_mask = 0xf0000fff, 907 .pvr_value = 0x50000892, 908 .cpu_name = "440GX Rev. C", 909 .cpu_features = CPU_FTRS_44X, 910 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 911 .icache_bsize = 32, 912 .dcache_bsize = 32, 913 }, 914 { /* 440GX Rev. F */ 915 .pvr_mask = 0xf0000fff, 916 .pvr_value = 0x50000894, 917 .cpu_name = "440GX Rev. F", 918 .cpu_features = CPU_FTRS_44X, 919 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 920 .icache_bsize = 32, 921 .dcache_bsize = 32, 922 }, 923 { /* 440SP Rev. A */ 924 .pvr_mask = 0xff000fff, 925 .pvr_value = 0x53000891, 926 .cpu_name = "440SP Rev. A", 927 .cpu_features = CPU_FTRS_44X, 928 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 929 .icache_bsize = 32, 930 .dcache_bsize = 32, 931 }, 932 { /* 440SPe Rev. A */ 933 .pvr_mask = 0xff000fff, 934 .pvr_value = 0x53000890, 935 .cpu_name = "440SPe Rev. A", 936 .cpu_features = CPU_FTR_SPLIT_ID_CACHE | 937 CPU_FTR_USE_TB, 938 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 939 .icache_bsize = 32, 940 .dcache_bsize = 32, 941 }, 942 #endif /* CONFIG_44x */ 943 #ifdef CONFIG_FSL_BOOKE 944 { /* e200z5 */ 945 .pvr_mask = 0xfff00000, 946 .pvr_value = 0x81000000, 947 .cpu_name = "e200z5", 948 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 949 .cpu_features = CPU_FTRS_E200, 950 .cpu_user_features = PPC_FEATURE_32 | 951 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE | 952 PPC_FEATURE_UNIFIED_CACHE, 953 .dcache_bsize = 32, 954 }, 955 { /* e200z6 */ 956 .pvr_mask = 0xfff00000, 957 .pvr_value = 0x81100000, 958 .cpu_name = "e200z6", 959 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 960 .cpu_features = CPU_FTRS_E200, 961 .cpu_user_features = PPC_FEATURE_32 | 962 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 963 PPC_FEATURE_HAS_EFP_SINGLE | 964 PPC_FEATURE_UNIFIED_CACHE, 965 .dcache_bsize = 32, 966 }, 967 { /* e500 */ 968 .pvr_mask = 0xffff0000, 969 .pvr_value = 0x80200000, 970 .cpu_name = "e500", 971 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 972 .cpu_features = CPU_FTRS_E500, 973 .cpu_user_features = PPC_FEATURE_32 | 974 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 975 PPC_FEATURE_HAS_EFP_SINGLE, 976 .icache_bsize = 32, 977 .dcache_bsize = 32, 978 .num_pmcs = 4, 979 }, 980 { /* e500v2 */ 981 .pvr_mask = 0xffff0000, 982 .pvr_value = 0x80210000, 983 .cpu_name = "e500v2", 984 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ 985 .cpu_features = CPU_FTRS_E500_2, 986 .cpu_user_features = PPC_FEATURE_32 | 987 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | 988 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 989 .icache_bsize = 32, 990 .dcache_bsize = 32, 991 .num_pmcs = 4, 992 }, 993 #endif 994 #if !CLASSIC_PPC 995 { /* default match */ 996 .pvr_mask = 0x00000000, 997 .pvr_value = 0x00000000, 998 .cpu_name = "(generic PPC)", 999 .cpu_features = CPU_FTRS_GENERIC_32, 1000 .cpu_user_features = PPC_FEATURE_32, 1001 .icache_bsize = 32, 1002 .dcache_bsize = 32, 1003 } 1004 #endif /* !CLASSIC_PPC */ 1005 #endif /* CONFIG_PPC32 */ 1006 }; 1007