1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_NA 0 18 #define _PAGE_RO 0 19 #define _PAGE_USER 0 20 21 #define _PAGE_EXEC 0x00001 /* execute permission */ 22 #define _PAGE_WRITE 0x00002 /* write access allowed */ 23 #define _PAGE_READ 0x00004 /* read access allowed */ 24 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 25 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 26 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 27 #define _PAGE_SAO 0x00010 /* Strong access order */ 28 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 29 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 30 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 31 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 32 /* 33 * Software bits 34 */ 35 #define _RPAGE_SW0 0x2000000000000000UL 36 #define _RPAGE_SW1 0x00800 37 #define _RPAGE_SW2 0x00400 38 #define _RPAGE_SW3 0x00200 39 #define _RPAGE_RSV1 0x1000000000000000UL 40 #define _RPAGE_RSV2 0x0800000000000000UL 41 #define _RPAGE_RSV3 0x0400000000000000UL 42 #define _RPAGE_RSV4 0x0200000000000000UL 43 #define _RPAGE_RSV5 0x00040UL 44 45 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 46 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 47 48 /* 49 * Top and bottom bits of RPN which can be used by hash 50 * translation mode, because we expect them to be zero 51 * otherwise. 52 */ 53 #define _RPAGE_RPN0 0x01000 54 #define _RPAGE_RPN1 0x02000 55 #define _RPAGE_RPN44 0x0100000000000000UL 56 #define _RPAGE_RPN43 0x0080000000000000UL 57 #define _RPAGE_RPN42 0x0040000000000000UL 58 #define _RPAGE_RPN41 0x0020000000000000UL 59 60 /* Max physical address bit as per radix table */ 61 #define _RPAGE_PA_MAX 57 62 63 /* 64 * Max physical address bit we will use for now. 65 * 66 * This is mostly a hardware limitation and for now Power9 has 67 * a 51 bit limit. 68 * 69 * This is different from the number of physical bit required to address 70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 72 * number of sections we can support (SECTIONS_SHIFT). 73 * 74 * This is different from Radix page table limitation above and 75 * should always be less than that. The limit is done such that 76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 77 * for hash linux page table specific bits. 78 * 79 * In order to be compatible with future hardware generations we keep 80 * some offsets and limit this for now to 53 81 */ 82 #define _PAGE_PA_MAX 53 83 84 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 85 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 86 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 87 #define __HAVE_ARCH_PTE_DEVMAP 88 89 /* 90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 91 * Instead of fixing all of them, add an alternate define which 92 * maps CI pte mapping. 93 */ 94 #define _PAGE_NO_CACHE _PAGE_TOLERANT 95 /* 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 98 * and every thing below PAGE_SHIFT; 99 */ 100 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 101 /* 102 * set of bits not changed in pmd_modify. Even though we have hash specific bits 103 * in here, on radix we expect them to be zero. 104 */ 105 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 107 _PAGE_SOFT_DIRTY) 108 /* 109 * user access blocked by key 110 */ 111 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 112 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 113 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 114 _PAGE_RW | _PAGE_EXEC) 115 /* 116 * No page size encoding in the linux PTE 117 */ 118 #define _PAGE_PSIZE 0 119 /* 120 * _PAGE_CHG_MASK masks of bits that are to be preserved across 121 * pgprot changes 122 */ 123 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 125 _PAGE_SOFT_DIRTY) 126 127 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 129 /* 130 * Mask of bits returned by pte_pgprot() 131 */ 132 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY) 136 /* 137 * We define 2 sets of base prot bits, one for basic pages (ie, 138 * cacheable kernel and user pages) and one for non cacheable 139 * pages. We always set _PAGE_COHERENT when SMP is enabled or 140 * the processor might need it for DMA coherency. 141 */ 142 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 143 #define _PAGE_BASE (_PAGE_BASE_NC) 144 145 /* Permission masks used to generate the __P and __S table, 146 * 147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 148 * 149 * Write permissions imply read permissions for now (we could make write-only 150 * pages on BookE but we don't bother for now). Execute permission control is 151 * possible on platforms that define _PAGE_EXEC 152 * 153 * Note due to the way vm flags are laid out, the bits are XWR 154 */ 155 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 156 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 157 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 158 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 159 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 160 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 161 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 162 163 #define __P000 PAGE_NONE 164 #define __P001 PAGE_READONLY 165 #define __P010 PAGE_COPY 166 #define __P011 PAGE_COPY 167 #define __P100 PAGE_READONLY_X 168 #define __P101 PAGE_READONLY_X 169 #define __P110 PAGE_COPY_X 170 #define __P111 PAGE_COPY_X 171 172 #define __S000 PAGE_NONE 173 #define __S001 PAGE_READONLY 174 #define __S010 PAGE_SHARED 175 #define __S011 PAGE_SHARED 176 #define __S100 PAGE_READONLY_X 177 #define __S101 PAGE_READONLY_X 178 #define __S110 PAGE_SHARED_X 179 #define __S111 PAGE_SHARED_X 180 181 /* Permission masks used for kernel mappings */ 182 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 183 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 184 _PAGE_TOLERANT) 185 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 186 _PAGE_NON_IDEMPOTENT) 187 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 188 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 189 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 190 191 /* 192 * Protection used for kernel text. We want the debuggers to be able to 193 * set breakpoints anywhere, so don't write protect the kernel text 194 * on platforms where such control is possible. 195 */ 196 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 198 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 199 #else 200 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 201 #endif 202 203 /* Make modules code happy. We don't set RO yet */ 204 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 205 #define PAGE_AGP (PAGE_KERNEL_NC) 206 207 #ifndef __ASSEMBLY__ 208 /* 209 * page table defines 210 */ 211 extern unsigned long __pte_index_size; 212 extern unsigned long __pmd_index_size; 213 extern unsigned long __pud_index_size; 214 extern unsigned long __pgd_index_size; 215 extern unsigned long __pud_cache_index; 216 #define PTE_INDEX_SIZE __pte_index_size 217 #define PMD_INDEX_SIZE __pmd_index_size 218 #define PUD_INDEX_SIZE __pud_index_size 219 #define PGD_INDEX_SIZE __pgd_index_size 220 /* pmd table use page table fragments */ 221 #define PMD_CACHE_INDEX 0 222 #define PUD_CACHE_INDEX __pud_cache_index 223 /* 224 * Because of use of pte fragments and THP, size of page table 225 * are not always derived out of index size above. 226 */ 227 extern unsigned long __pte_table_size; 228 extern unsigned long __pmd_table_size; 229 extern unsigned long __pud_table_size; 230 extern unsigned long __pgd_table_size; 231 #define PTE_TABLE_SIZE __pte_table_size 232 #define PMD_TABLE_SIZE __pmd_table_size 233 #define PUD_TABLE_SIZE __pud_table_size 234 #define PGD_TABLE_SIZE __pgd_table_size 235 236 extern unsigned long __pmd_val_bits; 237 extern unsigned long __pud_val_bits; 238 extern unsigned long __pgd_val_bits; 239 #define PMD_VAL_BITS __pmd_val_bits 240 #define PUD_VAL_BITS __pud_val_bits 241 #define PGD_VAL_BITS __pgd_val_bits 242 243 extern unsigned long __pte_frag_nr; 244 #define PTE_FRAG_NR __pte_frag_nr 245 extern unsigned long __pte_frag_size_shift; 246 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 247 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 248 249 extern unsigned long __pmd_frag_nr; 250 #define PMD_FRAG_NR __pmd_frag_nr 251 extern unsigned long __pmd_frag_size_shift; 252 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 253 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 254 255 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 256 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 257 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 258 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 259 260 /* PMD_SHIFT determines what a second-level page table entry can map */ 261 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 262 #define PMD_SIZE (1UL << PMD_SHIFT) 263 #define PMD_MASK (~(PMD_SIZE-1)) 264 265 /* PUD_SHIFT determines what a third-level page table entry can map */ 266 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 267 #define PUD_SIZE (1UL << PUD_SHIFT) 268 #define PUD_MASK (~(PUD_SIZE-1)) 269 270 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 271 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 272 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 273 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 274 275 /* Bits to mask out from a PMD to get to the PTE page */ 276 #define PMD_MASKED_BITS 0xc0000000000000ffUL 277 /* Bits to mask out from a PUD to get to the PMD page */ 278 #define PUD_MASKED_BITS 0xc0000000000000ffUL 279 /* Bits to mask out from a PGD to get to the PUD page */ 280 #define PGD_MASKED_BITS 0xc0000000000000ffUL 281 282 /* 283 * Used as an indicator for rcu callback functions 284 */ 285 enum pgtable_index { 286 PTE_INDEX = 0, 287 PMD_INDEX, 288 PUD_INDEX, 289 PGD_INDEX, 290 }; 291 292 extern unsigned long __vmalloc_start; 293 extern unsigned long __vmalloc_end; 294 #define VMALLOC_START __vmalloc_start 295 #define VMALLOC_END __vmalloc_end 296 297 extern unsigned long __kernel_virt_start; 298 extern unsigned long __kernel_virt_size; 299 extern unsigned long __kernel_io_start; 300 #define KERN_VIRT_START __kernel_virt_start 301 #define KERN_VIRT_SIZE __kernel_virt_size 302 #define KERN_IO_START __kernel_io_start 303 extern struct page *vmemmap; 304 extern unsigned long ioremap_bot; 305 extern unsigned long pci_io_base; 306 #endif /* __ASSEMBLY__ */ 307 308 #include <asm/book3s/64/hash.h> 309 #include <asm/book3s/64/radix.h> 310 311 #ifdef CONFIG_PPC_64K_PAGES 312 #include <asm/book3s/64/pgtable-64k.h> 313 #else 314 #include <asm/book3s/64/pgtable-4k.h> 315 #endif 316 317 #include <asm/barrier.h> 318 /* 319 * The second half of the kernel virtual space is used for IO mappings, 320 * it's itself carved into the PIO region (ISA and PHB IO space) and 321 * the ioremap space 322 * 323 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 324 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 325 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 326 */ 327 #define FULL_IO_SIZE 0x80000000ul 328 #define ISA_IO_BASE (KERN_IO_START) 329 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 330 #define PHB_IO_BASE (ISA_IO_END) 331 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 332 #define IOREMAP_BASE (PHB_IO_END) 333 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 334 335 /* Advertise special mapping type for AGP */ 336 #define HAVE_PAGE_AGP 337 338 /* Advertise support for _PAGE_SPECIAL */ 339 #define __HAVE_ARCH_PTE_SPECIAL 340 341 #ifndef __ASSEMBLY__ 342 343 /* 344 * This is the default implementation of various PTE accessors, it's 345 * used in all cases except Book3S with 64K pages where we have a 346 * concept of sub-pages 347 */ 348 #ifndef __real_pte 349 350 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 351 #define __rpte_to_pte(r) ((r).pte) 352 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 353 354 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 355 do { \ 356 index = 0; \ 357 shift = mmu_psize_defs[psize].shift; \ 358 359 #define pte_iterate_hashed_end() } while(0) 360 361 /* 362 * We expect this to be called only for user addresses or kernel virtual 363 * addresses other than the linear mapping. 364 */ 365 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 366 367 #endif /* __real_pte */ 368 369 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 370 pte_t *ptep, unsigned long clr, 371 unsigned long set, int huge) 372 { 373 if (radix_enabled()) 374 return radix__pte_update(mm, addr, ptep, clr, set, huge); 375 return hash__pte_update(mm, addr, ptep, clr, set, huge); 376 } 377 /* 378 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 379 * We currently remove entries from the hashtable regardless of whether 380 * the entry was young or dirty. 381 * 382 * We should be more intelligent about this but for the moment we override 383 * these functions and force a tlb flush unconditionally 384 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 385 * function for both hash and radix. 386 */ 387 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 388 unsigned long addr, pte_t *ptep) 389 { 390 unsigned long old; 391 392 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 393 return 0; 394 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 395 return (old & _PAGE_ACCESSED) != 0; 396 } 397 398 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 399 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 400 ({ \ 401 int __r; \ 402 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 403 __r; \ 404 }) 405 406 static inline int __pte_write(pte_t pte) 407 { 408 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 409 } 410 411 #ifdef CONFIG_NUMA_BALANCING 412 #define pte_savedwrite pte_savedwrite 413 static inline bool pte_savedwrite(pte_t pte) 414 { 415 /* 416 * Saved write ptes are prot none ptes that doesn't have 417 * privileged bit sit. We mark prot none as one which has 418 * present and pviliged bit set and RWX cleared. To mark 419 * protnone which used to have _PAGE_WRITE set we clear 420 * the privileged bit. 421 */ 422 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 423 } 424 #else 425 #define pte_savedwrite pte_savedwrite 426 static inline bool pte_savedwrite(pte_t pte) 427 { 428 return false; 429 } 430 #endif 431 432 static inline int pte_write(pte_t pte) 433 { 434 return __pte_write(pte) || pte_savedwrite(pte); 435 } 436 437 static inline int pte_read(pte_t pte) 438 { 439 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 440 } 441 442 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 443 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 444 pte_t *ptep) 445 { 446 if (__pte_write(*ptep)) 447 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 448 else if (unlikely(pte_savedwrite(*ptep))) 449 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 450 } 451 452 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 453 unsigned long addr, pte_t *ptep) 454 { 455 /* 456 * We should not find protnone for hugetlb, but this complete the 457 * interface. 458 */ 459 if (__pte_write(*ptep)) 460 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 461 else if (unlikely(pte_savedwrite(*ptep))) 462 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 463 } 464 465 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 466 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 467 unsigned long addr, pte_t *ptep) 468 { 469 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 470 return __pte(old); 471 } 472 473 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 474 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 475 unsigned long addr, 476 pte_t *ptep, int full) 477 { 478 if (full && radix_enabled()) { 479 /* 480 * Let's skip the DD1 style pte update here. We know that 481 * this is a full mm pte clear and hence can be sure there is 482 * no parallel set_pte. 483 */ 484 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 485 } 486 return ptep_get_and_clear(mm, addr, ptep); 487 } 488 489 490 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 491 pte_t * ptep) 492 { 493 pte_update(mm, addr, ptep, ~0UL, 0, 0); 494 } 495 496 static inline int pte_dirty(pte_t pte) 497 { 498 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 499 } 500 501 static inline int pte_young(pte_t pte) 502 { 503 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 504 } 505 506 static inline int pte_special(pte_t pte) 507 { 508 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 509 } 510 511 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 512 513 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 514 static inline bool pte_soft_dirty(pte_t pte) 515 { 516 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 517 } 518 519 static inline pte_t pte_mksoft_dirty(pte_t pte) 520 { 521 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 522 } 523 524 static inline pte_t pte_clear_soft_dirty(pte_t pte) 525 { 526 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 527 } 528 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 529 530 #ifdef CONFIG_NUMA_BALANCING 531 static inline int pte_protnone(pte_t pte) 532 { 533 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 534 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 535 } 536 537 #define pte_mk_savedwrite pte_mk_savedwrite 538 static inline pte_t pte_mk_savedwrite(pte_t pte) 539 { 540 /* 541 * Used by Autonuma subsystem to preserve the write bit 542 * while marking the pte PROT_NONE. Only allow this 543 * on PROT_NONE pte 544 */ 545 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 546 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 547 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 548 } 549 550 #define pte_clear_savedwrite pte_clear_savedwrite 551 static inline pte_t pte_clear_savedwrite(pte_t pte) 552 { 553 /* 554 * Used by KSM subsystem to make a protnone pte readonly. 555 */ 556 VM_BUG_ON(!pte_protnone(pte)); 557 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 558 } 559 #else 560 #define pte_clear_savedwrite pte_clear_savedwrite 561 static inline pte_t pte_clear_savedwrite(pte_t pte) 562 { 563 VM_WARN_ON(1); 564 return __pte(pte_val(pte) & ~_PAGE_WRITE); 565 } 566 #endif /* CONFIG_NUMA_BALANCING */ 567 568 static inline int pte_present(pte_t pte) 569 { 570 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 571 } 572 573 #ifdef CONFIG_PPC_MEM_KEYS 574 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 575 #else 576 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 577 { 578 return true; 579 } 580 #endif /* CONFIG_PPC_MEM_KEYS */ 581 582 #define pte_access_permitted pte_access_permitted 583 static inline bool pte_access_permitted(pte_t pte, bool write) 584 { 585 unsigned long pteval = pte_val(pte); 586 /* Also check for pte_user */ 587 unsigned long clear_pte_bits = _PAGE_PRIVILEGED; 588 /* 589 * _PAGE_READ is needed for any access and will be 590 * cleared for PROT_NONE 591 */ 592 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ; 593 594 if (write) 595 need_pte_bits |= _PAGE_WRITE; 596 597 if ((pteval & need_pte_bits) != need_pte_bits) 598 return false; 599 600 if ((pteval & clear_pte_bits) == clear_pte_bits) 601 return false; 602 603 return arch_pte_access_permitted(pte_val(pte), write, 0); 604 } 605 606 /* 607 * Conversion functions: convert a page and protection to a page entry, 608 * and a page entry and page directory to the page they refer to. 609 * 610 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 611 * long for now. 612 */ 613 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 614 { 615 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 616 pgprot_val(pgprot)); 617 } 618 619 static inline unsigned long pte_pfn(pte_t pte) 620 { 621 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 622 } 623 624 /* Generic modifiers for PTE bits */ 625 static inline pte_t pte_wrprotect(pte_t pte) 626 { 627 if (unlikely(pte_savedwrite(pte))) 628 return pte_clear_savedwrite(pte); 629 return __pte(pte_val(pte) & ~_PAGE_WRITE); 630 } 631 632 static inline pte_t pte_mkclean(pte_t pte) 633 { 634 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 635 } 636 637 static inline pte_t pte_mkold(pte_t pte) 638 { 639 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 640 } 641 642 static inline pte_t pte_mkwrite(pte_t pte) 643 { 644 /* 645 * write implies read, hence set both 646 */ 647 return __pte(pte_val(pte) | _PAGE_RW); 648 } 649 650 static inline pte_t pte_mkdirty(pte_t pte) 651 { 652 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 653 } 654 655 static inline pte_t pte_mkyoung(pte_t pte) 656 { 657 return __pte(pte_val(pte) | _PAGE_ACCESSED); 658 } 659 660 static inline pte_t pte_mkspecial(pte_t pte) 661 { 662 return __pte(pte_val(pte) | _PAGE_SPECIAL); 663 } 664 665 static inline pte_t pte_mkhuge(pte_t pte) 666 { 667 return pte; 668 } 669 670 static inline pte_t pte_mkdevmap(pte_t pte) 671 { 672 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); 673 } 674 675 /* 676 * This is potentially called with a pmd as the argument, in which case it's not 677 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 678 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 679 * use in page directory entries (ie. non-ptes). 680 */ 681 static inline int pte_devmap(pte_t pte) 682 { 683 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 684 685 return (pte_raw(pte) & mask) == mask; 686 } 687 688 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 689 { 690 /* FIXME!! check whether this need to be a conditional */ 691 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 692 } 693 694 static inline bool pte_user(pte_t pte) 695 { 696 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 697 } 698 699 /* Encode and de-code a swap entry */ 700 #define MAX_SWAPFILES_CHECK() do { \ 701 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 702 /* \ 703 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 704 * We filter HPTEFLAGS on set_pte. \ 705 */ \ 706 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 707 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 708 } while (0) 709 /* 710 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 711 */ 712 #define SWP_TYPE_BITS 5 713 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 714 & ((1UL << SWP_TYPE_BITS) - 1)) 715 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 716 #define __swp_entry(type, offset) ((swp_entry_t) { \ 717 ((type) << _PAGE_BIT_SWAP_TYPE) \ 718 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 719 /* 720 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 721 * swap type and offset we get from swap and convert that to pte to find a 722 * matching pte in linux page table. 723 * Clear bits not found in swap entries here. 724 */ 725 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 726 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 727 728 #ifdef CONFIG_MEM_SOFT_DIRTY 729 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 730 #else 731 #define _PAGE_SWP_SOFT_DIRTY 0UL 732 #endif /* CONFIG_MEM_SOFT_DIRTY */ 733 734 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 735 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 736 { 737 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 738 } 739 740 static inline bool pte_swp_soft_dirty(pte_t pte) 741 { 742 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 743 } 744 745 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 746 { 747 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 748 } 749 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 750 751 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 752 { 753 /* 754 * This check for _PAGE_RWX and _PAGE_PRESENT bits 755 */ 756 if (access & ~ptev) 757 return false; 758 /* 759 * This check for access to privilege space 760 */ 761 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 762 return false; 763 764 return true; 765 } 766 /* 767 * Generic functions with hash/radix callbacks 768 */ 769 770 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 771 pte_t *ptep, pte_t entry, 772 unsigned long address, 773 int psize) 774 { 775 if (radix_enabled()) 776 return radix__ptep_set_access_flags(vma, ptep, entry, 777 address, psize); 778 return hash__ptep_set_access_flags(ptep, entry); 779 } 780 781 #define __HAVE_ARCH_PTE_SAME 782 static inline int pte_same(pte_t pte_a, pte_t pte_b) 783 { 784 if (radix_enabled()) 785 return radix__pte_same(pte_a, pte_b); 786 return hash__pte_same(pte_a, pte_b); 787 } 788 789 static inline int pte_none(pte_t pte) 790 { 791 if (radix_enabled()) 792 return radix__pte_none(pte); 793 return hash__pte_none(pte); 794 } 795 796 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 797 pte_t *ptep, pte_t pte, int percpu) 798 { 799 if (radix_enabled()) 800 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 801 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 802 } 803 804 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 805 806 #define pgprot_noncached pgprot_noncached 807 static inline pgprot_t pgprot_noncached(pgprot_t prot) 808 { 809 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 810 _PAGE_NON_IDEMPOTENT); 811 } 812 813 #define pgprot_noncached_wc pgprot_noncached_wc 814 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 815 { 816 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 817 _PAGE_TOLERANT); 818 } 819 820 #define pgprot_cached pgprot_cached 821 static inline pgprot_t pgprot_cached(pgprot_t prot) 822 { 823 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 824 } 825 826 #define pgprot_writecombine pgprot_writecombine 827 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 828 { 829 return pgprot_noncached_wc(prot); 830 } 831 /* 832 * check a pte mapping have cache inhibited property 833 */ 834 static inline bool pte_ci(pte_t pte) 835 { 836 unsigned long pte_v = pte_val(pte); 837 838 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 839 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 840 return true; 841 return false; 842 } 843 844 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 845 { 846 *pmdp = __pmd(val); 847 } 848 849 static inline void pmd_clear(pmd_t *pmdp) 850 { 851 *pmdp = __pmd(0); 852 } 853 854 static inline int pmd_none(pmd_t pmd) 855 { 856 return !pmd_raw(pmd); 857 } 858 859 static inline int pmd_present(pmd_t pmd) 860 { 861 862 return !pmd_none(pmd); 863 } 864 865 static inline int pmd_bad(pmd_t pmd) 866 { 867 if (radix_enabled()) 868 return radix__pmd_bad(pmd); 869 return hash__pmd_bad(pmd); 870 } 871 872 static inline void pud_set(pud_t *pudp, unsigned long val) 873 { 874 *pudp = __pud(val); 875 } 876 877 static inline void pud_clear(pud_t *pudp) 878 { 879 *pudp = __pud(0); 880 } 881 882 static inline int pud_none(pud_t pud) 883 { 884 return !pud_raw(pud); 885 } 886 887 static inline int pud_present(pud_t pud) 888 { 889 return !pud_none(pud); 890 } 891 892 extern struct page *pud_page(pud_t pud); 893 extern struct page *pmd_page(pmd_t pmd); 894 static inline pte_t pud_pte(pud_t pud) 895 { 896 return __pte_raw(pud_raw(pud)); 897 } 898 899 static inline pud_t pte_pud(pte_t pte) 900 { 901 return __pud_raw(pte_raw(pte)); 902 } 903 #define pud_write(pud) pte_write(pud_pte(pud)) 904 905 static inline int pud_bad(pud_t pud) 906 { 907 if (radix_enabled()) 908 return radix__pud_bad(pud); 909 return hash__pud_bad(pud); 910 } 911 912 #define pud_access_permitted pud_access_permitted 913 static inline bool pud_access_permitted(pud_t pud, bool write) 914 { 915 return pte_access_permitted(pud_pte(pud), write); 916 } 917 918 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 919 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 920 { 921 *pgdp = __pgd(val); 922 } 923 924 static inline void pgd_clear(pgd_t *pgdp) 925 { 926 *pgdp = __pgd(0); 927 } 928 929 static inline int pgd_none(pgd_t pgd) 930 { 931 return !pgd_raw(pgd); 932 } 933 934 static inline int pgd_present(pgd_t pgd) 935 { 936 return !pgd_none(pgd); 937 } 938 939 static inline pte_t pgd_pte(pgd_t pgd) 940 { 941 return __pte_raw(pgd_raw(pgd)); 942 } 943 944 static inline pgd_t pte_pgd(pte_t pte) 945 { 946 return __pgd_raw(pte_raw(pte)); 947 } 948 949 static inline int pgd_bad(pgd_t pgd) 950 { 951 if (radix_enabled()) 952 return radix__pgd_bad(pgd); 953 return hash__pgd_bad(pgd); 954 } 955 956 #define pgd_access_permitted pgd_access_permitted 957 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 958 { 959 return pte_access_permitted(pgd_pte(pgd), write); 960 } 961 962 extern struct page *pgd_page(pgd_t pgd); 963 964 /* Pointers in the page table tree are physical addresses */ 965 #define __pgtable_ptr_val(ptr) __pa(ptr) 966 967 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 968 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 969 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 970 971 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 972 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 973 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 974 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 975 976 /* 977 * Find an entry in a page-table-directory. We combine the address region 978 * (the high order N bits) and the pgd portion of the address. 979 */ 980 981 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 982 983 #define pud_offset(pgdp, addr) \ 984 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 985 #define pmd_offset(pudp,addr) \ 986 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 987 #define pte_offset_kernel(dir,addr) \ 988 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 989 990 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 991 #define pte_unmap(pte) do { } while(0) 992 993 /* to find an entry in a kernel page-table-directory */ 994 /* This now only contains the vmalloc pages */ 995 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 996 997 #define pte_ERROR(e) \ 998 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 999 #define pmd_ERROR(e) \ 1000 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1001 #define pud_ERROR(e) \ 1002 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1003 #define pgd_ERROR(e) \ 1004 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1005 1006 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 1007 unsigned long flags) 1008 { 1009 if (radix_enabled()) { 1010 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1011 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1012 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1013 #endif 1014 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 1015 } 1016 return hash__map_kernel_page(ea, pa, flags); 1017 } 1018 1019 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1020 unsigned long page_size, 1021 unsigned long phys) 1022 { 1023 if (radix_enabled()) 1024 return radix__vmemmap_create_mapping(start, page_size, phys); 1025 return hash__vmemmap_create_mapping(start, page_size, phys); 1026 } 1027 1028 #ifdef CONFIG_MEMORY_HOTPLUG 1029 static inline void vmemmap_remove_mapping(unsigned long start, 1030 unsigned long page_size) 1031 { 1032 if (radix_enabled()) 1033 return radix__vmemmap_remove_mapping(start, page_size); 1034 return hash__vmemmap_remove_mapping(start, page_size); 1035 } 1036 #endif 1037 struct page *realmode_pfn_to_page(unsigned long pfn); 1038 1039 static inline pte_t pmd_pte(pmd_t pmd) 1040 { 1041 return __pte_raw(pmd_raw(pmd)); 1042 } 1043 1044 static inline pmd_t pte_pmd(pte_t pte) 1045 { 1046 return __pmd_raw(pte_raw(pte)); 1047 } 1048 1049 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1050 { 1051 return (pte_t *)pmd; 1052 } 1053 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1054 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1055 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1056 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1057 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1058 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1059 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1060 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1061 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1062 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1063 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1064 1065 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1066 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1067 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1068 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1069 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1070 1071 #ifdef CONFIG_NUMA_BALANCING 1072 static inline int pmd_protnone(pmd_t pmd) 1073 { 1074 return pte_protnone(pmd_pte(pmd)); 1075 } 1076 #endif /* CONFIG_NUMA_BALANCING */ 1077 1078 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1079 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1080 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1081 1082 #define pmd_access_permitted pmd_access_permitted 1083 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1084 { 1085 return pte_access_permitted(pmd_pte(pmd), write); 1086 } 1087 1088 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1089 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1090 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1091 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1092 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1093 pmd_t *pmdp, pmd_t pmd); 1094 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1095 pmd_t *pmd); 1096 extern int hash__has_transparent_hugepage(void); 1097 static inline int has_transparent_hugepage(void) 1098 { 1099 if (radix_enabled()) 1100 return radix__has_transparent_hugepage(); 1101 return hash__has_transparent_hugepage(); 1102 } 1103 #define has_transparent_hugepage has_transparent_hugepage 1104 1105 static inline unsigned long 1106 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1107 unsigned long clr, unsigned long set) 1108 { 1109 if (radix_enabled()) 1110 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1111 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1112 } 1113 1114 static inline int pmd_large(pmd_t pmd) 1115 { 1116 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1117 } 1118 1119 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1120 { 1121 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1122 } 1123 /* 1124 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1125 * the below will work for radix too 1126 */ 1127 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1128 unsigned long addr, pmd_t *pmdp) 1129 { 1130 unsigned long old; 1131 1132 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1133 return 0; 1134 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1135 return ((old & _PAGE_ACCESSED) != 0); 1136 } 1137 1138 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1139 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1140 pmd_t *pmdp) 1141 { 1142 if (__pmd_write((*pmdp))) 1143 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1144 else if (unlikely(pmd_savedwrite(*pmdp))) 1145 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1146 } 1147 1148 static inline int pmd_trans_huge(pmd_t pmd) 1149 { 1150 if (radix_enabled()) 1151 return radix__pmd_trans_huge(pmd); 1152 return hash__pmd_trans_huge(pmd); 1153 } 1154 1155 #define __HAVE_ARCH_PMD_SAME 1156 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1157 { 1158 if (radix_enabled()) 1159 return radix__pmd_same(pmd_a, pmd_b); 1160 return hash__pmd_same(pmd_a, pmd_b); 1161 } 1162 1163 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1164 { 1165 if (radix_enabled()) 1166 return radix__pmd_mkhuge(pmd); 1167 return hash__pmd_mkhuge(pmd); 1168 } 1169 1170 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1171 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1172 unsigned long address, pmd_t *pmdp, 1173 pmd_t entry, int dirty); 1174 1175 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1176 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1177 unsigned long address, pmd_t *pmdp); 1178 1179 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1180 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1181 unsigned long addr, pmd_t *pmdp) 1182 { 1183 if (radix_enabled()) 1184 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1185 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1186 } 1187 1188 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1189 unsigned long address, pmd_t *pmdp) 1190 { 1191 if (radix_enabled()) 1192 return radix__pmdp_collapse_flush(vma, address, pmdp); 1193 return hash__pmdp_collapse_flush(vma, address, pmdp); 1194 } 1195 #define pmdp_collapse_flush pmdp_collapse_flush 1196 1197 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1198 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1199 pmd_t *pmdp, pgtable_t pgtable) 1200 { 1201 if (radix_enabled()) 1202 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1203 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1204 } 1205 1206 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1207 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1208 pmd_t *pmdp) 1209 { 1210 if (radix_enabled()) 1211 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1212 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1213 } 1214 1215 #define __HAVE_ARCH_PMDP_INVALIDATE 1216 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1217 pmd_t *pmdp); 1218 1219 #define pmd_move_must_withdraw pmd_move_must_withdraw 1220 struct spinlock; 1221 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1222 struct spinlock *old_pmd_ptl, 1223 struct vm_area_struct *vma) 1224 { 1225 if (radix_enabled()) 1226 return false; 1227 /* 1228 * Archs like ppc64 use pgtable to store per pmd 1229 * specific information. So when we switch the pmd, 1230 * we should also withdraw and deposit the pgtable 1231 */ 1232 return true; 1233 } 1234 1235 1236 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1237 static inline bool arch_needs_pgtable_deposit(void) 1238 { 1239 if (radix_enabled()) 1240 return false; 1241 return true; 1242 } 1243 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1244 1245 1246 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1247 { 1248 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1249 } 1250 1251 static inline int pmd_devmap(pmd_t pmd) 1252 { 1253 return pte_devmap(pmd_pte(pmd)); 1254 } 1255 1256 static inline int pud_devmap(pud_t pud) 1257 { 1258 return 0; 1259 } 1260 1261 static inline int pgd_devmap(pgd_t pgd) 1262 { 1263 return 0; 1264 } 1265 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1266 1267 static inline const int pud_pfn(pud_t pud) 1268 { 1269 /* 1270 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1271 * check so this should never be used. If it grows another user we 1272 * want to know about it. 1273 */ 1274 BUILD_BUG(); 1275 return 0; 1276 } 1277 1278 #endif /* __ASSEMBLY__ */ 1279 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1280