1 /* 2 * Copyright (C) 2000, 2001 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 /* 20 * These are routines to set up and handle interrupts from the 21 * sb1250 general purpose timer 0. We're using the timer as a 22 * system clock, so we set it up to run at 100 Hz. On every 23 * interrupt, we update our idea of what the time of day is, 24 * then call do_timer() in the architecture-independent kernel 25 * code to do general bookkeeping (e.g. update jiffies, run 26 * bottom halves, etc.) 27 */ 28 #include <linux/config.h> 29 #include <linux/interrupt.h> 30 #include <linux/sched.h> 31 #include <linux/spinlock.h> 32 #include <linux/kernel_stat.h> 33 34 #include <asm/irq.h> 35 #include <asm/ptrace.h> 36 #include <asm/addrspace.h> 37 #include <asm/time.h> 38 #include <asm/io.h> 39 40 #include <asm/sibyte/sb1250.h> 41 #include <asm/sibyte/sb1250_regs.h> 42 #include <asm/sibyte/sb1250_int.h> 43 #include <asm/sibyte/sb1250_scd.h> 44 45 46 #define IMR_IP2_VAL K_INT_MAP_I0 47 #define IMR_IP3_VAL K_INT_MAP_I1 48 #define IMR_IP4_VAL K_INT_MAP_I2 49 50 #define SB1250_HPT_NUM 3 51 #define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ 52 #define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH) 53 54 55 extern int sb1250_steal_irq(int irq); 56 57 static unsigned int sb1250_hpt_read(void); 58 static void sb1250_hpt_init(unsigned int); 59 60 static unsigned int hpt_offset; 61 62 void __init sb1250_hpt_setup(void) 63 { 64 int cpu = smp_processor_id(); 65 66 if (!cpu) { 67 /* Setup hpt using timer #3 but do not enable irq for it */ 68 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 69 __raw_writeq(SB1250_HPT_VALUE, 70 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); 71 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 72 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 73 74 /* 75 * we need to fill 32 bits, so just use the upper 23 bits and pretend 76 * the timer is going 512Mhz instead of 1Mhz 77 */ 78 mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT; 79 mips_hpt_init = sb1250_hpt_init; 80 mips_hpt_read = sb1250_hpt_read; 81 } 82 } 83 84 85 void sb1250_time_init(void) 86 { 87 int cpu = smp_processor_id(); 88 int irq = K_INT_TIMER_0+cpu; 89 90 /* Only have 4 general purpose timers, and we use last one as hpt */ 91 if (cpu > 2) { 92 BUG(); 93 } 94 95 sb1250_mask_irq(cpu, irq); 96 97 /* Map the timer interrupt to ip[4] of this cpu */ 98 __raw_writeq(IMR_IP4_VAL, 99 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 100 (irq << 3))); 101 102 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ 103 /* Disable the timer and set up the count */ 104 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 105 #ifdef CONFIG_SIMULATION 106 __raw_writeq((50000 / HZ) - 1, 107 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 108 #else 109 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, 110 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 111 #endif 112 113 /* Set the timer running */ 114 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 115 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 116 117 sb1250_unmask_irq(cpu, irq); 118 sb1250_steal_irq(irq); 119 /* 120 * This interrupt is "special" in that it doesn't use the request_irq 121 * way to hook the irq line. The timer interrupt is initialized early 122 * enough to make this a major pain, and it's also firing enough to 123 * warrant a bit of special case code. sb1250_timer_interrupt is 124 * called directly from irq_handler.S when IP[4] is set during an 125 * interrupt 126 */ 127 } 128 129 void sb1250_timer_interrupt(struct pt_regs *regs) 130 { 131 int cpu = smp_processor_id(); 132 int irq = K_INT_TIMER_0 + cpu; 133 134 /* ACK interrupt */ 135 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 136 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 137 138 if (cpu == 0) { 139 /* 140 * CPU 0 handles the global timer interrupt job 141 */ 142 ll_timer_interrupt(irq, regs); 143 } 144 else { 145 /* 146 * other CPUs should just do profiling and process accounting 147 */ 148 ll_local_timer_interrupt(irq, regs); 149 } 150 } 151 152 /* 153 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 154 * again. There's no easy way to set to a specific value so store init value 155 * in hpt_offset and subtract each time. 156 * 157 * Note: Timer isn't full 32bits so shift it into the upper part making 158 * it appear to run at a higher frequency. 159 */ 160 static unsigned int sb1250_hpt_read(void) 161 { 162 unsigned int count; 163 164 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); 165 166 count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT; 167 168 return count - hpt_offset; 169 } 170 171 static void sb1250_hpt_init(unsigned int count) 172 { 173 hpt_offset = count; 174 return; 175 } 176