1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004,2005 by Thiemo Seufer 9 * Copyright (C) 2005 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * 12 * ... and the days got worse and worse and now you see 13 * I've gone completly out of my mind. 14 * 15 * They're coming to take me a away haha 16 * they're coming to take me a away hoho hihi haha 17 * to the funny farm where code is beautiful all the time ... 18 * 19 * (Condolences to Napoleon XIV) 20 */ 21 22 #include <stdarg.h> 23 24 #include <linux/config.h> 25 #include <linux/mm.h> 26 #include <linux/kernel.h> 27 #include <linux/types.h> 28 #include <linux/string.h> 29 #include <linux/init.h> 30 31 #include <asm/pgtable.h> 32 #include <asm/cacheflush.h> 33 #include <asm/mmu_context.h> 34 #include <asm/inst.h> 35 #include <asm/elf.h> 36 #include <asm/smp.h> 37 #include <asm/war.h> 38 39 /* #define DEBUG_TLB */ 40 41 static __init int __attribute__((unused)) r45k_bvahwbug(void) 42 { 43 /* XXX: We should probe for the presence of this bug, but we don't. */ 44 return 0; 45 } 46 47 static __init int __attribute__((unused)) r4k_250MHZhwbug(void) 48 { 49 /* XXX: We should probe for the presence of this bug, but we don't. */ 50 return 0; 51 } 52 53 static __init int __attribute__((unused)) bcm1250_m3_war(void) 54 { 55 return BCM1250_M3_WAR; 56 } 57 58 static __init int __attribute__((unused)) r10000_llsc_war(void) 59 { 60 return R10000_LLSC_WAR; 61 } 62 63 /* 64 * A little micro-assembler, intended for TLB refill handler 65 * synthesizing. It is intentionally kept simple, does only support 66 * a subset of instructions, and does not try to hide pipeline effects 67 * like branch delay slots. 68 */ 69 70 enum fields 71 { 72 RS = 0x001, 73 RT = 0x002, 74 RD = 0x004, 75 RE = 0x008, 76 SIMM = 0x010, 77 UIMM = 0x020, 78 BIMM = 0x040, 79 JIMM = 0x080, 80 FUNC = 0x100, 81 SET = 0x200 82 }; 83 84 #define OP_MASK 0x2f 85 #define OP_SH 26 86 #define RS_MASK 0x1f 87 #define RS_SH 21 88 #define RT_MASK 0x1f 89 #define RT_SH 16 90 #define RD_MASK 0x1f 91 #define RD_SH 11 92 #define RE_MASK 0x1f 93 #define RE_SH 6 94 #define IMM_MASK 0xffff 95 #define IMM_SH 0 96 #define JIMM_MASK 0x3ffffff 97 #define JIMM_SH 0 98 #define FUNC_MASK 0x2f 99 #define FUNC_SH 0 100 #define SET_MASK 0x7 101 #define SET_SH 0 102 103 enum opcode { 104 insn_invalid, 105 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 106 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 107 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 108 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 109 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 110 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 111 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 112 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, 113 insn_tlbwr, insn_xor, insn_xori 114 }; 115 116 struct insn { 117 enum opcode opcode; 118 u32 match; 119 enum fields fields; 120 }; 121 122 /* This macro sets the non-variable bits of an instruction. */ 123 #define M(a, b, c, d, e, f) \ 124 ((a) << OP_SH \ 125 | (b) << RS_SH \ 126 | (c) << RT_SH \ 127 | (d) << RD_SH \ 128 | (e) << RE_SH \ 129 | (f) << FUNC_SH) 130 131 static __initdata struct insn insn_table[] = { 132 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 133 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 134 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 135 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 136 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 137 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 138 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 139 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 140 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 141 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 142 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 143 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 145 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 146 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 147 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 148 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 149 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 150 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 151 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 152 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 153 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 154 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 155 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 156 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 157 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 158 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 159 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 160 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 161 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 162 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 163 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 164 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 165 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 166 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 167 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 168 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 169 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 170 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 171 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 172 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 173 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 174 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 175 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 176 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 177 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 178 { insn_invalid, 0, 0 } 179 }; 180 181 #undef M 182 183 static __init u32 build_rs(u32 arg) 184 { 185 if (arg & ~RS_MASK) 186 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 187 188 return (arg & RS_MASK) << RS_SH; 189 } 190 191 static __init u32 build_rt(u32 arg) 192 { 193 if (arg & ~RT_MASK) 194 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 195 196 return (arg & RT_MASK) << RT_SH; 197 } 198 199 static __init u32 build_rd(u32 arg) 200 { 201 if (arg & ~RD_MASK) 202 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 203 204 return (arg & RD_MASK) << RD_SH; 205 } 206 207 static __init u32 build_re(u32 arg) 208 { 209 if (arg & ~RE_MASK) 210 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 211 212 return (arg & RE_MASK) << RE_SH; 213 } 214 215 static __init u32 build_simm(s32 arg) 216 { 217 if (arg > 0x7fff || arg < -0x8000) 218 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 219 220 return arg & 0xffff; 221 } 222 223 static __init u32 build_uimm(u32 arg) 224 { 225 if (arg & ~IMM_MASK) 226 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 227 228 return arg & IMM_MASK; 229 } 230 231 static __init u32 build_bimm(s32 arg) 232 { 233 if (arg > 0x1ffff || arg < -0x20000) 234 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 235 236 if (arg & 0x3) 237 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); 238 239 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 240 } 241 242 static __init u32 build_jimm(u32 arg) 243 { 244 if (arg & ~((JIMM_MASK) << 2)) 245 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 246 247 return (arg >> 2) & JIMM_MASK; 248 } 249 250 static __init u32 build_func(u32 arg) 251 { 252 if (arg & ~FUNC_MASK) 253 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 254 255 return arg & FUNC_MASK; 256 } 257 258 static __init u32 build_set(u32 arg) 259 { 260 if (arg & ~SET_MASK) 261 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 262 263 return arg & SET_MASK; 264 } 265 266 /* 267 * The order of opcode arguments is implicitly left to right, 268 * starting with RS and ending with FUNC or IMM. 269 */ 270 static void __init build_insn(u32 **buf, enum opcode opc, ...) 271 { 272 struct insn *ip = NULL; 273 unsigned int i; 274 va_list ap; 275 u32 op; 276 277 for (i = 0; insn_table[i].opcode != insn_invalid; i++) 278 if (insn_table[i].opcode == opc) { 279 ip = &insn_table[i]; 280 break; 281 } 282 283 if (!ip) 284 panic("Unsupported TLB synthesizer instruction %d", opc); 285 286 op = ip->match; 287 va_start(ap, opc); 288 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); 289 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); 290 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); 291 if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); 292 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); 293 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); 294 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); 295 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); 296 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); 297 if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); 298 va_end(ap); 299 300 **buf = op; 301 (*buf)++; 302 } 303 304 #define I_u1u2u3(op) \ 305 static inline void __init i##op(u32 **buf, unsigned int a, \ 306 unsigned int b, unsigned int c) \ 307 { \ 308 build_insn(buf, insn##op, a, b, c); \ 309 } 310 311 #define I_u2u1u3(op) \ 312 static inline void __init i##op(u32 **buf, unsigned int a, \ 313 unsigned int b, unsigned int c) \ 314 { \ 315 build_insn(buf, insn##op, b, a, c); \ 316 } 317 318 #define I_u3u1u2(op) \ 319 static inline void __init i##op(u32 **buf, unsigned int a, \ 320 unsigned int b, unsigned int c) \ 321 { \ 322 build_insn(buf, insn##op, b, c, a); \ 323 } 324 325 #define I_u1u2s3(op) \ 326 static inline void __init i##op(u32 **buf, unsigned int a, \ 327 unsigned int b, signed int c) \ 328 { \ 329 build_insn(buf, insn##op, a, b, c); \ 330 } 331 332 #define I_u2s3u1(op) \ 333 static inline void __init i##op(u32 **buf, unsigned int a, \ 334 signed int b, unsigned int c) \ 335 { \ 336 build_insn(buf, insn##op, c, a, b); \ 337 } 338 339 #define I_u2u1s3(op) \ 340 static inline void __init i##op(u32 **buf, unsigned int a, \ 341 unsigned int b, signed int c) \ 342 { \ 343 build_insn(buf, insn##op, b, a, c); \ 344 } 345 346 #define I_u1u2(op) \ 347 static inline void __init i##op(u32 **buf, unsigned int a, \ 348 unsigned int b) \ 349 { \ 350 build_insn(buf, insn##op, a, b); \ 351 } 352 353 #define I_u1s2(op) \ 354 static inline void __init i##op(u32 **buf, unsigned int a, \ 355 signed int b) \ 356 { \ 357 build_insn(buf, insn##op, a, b); \ 358 } 359 360 #define I_u1(op) \ 361 static inline void __init i##op(u32 **buf, unsigned int a) \ 362 { \ 363 build_insn(buf, insn##op, a); \ 364 } 365 366 #define I_0(op) \ 367 static inline void __init i##op(u32 **buf) \ 368 { \ 369 build_insn(buf, insn##op); \ 370 } 371 372 I_u2u1s3(_addiu); 373 I_u3u1u2(_addu); 374 I_u2u1u3(_andi); 375 I_u3u1u2(_and); 376 I_u1u2s3(_beq); 377 I_u1u2s3(_beql); 378 I_u1s2(_bgez); 379 I_u1s2(_bgezl); 380 I_u1s2(_bltz); 381 I_u1s2(_bltzl); 382 I_u1u2s3(_bne); 383 I_u1u2u3(_dmfc0); 384 I_u1u2u3(_dmtc0); 385 I_u2u1s3(_daddiu); 386 I_u3u1u2(_daddu); 387 I_u2u1u3(_dsll); 388 I_u2u1u3(_dsll32); 389 I_u2u1u3(_dsra); 390 I_u2u1u3(_dsrl); 391 I_u3u1u2(_dsubu); 392 I_0(_eret); 393 I_u1(_j); 394 I_u1(_jal); 395 I_u1(_jr); 396 I_u2s3u1(_ld); 397 I_u2s3u1(_ll); 398 I_u2s3u1(_lld); 399 I_u1s2(_lui); 400 I_u2s3u1(_lw); 401 I_u1u2u3(_mfc0); 402 I_u1u2u3(_mtc0); 403 I_u2u1u3(_ori); 404 I_0(_rfe); 405 I_u2s3u1(_sc); 406 I_u2s3u1(_scd); 407 I_u2s3u1(_sd); 408 I_u2u1u3(_sll); 409 I_u2u1u3(_sra); 410 I_u2u1u3(_srl); 411 I_u3u1u2(_subu); 412 I_u2s3u1(_sw); 413 I_0(_tlbp); 414 I_0(_tlbwi); 415 I_0(_tlbwr); 416 I_u3u1u2(_xor) 417 I_u2u1u3(_xori); 418 419 /* 420 * handling labels 421 */ 422 423 enum label_id { 424 label_invalid, 425 label_second_part, 426 label_leave, 427 label_vmalloc, 428 label_vmalloc_done, 429 label_tlbw_hazard, 430 label_split, 431 label_nopage_tlbl, 432 label_nopage_tlbs, 433 label_nopage_tlbm, 434 label_smp_pgtable_change, 435 label_r3000_write_probe_fail, 436 }; 437 438 struct label { 439 u32 *addr; 440 enum label_id lab; 441 }; 442 443 static __init void build_label(struct label **lab, u32 *addr, 444 enum label_id l) 445 { 446 (*lab)->addr = addr; 447 (*lab)->lab = l; 448 (*lab)++; 449 } 450 451 #define L_LA(lb) \ 452 static inline void l##lb(struct label **lab, u32 *addr) \ 453 { \ 454 build_label(lab, addr, label##lb); \ 455 } 456 457 L_LA(_second_part) 458 L_LA(_leave) 459 L_LA(_vmalloc) 460 L_LA(_vmalloc_done) 461 L_LA(_tlbw_hazard) 462 L_LA(_split) 463 L_LA(_nopage_tlbl) 464 L_LA(_nopage_tlbs) 465 L_LA(_nopage_tlbm) 466 L_LA(_smp_pgtable_change) 467 L_LA(_r3000_write_probe_fail) 468 469 /* convenience macros for instructions */ 470 #ifdef CONFIG_64BIT 471 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 472 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 473 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 474 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) 475 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) 476 # define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd) 477 # define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd) 478 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) 479 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) 480 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) 481 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) 482 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) 483 #else 484 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) 485 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) 486 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) 487 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) 488 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) 489 # define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd) 490 # define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd) 491 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) 492 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) 493 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) 494 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) 495 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) 496 #endif 497 498 #define i_b(buf, off) i_beq(buf, 0, 0, off) 499 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) 500 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) 501 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) 502 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) 503 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) 504 #define i_nop(buf) i_sll(buf, 0, 0, 0) 505 #define i_ssnop(buf) i_sll(buf, 0, 0, 1) 506 #define i_ehb(buf) i_sll(buf, 0, 0, 3) 507 508 #ifdef CONFIG_64BIT 509 static __init int __attribute__((unused)) in_compat_space_p(long addr) 510 { 511 /* Is this address in 32bit compat space? */ 512 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 513 } 514 515 static __init int __attribute__((unused)) rel_highest(long val) 516 { 517 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 518 } 519 520 static __init int __attribute__((unused)) rel_higher(long val) 521 { 522 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 523 } 524 #endif 525 526 static __init int rel_hi(long val) 527 { 528 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 529 } 530 531 static __init int rel_lo(long val) 532 { 533 return ((val & 0xffff) ^ 0x8000) - 0x8000; 534 } 535 536 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 537 { 538 #ifdef CONFIG_64BIT 539 if (!in_compat_space_p(addr)) { 540 i_lui(buf, rs, rel_highest(addr)); 541 if (rel_higher(addr)) 542 i_daddiu(buf, rs, rs, rel_higher(addr)); 543 if (rel_hi(addr)) { 544 i_dsll(buf, rs, rs, 16); 545 i_daddiu(buf, rs, rs, rel_hi(addr)); 546 i_dsll(buf, rs, rs, 16); 547 } else 548 i_dsll32(buf, rs, rs, 0); 549 } else 550 #endif 551 i_lui(buf, rs, rel_hi(addr)); 552 } 553 554 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs, 555 long addr) 556 { 557 i_LA_mostly(buf, rs, addr); 558 if (rel_lo(addr)) 559 i_ADDIU(buf, rs, rs, rel_lo(addr)); 560 } 561 562 /* 563 * handle relocations 564 */ 565 566 struct reloc { 567 u32 *addr; 568 unsigned int type; 569 enum label_id lab; 570 }; 571 572 static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 573 enum label_id l) 574 { 575 (*rel)->addr = addr; 576 (*rel)->type = R_MIPS_PC16; 577 (*rel)->lab = l; 578 (*rel)++; 579 } 580 581 static inline void __resolve_relocs(struct reloc *rel, struct label *lab) 582 { 583 long laddr = (long)lab->addr; 584 long raddr = (long)rel->addr; 585 586 switch (rel->type) { 587 case R_MIPS_PC16: 588 *rel->addr |= build_bimm(laddr - (raddr + 4)); 589 break; 590 591 default: 592 panic("Unsupported TLB synthesizer relocation %d", 593 rel->type); 594 } 595 } 596 597 static __init void resolve_relocs(struct reloc *rel, struct label *lab) 598 { 599 struct label *l; 600 601 for (; rel->lab != label_invalid; rel++) 602 for (l = lab; l->lab != label_invalid; l++) 603 if (rel->lab == l->lab) 604 __resolve_relocs(rel, l); 605 } 606 607 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 608 long off) 609 { 610 for (; rel->lab != label_invalid; rel++) 611 if (rel->addr >= first && rel->addr < end) 612 rel->addr += off; 613 } 614 615 static __init void move_labels(struct label *lab, u32 *first, u32 *end, 616 long off) 617 { 618 for (; lab->lab != label_invalid; lab++) 619 if (lab->addr >= first && lab->addr < end) 620 lab->addr += off; 621 } 622 623 static __init void copy_handler(struct reloc *rel, struct label *lab, 624 u32 *first, u32 *end, u32 *target) 625 { 626 long off = (long)(target - first); 627 628 memcpy(target, first, (end - first) * sizeof(u32)); 629 630 move_relocs(rel, first, end, off); 631 move_labels(lab, first, end, off); 632 } 633 634 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel, 635 u32 *addr) 636 { 637 for (; rel->lab != label_invalid; rel++) { 638 if (rel->addr == addr 639 && (rel->type == R_MIPS_PC16 640 || rel->type == R_MIPS_26)) 641 return 1; 642 } 643 644 return 0; 645 } 646 647 /* convenience functions for labeled branches */ 648 static void __init __attribute__((unused)) 649 il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 650 { 651 r_mips_pc16(r, *p, l); 652 i_bltz(p, reg, 0); 653 } 654 655 static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r, 656 enum label_id l) 657 { 658 r_mips_pc16(r, *p, l); 659 i_b(p, 0); 660 } 661 662 static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, 663 enum label_id l) 664 { 665 r_mips_pc16(r, *p, l); 666 i_beqz(p, reg, 0); 667 } 668 669 static void __init __attribute__((unused)) 670 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) 671 { 672 r_mips_pc16(r, *p, l); 673 i_beqzl(p, reg, 0); 674 } 675 676 static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, 677 enum label_id l) 678 { 679 r_mips_pc16(r, *p, l); 680 i_bnez(p, reg, 0); 681 } 682 683 static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, 684 enum label_id l) 685 { 686 r_mips_pc16(r, *p, l); 687 i_bgezl(p, reg, 0); 688 } 689 690 /* The only general purpose registers allowed in TLB handlers. */ 691 #define K0 26 692 #define K1 27 693 694 /* Some CP0 registers */ 695 #define C0_INDEX 0, 0 696 #define C0_ENTRYLO0 2, 0 697 #define C0_TCBIND 2, 2 698 #define C0_ENTRYLO1 3, 0 699 #define C0_CONTEXT 4, 0 700 #define C0_BADVADDR 8, 0 701 #define C0_ENTRYHI 10, 0 702 #define C0_EPC 14, 0 703 #define C0_XCONTEXT 20, 0 704 705 #ifdef CONFIG_64BIT 706 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 707 #else 708 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 709 #endif 710 711 /* The worst case length of the handler is around 18 instructions for 712 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 713 * Maximum space available is 32 instructions for R3000 and 64 714 * instructions for R4000. 715 * 716 * We deliberately chose a buffer size of 128, so we won't scribble 717 * over anything important on overflow before we panic. 718 */ 719 static __initdata u32 tlb_handler[128]; 720 721 /* simply assume worst case size for labels and relocs */ 722 static __initdata struct label labels[128]; 723 static __initdata struct reloc relocs[128]; 724 725 /* 726 * The R3000 TLB handler is simple. 727 */ 728 static void __init build_r3000_tlb_refill_handler(void) 729 { 730 long pgdc = (long)pgd_current; 731 u32 *p; 732 733 memset(tlb_handler, 0, sizeof(tlb_handler)); 734 p = tlb_handler; 735 736 i_mfc0(&p, K0, C0_BADVADDR); 737 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ 738 i_lw(&p, K1, rel_lo(pgdc), K1); 739 i_srl(&p, K0, K0, 22); /* load delay */ 740 i_sll(&p, K0, K0, 2); 741 i_addu(&p, K1, K1, K0); 742 i_mfc0(&p, K0, C0_CONTEXT); 743 i_lw(&p, K1, 0, K1); /* cp0 delay */ 744 i_andi(&p, K0, K0, 0xffc); /* load delay */ 745 i_addu(&p, K1, K1, K0); 746 i_lw(&p, K0, 0, K1); 747 i_nop(&p); /* load delay */ 748 i_mtc0(&p, K0, C0_ENTRYLO0); 749 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 750 i_tlbwr(&p); /* cp0 delay */ 751 i_jr(&p, K1); 752 i_rfe(&p); /* branch delay */ 753 754 if (p > tlb_handler + 32) 755 panic("TLB refill handler space exceeded"); 756 757 printk("Synthesized TLB refill handler (%u instructions).\n", 758 (unsigned int)(p - tlb_handler)); 759 #ifdef DEBUG_TLB 760 { 761 int i; 762 763 for (i = 0; i < (p - tlb_handler); i++) 764 printk("%08x\n", tlb_handler[i]); 765 } 766 #endif 767 768 memcpy((void *)ebase, tlb_handler, 0x80); 769 } 770 771 /* 772 * The R4000 TLB handler is much more complicated. We have two 773 * consecutive handler areas with 32 instructions space each. 774 * Since they aren't used at the same time, we can overflow in the 775 * other one.To keep things simple, we first assume linear space, 776 * then we relocate it to the final handler layout as needed. 777 */ 778 static __initdata u32 final_handler[64]; 779 780 /* 781 * Hazards 782 * 783 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 784 * 2. A timing hazard exists for the TLBP instruction. 785 * 786 * stalling_instruction 787 * TLBP 788 * 789 * The JTLB is being read for the TLBP throughout the stall generated by the 790 * previous instruction. This is not really correct as the stalling instruction 791 * can modify the address used to access the JTLB. The failure symptom is that 792 * the TLBP instruction will use an address created for the stalling instruction 793 * and not the address held in C0_ENHI and thus report the wrong results. 794 * 795 * The software work-around is to not allow the instruction preceding the TLBP 796 * to stall - make it an NOP or some other instruction guaranteed not to stall. 797 * 798 * Errata 2 will not be fixed. This errata is also on the R5000. 799 * 800 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 801 */ 802 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p) 803 { 804 switch (current_cpu_data.cputype) { 805 /* Found by experiment: R4600 v2.0 needs this, too. */ 806 case CPU_R4600: 807 case CPU_R5000: 808 case CPU_R5000A: 809 case CPU_NEVADA: 810 i_nop(p); 811 i_tlbp(p); 812 break; 813 814 default: 815 i_tlbp(p); 816 break; 817 } 818 } 819 820 /* 821 * Write random or indexed TLB entry, and care about the hazards from 822 * the preceeding mtc0 and for the following eret. 823 */ 824 enum tlb_write_entry { tlb_random, tlb_indexed }; 825 826 static __init void build_tlb_write_entry(u32 **p, struct label **l, 827 struct reloc **r, 828 enum tlb_write_entry wmode) 829 { 830 void(*tlbw)(u32 **) = NULL; 831 832 switch (wmode) { 833 case tlb_random: tlbw = i_tlbwr; break; 834 case tlb_indexed: tlbw = i_tlbwi; break; 835 } 836 837 switch (current_cpu_data.cputype) { 838 case CPU_R4000PC: 839 case CPU_R4000SC: 840 case CPU_R4000MC: 841 case CPU_R4400PC: 842 case CPU_R4400SC: 843 case CPU_R4400MC: 844 /* 845 * This branch uses up a mtc0 hazard nop slot and saves 846 * two nops after the tlbw instruction. 847 */ 848 il_bgezl(p, r, 0, label_tlbw_hazard); 849 tlbw(p); 850 l_tlbw_hazard(l, *p); 851 i_nop(p); 852 break; 853 854 case CPU_R4600: 855 case CPU_R4700: 856 case CPU_R5000: 857 case CPU_R5000A: 858 i_nop(p); 859 tlbw(p); 860 i_nop(p); 861 break; 862 863 case CPU_R4300: 864 case CPU_5KC: 865 case CPU_TX49XX: 866 case CPU_AU1000: 867 case CPU_AU1100: 868 case CPU_AU1500: 869 case CPU_AU1550: 870 case CPU_AU1200: 871 case CPU_PR4450: 872 i_nop(p); 873 tlbw(p); 874 break; 875 876 case CPU_R10000: 877 case CPU_R12000: 878 case CPU_R14000: 879 case CPU_4KC: 880 case CPU_SB1: 881 case CPU_SB1A: 882 case CPU_4KSC: 883 case CPU_20KC: 884 case CPU_25KF: 885 tlbw(p); 886 break; 887 888 case CPU_NEVADA: 889 i_nop(p); /* QED specifies 2 nops hazard */ 890 /* 891 * This branch uses up a mtc0 hazard nop slot and saves 892 * a nop after the tlbw instruction. 893 */ 894 il_bgezl(p, r, 0, label_tlbw_hazard); 895 tlbw(p); 896 l_tlbw_hazard(l, *p); 897 break; 898 899 case CPU_RM7000: 900 i_nop(p); 901 i_nop(p); 902 i_nop(p); 903 i_nop(p); 904 tlbw(p); 905 break; 906 907 case CPU_4KEC: 908 case CPU_24K: 909 case CPU_34K: 910 case CPU_74K: 911 i_ehb(p); 912 tlbw(p); 913 break; 914 915 case CPU_RM9000: 916 /* 917 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 918 * use of the JTLB for instructions should not occur for 4 919 * cpu cycles and use for data translations should not occur 920 * for 3 cpu cycles. 921 */ 922 i_ssnop(p); 923 i_ssnop(p); 924 i_ssnop(p); 925 i_ssnop(p); 926 tlbw(p); 927 i_ssnop(p); 928 i_ssnop(p); 929 i_ssnop(p); 930 i_ssnop(p); 931 break; 932 933 case CPU_VR4111: 934 case CPU_VR4121: 935 case CPU_VR4122: 936 case CPU_VR4181: 937 case CPU_VR4181A: 938 i_nop(p); 939 i_nop(p); 940 tlbw(p); 941 i_nop(p); 942 i_nop(p); 943 break; 944 945 case CPU_VR4131: 946 case CPU_VR4133: 947 case CPU_R5432: 948 i_nop(p); 949 i_nop(p); 950 tlbw(p); 951 break; 952 953 default: 954 panic("No TLB refill handler yet (CPU type: %d)", 955 current_cpu_data.cputype); 956 break; 957 } 958 } 959 960 #ifdef CONFIG_64BIT 961 /* 962 * TMP and PTR are scratch. 963 * TMP will be clobbered, PTR will hold the pmd entry. 964 */ 965 static __init void 966 build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 967 unsigned int tmp, unsigned int ptr) 968 { 969 long pgdc = (long)pgd_current; 970 971 /* 972 * The vmalloc handling is not in the hotpath. 973 */ 974 i_dmfc0(p, tmp, C0_BADVADDR); 975 il_bltz(p, r, tmp, label_vmalloc); 976 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 977 978 #ifdef CONFIG_SMP 979 # ifdef CONFIG_MIPS_MT_SMTC 980 /* 981 * SMTC uses TCBind value as "CPU" index 982 */ 983 i_mfc0(p, ptr, C0_TCBIND); 984 i_dsrl(p, ptr, ptr, 19); 985 # else 986 /* 987 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 988 * stored in CONTEXT. 989 */ 990 i_dmfc0(p, ptr, C0_CONTEXT); 991 i_dsrl(p, ptr, ptr, 23); 992 #endif 993 i_LA_mostly(p, tmp, pgdc); 994 i_daddu(p, ptr, ptr, tmp); 995 i_dmfc0(p, tmp, C0_BADVADDR); 996 i_ld(p, ptr, rel_lo(pgdc), ptr); 997 #else 998 i_LA_mostly(p, ptr, pgdc); 999 i_ld(p, ptr, rel_lo(pgdc), ptr); 1000 #endif 1001 1002 l_vmalloc_done(l, *p); 1003 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 1004 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 1005 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 1006 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1007 i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 1008 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 1009 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 1010 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 1011 } 1012 1013 /* 1014 * BVADDR is the faulting address, PTR is scratch. 1015 * PTR will hold the pgd for vmalloc. 1016 */ 1017 static __init void 1018 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1019 unsigned int bvaddr, unsigned int ptr) 1020 { 1021 long swpd = (long)swapper_pg_dir; 1022 1023 l_vmalloc(l, *p); 1024 i_LA(p, ptr, VMALLOC_START); 1025 i_dsubu(p, bvaddr, bvaddr, ptr); 1026 1027 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1028 il_b(p, r, label_vmalloc_done); 1029 i_lui(p, ptr, rel_hi(swpd)); 1030 } else { 1031 i_LA_mostly(p, ptr, swpd); 1032 il_b(p, r, label_vmalloc_done); 1033 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1034 } 1035 } 1036 1037 #else /* !CONFIG_64BIT */ 1038 1039 /* 1040 * TMP and PTR are scratch. 1041 * TMP will be clobbered, PTR will hold the pgd entry. 1042 */ 1043 static __init void __attribute__((unused)) 1044 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1045 { 1046 long pgdc = (long)pgd_current; 1047 1048 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 1049 #ifdef CONFIG_SMP 1050 #ifdef CONFIG_MIPS_MT_SMTC 1051 /* 1052 * SMTC uses TCBind value as "CPU" index 1053 */ 1054 i_mfc0(p, ptr, C0_TCBIND); 1055 i_LA_mostly(p, tmp, pgdc); 1056 i_srl(p, ptr, ptr, 19); 1057 #else 1058 /* 1059 * smp_processor_id() << 3 is stored in CONTEXT. 1060 */ 1061 i_mfc0(p, ptr, C0_CONTEXT); 1062 i_LA_mostly(p, tmp, pgdc); 1063 i_srl(p, ptr, ptr, 23); 1064 #endif 1065 i_addu(p, ptr, tmp, ptr); 1066 #else 1067 i_LA_mostly(p, ptr, pgdc); 1068 #endif 1069 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1070 i_lw(p, ptr, rel_lo(pgdc), ptr); 1071 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 1072 i_sll(p, tmp, tmp, PGD_T_LOG2); 1073 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1074 } 1075 1076 #endif /* !CONFIG_64BIT */ 1077 1078 static __init void build_adjust_context(u32 **p, unsigned int ctx) 1079 { 1080 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1081 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1082 1083 switch (current_cpu_data.cputype) { 1084 case CPU_VR41XX: 1085 case CPU_VR4111: 1086 case CPU_VR4121: 1087 case CPU_VR4122: 1088 case CPU_VR4131: 1089 case CPU_VR4181: 1090 case CPU_VR4181A: 1091 case CPU_VR4133: 1092 shift += 2; 1093 break; 1094 1095 default: 1096 break; 1097 } 1098 1099 if (shift) 1100 i_SRL(p, ctx, ctx, shift); 1101 i_andi(p, ctx, ctx, mask); 1102 } 1103 1104 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1105 { 1106 /* 1107 * Bug workaround for the Nevada. It seems as if under certain 1108 * circumstances the move from cp0_context might produce a 1109 * bogus result when the mfc0 instruction and its consumer are 1110 * in a different cacheline or a load instruction, probably any 1111 * memory reference, is between them. 1112 */ 1113 switch (current_cpu_data.cputype) { 1114 case CPU_NEVADA: 1115 i_LW(p, ptr, 0, ptr); 1116 GET_CONTEXT(p, tmp); /* get context reg */ 1117 break; 1118 1119 default: 1120 GET_CONTEXT(p, tmp); /* get context reg */ 1121 i_LW(p, ptr, 0, ptr); 1122 break; 1123 } 1124 1125 build_adjust_context(p, tmp); 1126 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1127 } 1128 1129 static __init void build_update_entries(u32 **p, unsigned int tmp, 1130 unsigned int ptep) 1131 { 1132 /* 1133 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1134 * Kernel is a special case. Only a few CPUs use it. 1135 */ 1136 #ifdef CONFIG_64BIT_PHYS_ADDR 1137 if (cpu_has_64bits) { 1138 i_ld(p, tmp, 0, ptep); /* get even pte */ 1139 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1140 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ 1141 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1142 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ 1143 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1144 } else { 1145 int pte_off_even = sizeof(pte_t) / 2; 1146 int pte_off_odd = pte_off_even + sizeof(pte_t); 1147 1148 /* The pte entries are pre-shifted */ 1149 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1150 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1151 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1152 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1153 } 1154 #else 1155 i_LW(p, tmp, 0, ptep); /* get even pte */ 1156 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1157 if (r45k_bvahwbug()) 1158 build_tlb_probe_entry(p); 1159 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ 1160 if (r4k_250MHZhwbug()) 1161 i_mtc0(p, 0, C0_ENTRYLO0); 1162 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ 1163 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ 1164 if (r45k_bvahwbug()) 1165 i_mfc0(p, tmp, C0_INDEX); 1166 if (r4k_250MHZhwbug()) 1167 i_mtc0(p, 0, C0_ENTRYLO1); 1168 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ 1169 #endif 1170 } 1171 1172 static void __init build_r4000_tlb_refill_handler(void) 1173 { 1174 u32 *p = tlb_handler; 1175 struct label *l = labels; 1176 struct reloc *r = relocs; 1177 u32 *f; 1178 unsigned int final_len; 1179 1180 memset(tlb_handler, 0, sizeof(tlb_handler)); 1181 memset(labels, 0, sizeof(labels)); 1182 memset(relocs, 0, sizeof(relocs)); 1183 memset(final_handler, 0, sizeof(final_handler)); 1184 1185 /* 1186 * create the plain linear handler 1187 */ 1188 if (bcm1250_m3_war()) { 1189 i_MFC0(&p, K0, C0_BADVADDR); 1190 i_MFC0(&p, K1, C0_ENTRYHI); 1191 i_xor(&p, K0, K0, K1); 1192 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1193 il_bnez(&p, &r, K0, label_leave); 1194 /* No need for i_nop */ 1195 } 1196 1197 #ifdef CONFIG_64BIT 1198 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1199 #else 1200 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1201 #endif 1202 1203 build_get_ptep(&p, K0, K1); 1204 build_update_entries(&p, K0, K1); 1205 build_tlb_write_entry(&p, &l, &r, tlb_random); 1206 l_leave(&l, p); 1207 i_eret(&p); /* return from trap */ 1208 1209 #ifdef CONFIG_64BIT 1210 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1211 #endif 1212 1213 /* 1214 * Overflow check: For the 64bit handler, we need at least one 1215 * free instruction slot for the wrap-around branch. In worst 1216 * case, if the intended insertion point is a delay slot, we 1217 * need three, with the the second nop'ed and the third being 1218 * unused. 1219 */ 1220 #ifdef CONFIG_32BIT 1221 if ((p - tlb_handler) > 64) 1222 panic("TLB refill handler space exceeded"); 1223 #else 1224 if (((p - tlb_handler) > 63) 1225 || (((p - tlb_handler) > 61) 1226 && insn_has_bdelay(relocs, tlb_handler + 29))) 1227 panic("TLB refill handler space exceeded"); 1228 #endif 1229 1230 /* 1231 * Now fold the handler in the TLB refill handler space. 1232 */ 1233 #ifdef CONFIG_32BIT 1234 f = final_handler; 1235 /* Simplest case, just copy the handler. */ 1236 copy_handler(relocs, labels, tlb_handler, p, f); 1237 final_len = p - tlb_handler; 1238 #else /* CONFIG_64BIT */ 1239 f = final_handler + 32; 1240 if ((p - tlb_handler) <= 32) { 1241 /* Just copy the handler. */ 1242 copy_handler(relocs, labels, tlb_handler, p, f); 1243 final_len = p - tlb_handler; 1244 } else { 1245 u32 *split = tlb_handler + 30; 1246 1247 /* 1248 * Find the split point. 1249 */ 1250 if (insn_has_bdelay(relocs, split - 1)) 1251 split--; 1252 1253 /* Copy first part of the handler. */ 1254 copy_handler(relocs, labels, tlb_handler, split, f); 1255 f += split - tlb_handler; 1256 1257 /* Insert branch. */ 1258 l_split(&l, final_handler); 1259 il_b(&f, &r, label_split); 1260 if (insn_has_bdelay(relocs, split)) 1261 i_nop(&f); 1262 else { 1263 copy_handler(relocs, labels, split, split + 1, f); 1264 move_labels(labels, f, f + 1, -1); 1265 f++; 1266 split++; 1267 } 1268 1269 /* Copy the rest of the handler. */ 1270 copy_handler(relocs, labels, split, p, final_handler); 1271 final_len = (f - (final_handler + 32)) + (p - split); 1272 } 1273 #endif /* CONFIG_64BIT */ 1274 1275 resolve_relocs(relocs, labels); 1276 printk("Synthesized TLB refill handler (%u instructions).\n", 1277 final_len); 1278 1279 #ifdef DEBUG_TLB 1280 { 1281 int i; 1282 1283 f = final_handler; 1284 #ifdef CONFIG_64BIT 1285 if (final_len > 32) 1286 final_len = 64; 1287 else 1288 f = final_handler + 32; 1289 #endif /* CONFIG_64BIT */ 1290 for (i = 0; i < final_len; i++) 1291 printk("%08x\n", f[i]); 1292 } 1293 #endif 1294 1295 memcpy((void *)ebase, final_handler, 0x100); 1296 } 1297 1298 /* 1299 * TLB load/store/modify handlers. 1300 * 1301 * Only the fastpath gets synthesized at runtime, the slowpath for 1302 * do_page_fault remains normal asm. 1303 */ 1304 extern void tlb_do_page_fault_0(void); 1305 extern void tlb_do_page_fault_1(void); 1306 1307 #define __tlb_handler_align \ 1308 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) 1309 1310 /* 1311 * 128 instructions for the fastpath handler is generous and should 1312 * never be exceeded. 1313 */ 1314 #define FASTPATH_SIZE 128 1315 1316 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1317 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1318 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1319 1320 static void __init 1321 iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1322 { 1323 #ifdef CONFIG_SMP 1324 # ifdef CONFIG_64BIT_PHYS_ADDR 1325 if (cpu_has_64bits) 1326 i_lld(p, pte, 0, ptr); 1327 else 1328 # endif 1329 i_LL(p, pte, 0, ptr); 1330 #else 1331 # ifdef CONFIG_64BIT_PHYS_ADDR 1332 if (cpu_has_64bits) 1333 i_ld(p, pte, 0, ptr); 1334 else 1335 # endif 1336 i_LW(p, pte, 0, ptr); 1337 #endif 1338 } 1339 1340 static void __init 1341 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, 1342 unsigned int mode) 1343 { 1344 #ifdef CONFIG_64BIT_PHYS_ADDR 1345 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1346 #endif 1347 1348 i_ori(p, pte, pte, mode); 1349 #ifdef CONFIG_SMP 1350 # ifdef CONFIG_64BIT_PHYS_ADDR 1351 if (cpu_has_64bits) 1352 i_scd(p, pte, 0, ptr); 1353 else 1354 # endif 1355 i_SC(p, pte, 0, ptr); 1356 1357 if (r10000_llsc_war()) 1358 il_beqzl(p, r, pte, label_smp_pgtable_change); 1359 else 1360 il_beqz(p, r, pte, label_smp_pgtable_change); 1361 1362 # ifdef CONFIG_64BIT_PHYS_ADDR 1363 if (!cpu_has_64bits) { 1364 /* no i_nop needed */ 1365 i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1366 i_ori(p, pte, pte, hwmode); 1367 i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1368 il_beqz(p, r, pte, label_smp_pgtable_change); 1369 /* no i_nop needed */ 1370 i_lw(p, pte, 0, ptr); 1371 } else 1372 i_nop(p); 1373 # else 1374 i_nop(p); 1375 # endif 1376 #else 1377 # ifdef CONFIG_64BIT_PHYS_ADDR 1378 if (cpu_has_64bits) 1379 i_sd(p, pte, 0, ptr); 1380 else 1381 # endif 1382 i_SW(p, pte, 0, ptr); 1383 1384 # ifdef CONFIG_64BIT_PHYS_ADDR 1385 if (!cpu_has_64bits) { 1386 i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1387 i_ori(p, pte, pte, hwmode); 1388 i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1389 i_lw(p, pte, 0, ptr); 1390 } 1391 # endif 1392 #endif 1393 } 1394 1395 /* 1396 * Check if PTE is present, if not then jump to LABEL. PTR points to 1397 * the page table where this PTE is located, PTE will be re-loaded 1398 * with it's original value. 1399 */ 1400 static void __init 1401 build_pte_present(u32 **p, struct label **l, struct reloc **r, 1402 unsigned int pte, unsigned int ptr, enum label_id lid) 1403 { 1404 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1405 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1406 il_bnez(p, r, pte, lid); 1407 iPTE_LW(p, l, pte, ptr); 1408 } 1409 1410 /* Make PTE valid, store result in PTR. */ 1411 static void __init 1412 build_make_valid(u32 **p, struct reloc **r, unsigned int pte, 1413 unsigned int ptr) 1414 { 1415 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1416 1417 iPTE_SW(p, r, pte, ptr, mode); 1418 } 1419 1420 /* 1421 * Check if PTE can be written to, if not branch to LABEL. Regardless 1422 * restore PTE with value from PTR when done. 1423 */ 1424 static void __init 1425 build_pte_writable(u32 **p, struct label **l, struct reloc **r, 1426 unsigned int pte, unsigned int ptr, enum label_id lid) 1427 { 1428 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1429 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1430 il_bnez(p, r, pte, lid); 1431 iPTE_LW(p, l, pte, ptr); 1432 } 1433 1434 /* Make PTE writable, update software status bits as well, then store 1435 * at PTR. 1436 */ 1437 static void __init 1438 build_make_write(u32 **p, struct reloc **r, unsigned int pte, 1439 unsigned int ptr) 1440 { 1441 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1442 | _PAGE_DIRTY); 1443 1444 iPTE_SW(p, r, pte, ptr, mode); 1445 } 1446 1447 /* 1448 * Check if PTE can be modified, if not branch to LABEL. Regardless 1449 * restore PTE with value from PTR when done. 1450 */ 1451 static void __init 1452 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, 1453 unsigned int pte, unsigned int ptr, enum label_id lid) 1454 { 1455 i_andi(p, pte, pte, _PAGE_WRITE); 1456 il_beqz(p, r, pte, lid); 1457 iPTE_LW(p, l, pte, ptr); 1458 } 1459 1460 /* 1461 * R3000 style TLB load/store/modify handlers. 1462 */ 1463 1464 /* 1465 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1466 * Then it returns. 1467 */ 1468 static void __init 1469 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1470 { 1471 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1472 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1473 i_tlbwi(p); 1474 i_jr(p, tmp); 1475 i_rfe(p); /* branch delay */ 1476 } 1477 1478 /* 1479 * This places the pte into ENTRYLO0 and writes it with tlbwi 1480 * or tlbwr as appropriate. This is because the index register 1481 * may have the probe fail bit set as a result of a trap on a 1482 * kseg2 access, i.e. without refill. Then it returns. 1483 */ 1484 static void __init 1485 build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, 1486 unsigned int pte, unsigned int tmp) 1487 { 1488 i_mfc0(p, tmp, C0_INDEX); 1489 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1490 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1491 i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1492 i_tlbwi(p); /* cp0 delay */ 1493 i_jr(p, tmp); 1494 i_rfe(p); /* branch delay */ 1495 l_r3000_write_probe_fail(l, *p); 1496 i_tlbwr(p); /* cp0 delay */ 1497 i_jr(p, tmp); 1498 i_rfe(p); /* branch delay */ 1499 } 1500 1501 static void __init 1502 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1503 unsigned int ptr) 1504 { 1505 long pgdc = (long)pgd_current; 1506 1507 i_mfc0(p, pte, C0_BADVADDR); 1508 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ 1509 i_lw(p, ptr, rel_lo(pgdc), ptr); 1510 i_srl(p, pte, pte, 22); /* load delay */ 1511 i_sll(p, pte, pte, 2); 1512 i_addu(p, ptr, ptr, pte); 1513 i_mfc0(p, pte, C0_CONTEXT); 1514 i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1515 i_andi(p, pte, pte, 0xffc); /* load delay */ 1516 i_addu(p, ptr, ptr, pte); 1517 i_lw(p, pte, 0, ptr); 1518 i_tlbp(p); /* load delay */ 1519 } 1520 1521 static void __init build_r3000_tlb_load_handler(void) 1522 { 1523 u32 *p = handle_tlbl; 1524 struct label *l = labels; 1525 struct reloc *r = relocs; 1526 1527 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1528 memset(labels, 0, sizeof(labels)); 1529 memset(relocs, 0, sizeof(relocs)); 1530 1531 build_r3000_tlbchange_handler_head(&p, K0, K1); 1532 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1533 i_nop(&p); /* load delay */ 1534 build_make_valid(&p, &r, K0, K1); 1535 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1536 1537 l_nopage_tlbl(&l, p); 1538 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1539 i_nop(&p); 1540 1541 if ((p - handle_tlbl) > FASTPATH_SIZE) 1542 panic("TLB load handler fastpath space exceeded"); 1543 1544 resolve_relocs(relocs, labels); 1545 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1546 (unsigned int)(p - handle_tlbl)); 1547 1548 #ifdef DEBUG_TLB 1549 { 1550 int i; 1551 1552 for (i = 0; i < (p - handle_tlbl); i++) 1553 printk("%08x\n", handle_tlbl[i]); 1554 } 1555 #endif 1556 } 1557 1558 static void __init build_r3000_tlb_store_handler(void) 1559 { 1560 u32 *p = handle_tlbs; 1561 struct label *l = labels; 1562 struct reloc *r = relocs; 1563 1564 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1565 memset(labels, 0, sizeof(labels)); 1566 memset(relocs, 0, sizeof(relocs)); 1567 1568 build_r3000_tlbchange_handler_head(&p, K0, K1); 1569 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1570 i_nop(&p); /* load delay */ 1571 build_make_write(&p, &r, K0, K1); 1572 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1573 1574 l_nopage_tlbs(&l, p); 1575 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1576 i_nop(&p); 1577 1578 if ((p - handle_tlbs) > FASTPATH_SIZE) 1579 panic("TLB store handler fastpath space exceeded"); 1580 1581 resolve_relocs(relocs, labels); 1582 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1583 (unsigned int)(p - handle_tlbs)); 1584 1585 #ifdef DEBUG_TLB 1586 { 1587 int i; 1588 1589 for (i = 0; i < (p - handle_tlbs); i++) 1590 printk("%08x\n", handle_tlbs[i]); 1591 } 1592 #endif 1593 } 1594 1595 static void __init build_r3000_tlb_modify_handler(void) 1596 { 1597 u32 *p = handle_tlbm; 1598 struct label *l = labels; 1599 struct reloc *r = relocs; 1600 1601 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1602 memset(labels, 0, sizeof(labels)); 1603 memset(relocs, 0, sizeof(relocs)); 1604 1605 build_r3000_tlbchange_handler_head(&p, K0, K1); 1606 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1607 i_nop(&p); /* load delay */ 1608 build_make_write(&p, &r, K0, K1); 1609 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1610 1611 l_nopage_tlbm(&l, p); 1612 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1613 i_nop(&p); 1614 1615 if ((p - handle_tlbm) > FASTPATH_SIZE) 1616 panic("TLB modify handler fastpath space exceeded"); 1617 1618 resolve_relocs(relocs, labels); 1619 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1620 (unsigned int)(p - handle_tlbm)); 1621 1622 #ifdef DEBUG_TLB 1623 { 1624 int i; 1625 1626 for (i = 0; i < (p - handle_tlbm); i++) 1627 printk("%08x\n", handle_tlbm[i]); 1628 } 1629 #endif 1630 } 1631 1632 /* 1633 * R4000 style TLB load/store/modify handlers. 1634 */ 1635 static void __init 1636 build_r4000_tlbchange_handler_head(u32 **p, struct label **l, 1637 struct reloc **r, unsigned int pte, 1638 unsigned int ptr) 1639 { 1640 #ifdef CONFIG_64BIT 1641 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1642 #else 1643 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1644 #endif 1645 1646 i_MFC0(p, pte, C0_BADVADDR); 1647 i_LW(p, ptr, 0, ptr); 1648 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1649 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1650 i_ADDU(p, ptr, ptr, pte); 1651 1652 #ifdef CONFIG_SMP 1653 l_smp_pgtable_change(l, *p); 1654 # endif 1655 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1656 build_tlb_probe_entry(p); 1657 } 1658 1659 static void __init 1660 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, 1661 struct reloc **r, unsigned int tmp, 1662 unsigned int ptr) 1663 { 1664 i_ori(p, ptr, ptr, sizeof(pte_t)); 1665 i_xori(p, ptr, ptr, sizeof(pte_t)); 1666 build_update_entries(p, tmp, ptr); 1667 build_tlb_write_entry(p, l, r, tlb_indexed); 1668 l_leave(l, *p); 1669 i_eret(p); /* return from trap */ 1670 1671 #ifdef CONFIG_64BIT 1672 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1673 #endif 1674 } 1675 1676 static void __init build_r4000_tlb_load_handler(void) 1677 { 1678 u32 *p = handle_tlbl; 1679 struct label *l = labels; 1680 struct reloc *r = relocs; 1681 1682 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1683 memset(labels, 0, sizeof(labels)); 1684 memset(relocs, 0, sizeof(relocs)); 1685 1686 if (bcm1250_m3_war()) { 1687 i_MFC0(&p, K0, C0_BADVADDR); 1688 i_MFC0(&p, K1, C0_ENTRYHI); 1689 i_xor(&p, K0, K0, K1); 1690 i_SRL(&p, K0, K0, PAGE_SHIFT + 1); 1691 il_bnez(&p, &r, K0, label_leave); 1692 /* No need for i_nop */ 1693 } 1694 1695 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1696 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1697 build_make_valid(&p, &r, K0, K1); 1698 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1699 1700 l_nopage_tlbl(&l, p); 1701 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1702 i_nop(&p); 1703 1704 if ((p - handle_tlbl) > FASTPATH_SIZE) 1705 panic("TLB load handler fastpath space exceeded"); 1706 1707 resolve_relocs(relocs, labels); 1708 printk("Synthesized TLB load handler fastpath (%u instructions).\n", 1709 (unsigned int)(p - handle_tlbl)); 1710 1711 #ifdef DEBUG_TLB 1712 { 1713 int i; 1714 1715 for (i = 0; i < (p - handle_tlbl); i++) 1716 printk("%08x\n", handle_tlbl[i]); 1717 } 1718 #endif 1719 } 1720 1721 static void __init build_r4000_tlb_store_handler(void) 1722 { 1723 u32 *p = handle_tlbs; 1724 struct label *l = labels; 1725 struct reloc *r = relocs; 1726 1727 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1728 memset(labels, 0, sizeof(labels)); 1729 memset(relocs, 0, sizeof(relocs)); 1730 1731 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1732 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1733 build_make_write(&p, &r, K0, K1); 1734 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1735 1736 l_nopage_tlbs(&l, p); 1737 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1738 i_nop(&p); 1739 1740 if ((p - handle_tlbs) > FASTPATH_SIZE) 1741 panic("TLB store handler fastpath space exceeded"); 1742 1743 resolve_relocs(relocs, labels); 1744 printk("Synthesized TLB store handler fastpath (%u instructions).\n", 1745 (unsigned int)(p - handle_tlbs)); 1746 1747 #ifdef DEBUG_TLB 1748 { 1749 int i; 1750 1751 for (i = 0; i < (p - handle_tlbs); i++) 1752 printk("%08x\n", handle_tlbs[i]); 1753 } 1754 #endif 1755 } 1756 1757 static void __init build_r4000_tlb_modify_handler(void) 1758 { 1759 u32 *p = handle_tlbm; 1760 struct label *l = labels; 1761 struct reloc *r = relocs; 1762 1763 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1764 memset(labels, 0, sizeof(labels)); 1765 memset(relocs, 0, sizeof(relocs)); 1766 1767 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1768 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1769 /* Present and writable bits set, set accessed and dirty bits. */ 1770 build_make_write(&p, &r, K0, K1); 1771 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1772 1773 l_nopage_tlbm(&l, p); 1774 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1775 i_nop(&p); 1776 1777 if ((p - handle_tlbm) > FASTPATH_SIZE) 1778 panic("TLB modify handler fastpath space exceeded"); 1779 1780 resolve_relocs(relocs, labels); 1781 printk("Synthesized TLB modify handler fastpath (%u instructions).\n", 1782 (unsigned int)(p - handle_tlbm)); 1783 1784 #ifdef DEBUG_TLB 1785 { 1786 int i; 1787 1788 for (i = 0; i < (p - handle_tlbm); i++) 1789 printk("%08x\n", handle_tlbm[i]); 1790 } 1791 #endif 1792 } 1793 1794 void __init build_tlb_refill_handler(void) 1795 { 1796 /* 1797 * The refill handler is generated per-CPU, multi-node systems 1798 * may have local storage for it. The other handlers are only 1799 * needed once. 1800 */ 1801 static int run_once = 0; 1802 1803 switch (current_cpu_data.cputype) { 1804 case CPU_R2000: 1805 case CPU_R3000: 1806 case CPU_R3000A: 1807 case CPU_R3081E: 1808 case CPU_TX3912: 1809 case CPU_TX3922: 1810 case CPU_TX3927: 1811 build_r3000_tlb_refill_handler(); 1812 if (!run_once) { 1813 build_r3000_tlb_load_handler(); 1814 build_r3000_tlb_store_handler(); 1815 build_r3000_tlb_modify_handler(); 1816 run_once++; 1817 } 1818 break; 1819 1820 case CPU_R6000: 1821 case CPU_R6000A: 1822 panic("No R6000 TLB refill handler yet"); 1823 break; 1824 1825 case CPU_R8000: 1826 panic("No R8000 TLB refill handler yet"); 1827 break; 1828 1829 default: 1830 build_r4000_tlb_refill_handler(); 1831 if (!run_once) { 1832 build_r4000_tlb_load_handler(); 1833 build_r4000_tlb_store_handler(); 1834 build_r4000_tlb_modify_handler(); 1835 run_once++; 1836 } 1837 } 1838 } 1839 1840 void __init flush_tlb_handlers(void) 1841 { 1842 flush_icache_range((unsigned long)handle_tlbl, 1843 (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 1844 flush_icache_range((unsigned long)handle_tlbs, 1845 (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 1846 flush_icache_range((unsigned long)handle_tlbm, 1847 (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 1848 } 1849