1287e3f3fSJohn Crispin /* 2287e3f3fSJohn Crispin * This program is free software; you can redistribute it and/or modify it 3287e3f3fSJohn Crispin * under the terms of the GNU General Public License version 2 as published 4287e3f3fSJohn Crispin * by the Free Software Foundation. 5287e3f3fSJohn Crispin * 6287e3f3fSJohn Crispin * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org> 7287e3f3fSJohn Crispin */ 8287e3f3fSJohn Crispin 9287e3f3fSJohn Crispin #include <linux/ioport.h> 10287e3f3fSJohn Crispin #include <linux/export.h> 11287e3f3fSJohn Crispin #include <linux/clkdev.h> 12287e3f3fSJohn Crispin #include <linux/of.h> 13287e3f3fSJohn Crispin #include <linux/of_platform.h> 14287e3f3fSJohn Crispin #include <linux/of_address.h> 15287e3f3fSJohn Crispin 16287e3f3fSJohn Crispin #include <lantiq_soc.h> 17287e3f3fSJohn Crispin 18287e3f3fSJohn Crispin #include "../clk.h" 19287e3f3fSJohn Crispin #include "../prom.h" 20287e3f3fSJohn Crispin 21287e3f3fSJohn Crispin /* clock control register */ 22287e3f3fSJohn Crispin #define CGU_IFCCR 0x0018 23e29b72f5SJohn Crispin #define CGU_IFCCR_VR9 0x0024 24287e3f3fSJohn Crispin /* system clock register */ 25287e3f3fSJohn Crispin #define CGU_SYS 0x0010 26287e3f3fSJohn Crispin /* pci control register */ 27287e3f3fSJohn Crispin #define CGU_PCICR 0x0034 28e29b72f5SJohn Crispin #define CGU_PCICR_VR9 0x0038 29287e3f3fSJohn Crispin /* ephy configuration register */ 30287e3f3fSJohn Crispin #define CGU_EPHY 0x10 31287e3f3fSJohn Crispin /* power control register */ 32287e3f3fSJohn Crispin #define PMU_PWDCR 0x1C 33287e3f3fSJohn Crispin /* power status register */ 34287e3f3fSJohn Crispin #define PMU_PWDSR 0x20 35287e3f3fSJohn Crispin /* power control register */ 36287e3f3fSJohn Crispin #define PMU_PWDCR1 0x24 37287e3f3fSJohn Crispin /* power status register */ 38287e3f3fSJohn Crispin #define PMU_PWDSR1 0x28 39287e3f3fSJohn Crispin /* power control register */ 40287e3f3fSJohn Crispin #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) 41287e3f3fSJohn Crispin /* power status register */ 42287e3f3fSJohn Crispin #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) 43287e3f3fSJohn Crispin 44287e3f3fSJohn Crispin /* clock gates that we can en/disable */ 45287e3f3fSJohn Crispin #define PMU_USB0_P BIT(0) 46287e3f3fSJohn Crispin #define PMU_PCI BIT(4) 47009d6914SJohn Crispin #define PMU_DMA BIT(5) 48287e3f3fSJohn Crispin #define PMU_USB0 BIT(6) 49287e3f3fSJohn Crispin #define PMU_ASC0 BIT(7) 50287e3f3fSJohn Crispin #define PMU_EPHY BIT(7) /* ase */ 51287e3f3fSJohn Crispin #define PMU_SPI BIT(8) 52287e3f3fSJohn Crispin #define PMU_DFE BIT(9) 53287e3f3fSJohn Crispin #define PMU_EBU BIT(10) 54287e3f3fSJohn Crispin #define PMU_STP BIT(11) 55009d6914SJohn Crispin #define PMU_GPT BIT(12) 56287e3f3fSJohn Crispin #define PMU_AHBS BIT(13) /* vr9 */ 57009d6914SJohn Crispin #define PMU_FPI BIT(14) 58287e3f3fSJohn Crispin #define PMU_AHBM BIT(15) 59287e3f3fSJohn Crispin #define PMU_ASC1 BIT(17) 60287e3f3fSJohn Crispin #define PMU_PPE_QSB BIT(18) 61287e3f3fSJohn Crispin #define PMU_PPE_SLL01 BIT(19) 62287e3f3fSJohn Crispin #define PMU_PPE_TC BIT(21) 63287e3f3fSJohn Crispin #define PMU_PPE_EMA BIT(22) 64287e3f3fSJohn Crispin #define PMU_PPE_DPLUM BIT(23) 65287e3f3fSJohn Crispin #define PMU_PPE_DPLUS BIT(24) 66287e3f3fSJohn Crispin #define PMU_USB1_P BIT(26) 67287e3f3fSJohn Crispin #define PMU_USB1 BIT(27) 68009d6914SJohn Crispin #define PMU_SWITCH BIT(28) 69287e3f3fSJohn Crispin #define PMU_PPE_TOP BIT(29) 70287e3f3fSJohn Crispin #define PMU_GPHY BIT(30) 71287e3f3fSJohn Crispin #define PMU_PCIE_CLK BIT(31) 72287e3f3fSJohn Crispin 73287e3f3fSJohn Crispin #define PMU1_PCIE_PHY BIT(0) 74287e3f3fSJohn Crispin #define PMU1_PCIE_CTL BIT(1) 75287e3f3fSJohn Crispin #define PMU1_PCIE_PDI BIT(4) 76287e3f3fSJohn Crispin #define PMU1_PCIE_MSI BIT(5) 77287e3f3fSJohn Crispin 78287e3f3fSJohn Crispin #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y)) 79287e3f3fSJohn Crispin #define pmu_r32(x) ltq_r32(pmu_membase + (x)) 80287e3f3fSJohn Crispin 81287e3f3fSJohn Crispin static void __iomem *pmu_membase; 82287e3f3fSJohn Crispin void __iomem *ltq_cgu_membase; 83287e3f3fSJohn Crispin void __iomem *ltq_ebu_membase; 84287e3f3fSJohn Crispin 85e29b72f5SJohn Crispin static u32 ifccr = CGU_IFCCR; 86e29b72f5SJohn Crispin static u32 pcicr = CGU_PCICR; 87e29b72f5SJohn Crispin 88287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */ 89287e3f3fSJohn Crispin void ltq_pmu_enable(unsigned int module) 90287e3f3fSJohn Crispin { 91287e3f3fSJohn Crispin int err = 1000000; 92287e3f3fSJohn Crispin 93287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR); 94287e3f3fSJohn Crispin do {} while (--err && (pmu_r32(PMU_PWDSR) & module)); 95287e3f3fSJohn Crispin 96287e3f3fSJohn Crispin if (!err) 97287e3f3fSJohn Crispin panic("activating PMU module failed!"); 98287e3f3fSJohn Crispin } 99287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_enable); 100287e3f3fSJohn Crispin 101287e3f3fSJohn Crispin /* legacy function kept alive to ease clkdev transition */ 102287e3f3fSJohn Crispin void ltq_pmu_disable(unsigned int module) 103287e3f3fSJohn Crispin { 104287e3f3fSJohn Crispin pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR); 105287e3f3fSJohn Crispin } 106287e3f3fSJohn Crispin EXPORT_SYMBOL(ltq_pmu_disable); 107287e3f3fSJohn Crispin 108287e3f3fSJohn Crispin /* enable a hw clock */ 109287e3f3fSJohn Crispin static int cgu_enable(struct clk *clk) 110287e3f3fSJohn Crispin { 111e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); 112287e3f3fSJohn Crispin return 0; 113287e3f3fSJohn Crispin } 114287e3f3fSJohn Crispin 115287e3f3fSJohn Crispin /* disable a hw clock */ 116287e3f3fSJohn Crispin static void cgu_disable(struct clk *clk) 117287e3f3fSJohn Crispin { 118e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); 119287e3f3fSJohn Crispin } 120287e3f3fSJohn Crispin 121287e3f3fSJohn Crispin /* enable a clock gate */ 122287e3f3fSJohn Crispin static int pmu_enable(struct clk *clk) 123287e3f3fSJohn Crispin { 124287e3f3fSJohn Crispin int retry = 1000000; 125287e3f3fSJohn Crispin 126287e3f3fSJohn Crispin pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, 127287e3f3fSJohn Crispin PWDCR(clk->module)); 128287e3f3fSJohn Crispin do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); 129287e3f3fSJohn Crispin 130287e3f3fSJohn Crispin if (!retry) 131287e3f3fSJohn Crispin panic("activating PMU module failed!\n"); 132287e3f3fSJohn Crispin 133287e3f3fSJohn Crispin return 0; 134287e3f3fSJohn Crispin } 135287e3f3fSJohn Crispin 136287e3f3fSJohn Crispin /* disable a clock gate */ 137287e3f3fSJohn Crispin static void pmu_disable(struct clk *clk) 138287e3f3fSJohn Crispin { 139287e3f3fSJohn Crispin pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, 140287e3f3fSJohn Crispin PWDCR(clk->module)); 141287e3f3fSJohn Crispin } 142287e3f3fSJohn Crispin 143287e3f3fSJohn Crispin /* the pci enable helper */ 144287e3f3fSJohn Crispin static int pci_enable(struct clk *clk) 145287e3f3fSJohn Crispin { 146e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr); 147287e3f3fSJohn Crispin /* set bus clock speed */ 148f40e1f9dSJohn Crispin if (of_machine_is_compatible("lantiq,ar9") || 149f40e1f9dSJohn Crispin of_machine_is_compatible("lantiq,vr9")) { 150e29b72f5SJohn Crispin val &= ~0x1f00000; 151287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M) 152e29b72f5SJohn Crispin val |= 0xe00000; 153287e3f3fSJohn Crispin else 154e29b72f5SJohn Crispin val |= 0x700000; /* 62.5M */ 155287e3f3fSJohn Crispin } else { 156e29b72f5SJohn Crispin val &= ~0xf00000; 157287e3f3fSJohn Crispin if (clk->rate == CLOCK_33M) 158e29b72f5SJohn Crispin val |= 0x800000; 159287e3f3fSJohn Crispin else 160e29b72f5SJohn Crispin val |= 0x400000; /* 62.5M */ 161287e3f3fSJohn Crispin } 162e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr); 163287e3f3fSJohn Crispin pmu_enable(clk); 164287e3f3fSJohn Crispin return 0; 165287e3f3fSJohn Crispin } 166287e3f3fSJohn Crispin 167287e3f3fSJohn Crispin /* enable the external clock as a source */ 168287e3f3fSJohn Crispin static int pci_ext_enable(struct clk *clk) 169287e3f3fSJohn Crispin { 170e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr); 171e29b72f5SJohn Crispin ltq_cgu_w32((1 << 30), pcicr); 172287e3f3fSJohn Crispin return 0; 173287e3f3fSJohn Crispin } 174287e3f3fSJohn Crispin 175287e3f3fSJohn Crispin /* disable the external clock as a source */ 176287e3f3fSJohn Crispin static void pci_ext_disable(struct clk *clk) 177287e3f3fSJohn Crispin { 178e29b72f5SJohn Crispin ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr); 179e29b72f5SJohn Crispin ltq_cgu_w32((1 << 31) | (1 << 30), pcicr); 180287e3f3fSJohn Crispin } 181287e3f3fSJohn Crispin 182287e3f3fSJohn Crispin /* enable a clockout source */ 183287e3f3fSJohn Crispin static int clkout_enable(struct clk *clk) 184287e3f3fSJohn Crispin { 185287e3f3fSJohn Crispin int i; 186287e3f3fSJohn Crispin 187287e3f3fSJohn Crispin /* get the correct rate */ 188287e3f3fSJohn Crispin for (i = 0; i < 4; i++) { 189287e3f3fSJohn Crispin if (clk->rates[i] == clk->rate) { 190287e3f3fSJohn Crispin int shift = 14 - (2 * clk->module); 19198dbc576SJohn Crispin int enable = 7 - clk->module; 192e29b72f5SJohn Crispin unsigned int val = ltq_cgu_r32(ifccr); 193287e3f3fSJohn Crispin 194e29b72f5SJohn Crispin val &= ~(3 << shift); 195e29b72f5SJohn Crispin val |= i << shift; 19698dbc576SJohn Crispin val |= enable; 197e29b72f5SJohn Crispin ltq_cgu_w32(val, ifccr); 198287e3f3fSJohn Crispin return 0; 199287e3f3fSJohn Crispin } 200287e3f3fSJohn Crispin } 201287e3f3fSJohn Crispin return -1; 202287e3f3fSJohn Crispin } 203287e3f3fSJohn Crispin 204287e3f3fSJohn Crispin /* manage the clock gates via PMU */ 205287e3f3fSJohn Crispin static void clkdev_add_pmu(const char *dev, const char *con, 206287e3f3fSJohn Crispin unsigned int module, unsigned int bits) 207287e3f3fSJohn Crispin { 208287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 209287e3f3fSJohn Crispin 210287e3f3fSJohn Crispin clk->cl.dev_id = dev; 211287e3f3fSJohn Crispin clk->cl.con_id = con; 212287e3f3fSJohn Crispin clk->cl.clk = clk; 213287e3f3fSJohn Crispin clk->enable = pmu_enable; 214287e3f3fSJohn Crispin clk->disable = pmu_disable; 215287e3f3fSJohn Crispin clk->module = module; 216287e3f3fSJohn Crispin clk->bits = bits; 217287e3f3fSJohn Crispin clkdev_add(&clk->cl); 218287e3f3fSJohn Crispin } 219287e3f3fSJohn Crispin 220287e3f3fSJohn Crispin /* manage the clock generator */ 221287e3f3fSJohn Crispin static void clkdev_add_cgu(const char *dev, const char *con, 222287e3f3fSJohn Crispin unsigned int bits) 223287e3f3fSJohn Crispin { 224287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 225287e3f3fSJohn Crispin 226287e3f3fSJohn Crispin clk->cl.dev_id = dev; 227287e3f3fSJohn Crispin clk->cl.con_id = con; 228287e3f3fSJohn Crispin clk->cl.clk = clk; 229287e3f3fSJohn Crispin clk->enable = cgu_enable; 230287e3f3fSJohn Crispin clk->disable = cgu_disable; 231287e3f3fSJohn Crispin clk->bits = bits; 232287e3f3fSJohn Crispin clkdev_add(&clk->cl); 233287e3f3fSJohn Crispin } 234287e3f3fSJohn Crispin 235287e3f3fSJohn Crispin /* pci needs its own enable function as the setup is a bit more complex */ 236287e3f3fSJohn Crispin static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0}; 237287e3f3fSJohn Crispin 238287e3f3fSJohn Crispin static void clkdev_add_pci(void) 239287e3f3fSJohn Crispin { 240287e3f3fSJohn Crispin struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 241287e3f3fSJohn Crispin struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); 242287e3f3fSJohn Crispin 243287e3f3fSJohn Crispin /* main pci clock */ 244287e3f3fSJohn Crispin clk->cl.dev_id = "17000000.pci"; 245287e3f3fSJohn Crispin clk->cl.con_id = NULL; 246287e3f3fSJohn Crispin clk->cl.clk = clk; 247287e3f3fSJohn Crispin clk->rate = CLOCK_33M; 248287e3f3fSJohn Crispin clk->rates = valid_pci_rates; 249287e3f3fSJohn Crispin clk->enable = pci_enable; 250287e3f3fSJohn Crispin clk->disable = pmu_disable; 251287e3f3fSJohn Crispin clk->module = 0; 252287e3f3fSJohn Crispin clk->bits = PMU_PCI; 253287e3f3fSJohn Crispin clkdev_add(&clk->cl); 254287e3f3fSJohn Crispin 255287e3f3fSJohn Crispin /* use internal/external bus clock */ 256287e3f3fSJohn Crispin clk_ext->cl.dev_id = "17000000.pci"; 257287e3f3fSJohn Crispin clk_ext->cl.con_id = "external"; 258287e3f3fSJohn Crispin clk_ext->cl.clk = clk_ext; 259287e3f3fSJohn Crispin clk_ext->enable = pci_ext_enable; 260287e3f3fSJohn Crispin clk_ext->disable = pci_ext_disable; 261287e3f3fSJohn Crispin clkdev_add(&clk_ext->cl); 262287e3f3fSJohn Crispin } 263287e3f3fSJohn Crispin 264287e3f3fSJohn Crispin /* xway socs can generate clocks on gpio pins */ 265287e3f3fSJohn Crispin static unsigned long valid_clkout_rates[4][5] = { 266287e3f3fSJohn Crispin {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, 267287e3f3fSJohn Crispin {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0}, 268287e3f3fSJohn Crispin {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0}, 269287e3f3fSJohn Crispin {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0}, 270287e3f3fSJohn Crispin }; 271287e3f3fSJohn Crispin 272287e3f3fSJohn Crispin static void clkdev_add_clkout(void) 273287e3f3fSJohn Crispin { 274287e3f3fSJohn Crispin int i; 275287e3f3fSJohn Crispin 276287e3f3fSJohn Crispin for (i = 0; i < 4; i++) { 277287e3f3fSJohn Crispin struct clk *clk; 278287e3f3fSJohn Crispin char *name; 279287e3f3fSJohn Crispin 280287e3f3fSJohn Crispin name = kzalloc(sizeof("clkout0"), GFP_KERNEL); 281287e3f3fSJohn Crispin sprintf(name, "clkout%d", i); 282287e3f3fSJohn Crispin 283287e3f3fSJohn Crispin clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 284287e3f3fSJohn Crispin clk->cl.dev_id = "1f103000.cgu"; 285287e3f3fSJohn Crispin clk->cl.con_id = name; 286287e3f3fSJohn Crispin clk->cl.clk = clk; 287287e3f3fSJohn Crispin clk->rate = 0; 288287e3f3fSJohn Crispin clk->rates = valid_clkout_rates[i]; 289287e3f3fSJohn Crispin clk->enable = clkout_enable; 290287e3f3fSJohn Crispin clk->module = i; 291287e3f3fSJohn Crispin clkdev_add(&clk->cl); 292287e3f3fSJohn Crispin } 293287e3f3fSJohn Crispin } 294287e3f3fSJohn Crispin 295287e3f3fSJohn Crispin /* bring up all register ranges that we need for basic system control */ 296287e3f3fSJohn Crispin void __init ltq_soc_init(void) 297287e3f3fSJohn Crispin { 298287e3f3fSJohn Crispin struct resource res_pmu, res_cgu, res_ebu; 299287e3f3fSJohn Crispin struct device_node *np_pmu = 300287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway"); 301287e3f3fSJohn Crispin struct device_node *np_cgu = 302287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway"); 303287e3f3fSJohn Crispin struct device_node *np_ebu = 304287e3f3fSJohn Crispin of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway"); 305287e3f3fSJohn Crispin 306287e3f3fSJohn Crispin /* check if all the core register ranges are available */ 307287e3f3fSJohn Crispin if (!np_pmu || !np_cgu || !np_ebu) 308287e3f3fSJohn Crispin panic("Failed to load core nodess from devicetree"); 309287e3f3fSJohn Crispin 310287e3f3fSJohn Crispin if (of_address_to_resource(np_pmu, 0, &res_pmu) || 311287e3f3fSJohn Crispin of_address_to_resource(np_cgu, 0, &res_cgu) || 312287e3f3fSJohn Crispin of_address_to_resource(np_ebu, 0, &res_ebu)) 313287e3f3fSJohn Crispin panic("Failed to get core resources"); 314287e3f3fSJohn Crispin 315287e3f3fSJohn Crispin if ((request_mem_region(res_pmu.start, resource_size(&res_pmu), 316287e3f3fSJohn Crispin res_pmu.name) < 0) || 317287e3f3fSJohn Crispin (request_mem_region(res_cgu.start, resource_size(&res_cgu), 318287e3f3fSJohn Crispin res_cgu.name) < 0) || 319287e3f3fSJohn Crispin (request_mem_region(res_ebu.start, resource_size(&res_ebu), 320287e3f3fSJohn Crispin res_ebu.name) < 0)) 321287e3f3fSJohn Crispin pr_err("Failed to request core reources"); 322287e3f3fSJohn Crispin 323287e3f3fSJohn Crispin pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu)); 324287e3f3fSJohn Crispin ltq_cgu_membase = ioremap_nocache(res_cgu.start, 325287e3f3fSJohn Crispin resource_size(&res_cgu)); 326287e3f3fSJohn Crispin ltq_ebu_membase = ioremap_nocache(res_ebu.start, 327287e3f3fSJohn Crispin resource_size(&res_ebu)); 328287e3f3fSJohn Crispin if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase) 329287e3f3fSJohn Crispin panic("Failed to remap core resources"); 330287e3f3fSJohn Crispin 331287e3f3fSJohn Crispin /* make sure to unprotect the memory region where flash is located */ 332287e3f3fSJohn Crispin ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); 333287e3f3fSJohn Crispin 334287e3f3fSJohn Crispin /* add our generic xway clocks */ 335287e3f3fSJohn Crispin clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI); 336287e3f3fSJohn Crispin clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0); 337287e3f3fSJohn Crispin clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT); 338287e3f3fSJohn Crispin clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP); 339287e3f3fSJohn Crispin clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA); 340287e3f3fSJohn Crispin clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI); 341287e3f3fSJohn Crispin clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU); 342287e3f3fSJohn Crispin clkdev_add_clkout(); 343287e3f3fSJohn Crispin 344287e3f3fSJohn Crispin /* add the soc dependent clocks */ 345e29b72f5SJohn Crispin if (of_machine_is_compatible("lantiq,vr9")) { 346e29b72f5SJohn Crispin ifccr = CGU_IFCCR_VR9; 347e29b72f5SJohn Crispin pcicr = CGU_PCICR_VR9; 348e29b72f5SJohn Crispin } else { 349287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); 350e29b72f5SJohn Crispin } 351287e3f3fSJohn Crispin 352287e3f3fSJohn Crispin if (!of_machine_is_compatible("lantiq,ase")) { 353287e3f3fSJohn Crispin clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); 354287e3f3fSJohn Crispin clkdev_add_pci(); 355287e3f3fSJohn Crispin } 356287e3f3fSJohn Crispin 357287e3f3fSJohn Crispin if (of_machine_is_compatible("lantiq,ase")) { 358287e3f3fSJohn Crispin if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 359287e3f3fSJohn Crispin clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); 360287e3f3fSJohn Crispin else 361287e3f3fSJohn Crispin clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); 362287e3f3fSJohn Crispin clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), 363287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); 364287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,vr9")) { 365287e3f3fSJohn Crispin clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 366287e3f3fSJohn Crispin ltq_vr9_fpi_hz()); 367287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); 368287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); 369287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); 370287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI); 371287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL); 372287e3f3fSJohn Crispin clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); 373*f2bbe41cSJohn Crispin clkdev_add_pmu("1e108000.eth", NULL, 0, 374*f2bbe41cSJohn Crispin PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 375*f2bbe41cSJohn Crispin PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 376*f2bbe41cSJohn Crispin PMU_PPE_QSB | PMU_PPE_TOP); 377287e3f3fSJohn Crispin } else if (of_machine_is_compatible("lantiq,ar9")) { 378287e3f3fSJohn Crispin clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 379287e3f3fSJohn Crispin ltq_ar9_fpi_hz()); 380287e3f3fSJohn Crispin clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); 381287e3f3fSJohn Crispin } else { 382287e3f3fSJohn Crispin clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 383287e3f3fSJohn Crispin ltq_danube_fpi_hz()); 384287e3f3fSJohn Crispin } 385287e3f3fSJohn Crispin } 386