1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/init.h> 15 #include <linux/mm.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/smp_lock.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/bootmem.h> 23 #include <linux/interrupt.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/branch.h> 27 #include <asm/break.h> 28 #include <asm/cpu.h> 29 #include <asm/dsp.h> 30 #include <asm/fpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/module.h> 34 #include <asm/pgtable.h> 35 #include <asm/ptrace.h> 36 #include <asm/sections.h> 37 #include <asm/system.h> 38 #include <asm/tlbdebug.h> 39 #include <asm/traps.h> 40 #include <asm/uaccess.h> 41 #include <asm/mmu_context.h> 42 #include <asm/watch.h> 43 #include <asm/types.h> 44 #include <asm/stacktrace.h> 45 46 extern asmlinkage void handle_int(void); 47 extern asmlinkage void handle_tlbm(void); 48 extern asmlinkage void handle_tlbl(void); 49 extern asmlinkage void handle_tlbs(void); 50 extern asmlinkage void handle_adel(void); 51 extern asmlinkage void handle_ades(void); 52 extern asmlinkage void handle_ibe(void); 53 extern asmlinkage void handle_dbe(void); 54 extern asmlinkage void handle_sys(void); 55 extern asmlinkage void handle_bp(void); 56 extern asmlinkage void handle_ri(void); 57 extern asmlinkage void handle_ri_rdhwr_vivt(void); 58 extern asmlinkage void handle_ri_rdhwr(void); 59 extern asmlinkage void handle_cpu(void); 60 extern asmlinkage void handle_ov(void); 61 extern asmlinkage void handle_tr(void); 62 extern asmlinkage void handle_fpe(void); 63 extern asmlinkage void handle_mdmx(void); 64 extern asmlinkage void handle_watch(void); 65 extern asmlinkage void handle_mt(void); 66 extern asmlinkage void handle_dsp(void); 67 extern asmlinkage void handle_mcheck(void); 68 extern asmlinkage void handle_reserved(void); 69 70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 71 struct mips_fpu_struct *ctx, int has_fpu); 72 73 void (*board_be_init)(void); 74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 75 void (*board_nmi_handler_setup)(void); 76 void (*board_ejtag_handler_setup)(void); 77 void (*board_bind_eic_interrupt)(int irq, int regset); 78 79 80 static void show_raw_backtrace(unsigned long reg29) 81 { 82 unsigned long *sp = (unsigned long *)reg29; 83 unsigned long addr; 84 85 printk("Call Trace:"); 86 #ifdef CONFIG_KALLSYMS 87 printk("\n"); 88 #endif 89 while (!kstack_end(sp)) { 90 addr = *sp++; 91 if (__kernel_text_address(addr)) 92 print_ip_sym(addr); 93 } 94 printk("\n"); 95 } 96 97 #ifdef CONFIG_KALLSYMS 98 int raw_show_trace; 99 static int __init set_raw_show_trace(char *str) 100 { 101 raw_show_trace = 1; 102 return 1; 103 } 104 __setup("raw_show_trace", set_raw_show_trace); 105 #endif 106 107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs) 108 { 109 unsigned long sp = regs->regs[29]; 110 unsigned long ra = regs->regs[31]; 111 unsigned long pc = regs->cp0_epc; 112 113 if (raw_show_trace || !__kernel_text_address(pc)) { 114 show_raw_backtrace(sp); 115 return; 116 } 117 printk("Call Trace:\n"); 118 do { 119 print_ip_sym(pc); 120 pc = unwind_stack(task, &sp, pc, &ra); 121 } while (pc); 122 printk("\n"); 123 } 124 125 /* 126 * This routine abuses get_user()/put_user() to reference pointers 127 * with at least a bit of error checking ... 128 */ 129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) 130 { 131 const int field = 2 * sizeof(unsigned long); 132 long stackdata; 133 int i; 134 unsigned long *sp = (unsigned long *)regs->regs[29]; 135 136 printk("Stack :"); 137 i = 0; 138 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 139 if (i && ((i % (64 / field)) == 0)) 140 printk("\n "); 141 if (i > 39) { 142 printk(" ..."); 143 break; 144 } 145 146 if (__get_user(stackdata, sp++)) { 147 printk(" (Bad stack address)"); 148 break; 149 } 150 151 printk(" %0*lx", field, stackdata); 152 i++; 153 } 154 printk("\n"); 155 show_backtrace(task, regs); 156 } 157 158 void show_stack(struct task_struct *task, unsigned long *sp) 159 { 160 struct pt_regs regs; 161 if (sp) { 162 regs.regs[29] = (unsigned long)sp; 163 regs.regs[31] = 0; 164 regs.cp0_epc = 0; 165 } else { 166 if (task && task != current) { 167 regs.regs[29] = task->thread.reg29; 168 regs.regs[31] = 0; 169 regs.cp0_epc = task->thread.reg31; 170 } else { 171 prepare_frametrace(®s); 172 } 173 } 174 show_stacktrace(task, ®s); 175 } 176 177 /* 178 * The architecture-independent dump_stack generator 179 */ 180 void dump_stack(void) 181 { 182 struct pt_regs regs; 183 184 prepare_frametrace(®s); 185 show_backtrace(current, ®s); 186 } 187 188 EXPORT_SYMBOL(dump_stack); 189 190 void show_code(unsigned int *pc) 191 { 192 long i; 193 194 printk("\nCode:"); 195 196 for(i = -3 ; i < 6 ; i++) { 197 unsigned int insn; 198 if (__get_user(insn, pc + i)) { 199 printk(" (Bad address in epc)\n"); 200 break; 201 } 202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 203 } 204 } 205 206 void show_regs(struct pt_regs *regs) 207 { 208 const int field = 2 * sizeof(unsigned long); 209 unsigned int cause = regs->cp0_cause; 210 int i; 211 212 printk("Cpu %d\n", smp_processor_id()); 213 214 /* 215 * Saved main processor registers 216 */ 217 for (i = 0; i < 32; ) { 218 if ((i % 4) == 0) 219 printk("$%2d :", i); 220 if (i == 0) 221 printk(" %0*lx", field, 0UL); 222 else if (i == 26 || i == 27) 223 printk(" %*s", field, ""); 224 else 225 printk(" %0*lx", field, regs->regs[i]); 226 227 i++; 228 if ((i % 4) == 0) 229 printk("\n"); 230 } 231 232 #ifdef CONFIG_CPU_HAS_SMARTMIPS 233 printk("Acx : %0*lx\n", field, regs->acx); 234 #endif 235 printk("Hi : %0*lx\n", field, regs->hi); 236 printk("Lo : %0*lx\n", field, regs->lo); 237 238 /* 239 * Saved cp0 registers 240 */ 241 printk("epc : %0*lx ", field, regs->cp0_epc); 242 print_symbol("%s ", regs->cp0_epc); 243 printk(" %s\n", print_tainted()); 244 printk("ra : %0*lx ", field, regs->regs[31]); 245 print_symbol("%s\n", regs->regs[31]); 246 247 printk("Status: %08x ", (uint32_t) regs->cp0_status); 248 249 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 250 if (regs->cp0_status & ST0_KUO) 251 printk("KUo "); 252 if (regs->cp0_status & ST0_IEO) 253 printk("IEo "); 254 if (regs->cp0_status & ST0_KUP) 255 printk("KUp "); 256 if (regs->cp0_status & ST0_IEP) 257 printk("IEp "); 258 if (regs->cp0_status & ST0_KUC) 259 printk("KUc "); 260 if (regs->cp0_status & ST0_IEC) 261 printk("IEc "); 262 } else { 263 if (regs->cp0_status & ST0_KX) 264 printk("KX "); 265 if (regs->cp0_status & ST0_SX) 266 printk("SX "); 267 if (regs->cp0_status & ST0_UX) 268 printk("UX "); 269 switch (regs->cp0_status & ST0_KSU) { 270 case KSU_USER: 271 printk("USER "); 272 break; 273 case KSU_SUPERVISOR: 274 printk("SUPERVISOR "); 275 break; 276 case KSU_KERNEL: 277 printk("KERNEL "); 278 break; 279 default: 280 printk("BAD_MODE "); 281 break; 282 } 283 if (regs->cp0_status & ST0_ERL) 284 printk("ERL "); 285 if (regs->cp0_status & ST0_EXL) 286 printk("EXL "); 287 if (regs->cp0_status & ST0_IE) 288 printk("IE "); 289 } 290 printk("\n"); 291 292 printk("Cause : %08x\n", cause); 293 294 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 295 if (1 <= cause && cause <= 5) 296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 297 298 printk("PrId : %08x\n", read_c0_prid()); 299 } 300 301 void show_registers(struct pt_regs *regs) 302 { 303 show_regs(regs); 304 print_modules(); 305 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 306 current->comm, current->pid, current_thread_info(), current); 307 show_stacktrace(current, regs); 308 show_code((unsigned int *) regs->cp0_epc); 309 printk("\n"); 310 } 311 312 static DEFINE_SPINLOCK(die_lock); 313 314 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) 315 { 316 static int die_counter; 317 #ifdef CONFIG_MIPS_MT_SMTC 318 unsigned long dvpret = dvpe(); 319 #endif /* CONFIG_MIPS_MT_SMTC */ 320 321 console_verbose(); 322 spin_lock_irq(&die_lock); 323 bust_spinlocks(1); 324 #ifdef CONFIG_MIPS_MT_SMTC 325 mips_mt_regdump(dvpret); 326 #endif /* CONFIG_MIPS_MT_SMTC */ 327 printk("%s[#%d]:\n", str, ++die_counter); 328 show_registers(regs); 329 spin_unlock_irq(&die_lock); 330 331 if (in_interrupt()) 332 panic("Fatal exception in interrupt"); 333 334 if (panic_on_oops) { 335 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 336 ssleep(5); 337 panic("Fatal exception"); 338 } 339 340 do_exit(SIGSEGV); 341 } 342 343 extern const struct exception_table_entry __start___dbe_table[]; 344 extern const struct exception_table_entry __stop___dbe_table[]; 345 346 __asm__( 347 " .section __dbe_table, \"a\"\n" 348 " .previous \n"); 349 350 /* Given an address, look for it in the exception tables. */ 351 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 352 { 353 const struct exception_table_entry *e; 354 355 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 356 if (!e) 357 e = search_module_dbetables(addr); 358 return e; 359 } 360 361 asmlinkage void do_be(struct pt_regs *regs) 362 { 363 const int field = 2 * sizeof(unsigned long); 364 const struct exception_table_entry *fixup = NULL; 365 int data = regs->cp0_cause & 4; 366 int action = MIPS_BE_FATAL; 367 368 /* XXX For now. Fixme, this searches the wrong table ... */ 369 if (data && !user_mode(regs)) 370 fixup = search_dbe_tables(exception_epc(regs)); 371 372 if (fixup) 373 action = MIPS_BE_FIXUP; 374 375 if (board_be_handler) 376 action = board_be_handler(regs, fixup != 0); 377 378 switch (action) { 379 case MIPS_BE_DISCARD: 380 return; 381 case MIPS_BE_FIXUP: 382 if (fixup) { 383 regs->cp0_epc = fixup->nextinsn; 384 return; 385 } 386 break; 387 default: 388 break; 389 } 390 391 /* 392 * Assume it would be too dangerous to continue ... 393 */ 394 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 395 data ? "Data" : "Instruction", 396 field, regs->cp0_epc, field, regs->regs[31]); 397 die_if_kernel("Oops", regs); 398 force_sig(SIGBUS, current); 399 } 400 401 /* 402 * ll/sc emulation 403 */ 404 405 #define OPCODE 0xfc000000 406 #define BASE 0x03e00000 407 #define RT 0x001f0000 408 #define OFFSET 0x0000ffff 409 #define LL 0xc0000000 410 #define SC 0xe0000000 411 #define SPEC3 0x7c000000 412 #define RD 0x0000f800 413 #define FUNC 0x0000003f 414 #define RDHWR 0x0000003b 415 416 /* 417 * The ll_bit is cleared by r*_switch.S 418 */ 419 420 unsigned long ll_bit; 421 422 static struct task_struct *ll_task = NULL; 423 424 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 425 { 426 unsigned long value, __user *vaddr; 427 long offset; 428 int signal = 0; 429 430 /* 431 * analyse the ll instruction that just caused a ri exception 432 * and put the referenced address to addr. 433 */ 434 435 /* sign extend offset */ 436 offset = opcode & OFFSET; 437 offset <<= 16; 438 offset >>= 16; 439 440 vaddr = (unsigned long __user *) 441 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 442 443 if ((unsigned long)vaddr & 3) { 444 signal = SIGBUS; 445 goto sig; 446 } 447 if (get_user(value, vaddr)) { 448 signal = SIGSEGV; 449 goto sig; 450 } 451 452 preempt_disable(); 453 454 if (ll_task == NULL || ll_task == current) { 455 ll_bit = 1; 456 } else { 457 ll_bit = 0; 458 } 459 ll_task = current; 460 461 preempt_enable(); 462 463 compute_return_epc(regs); 464 465 regs->regs[(opcode & RT) >> 16] = value; 466 467 return; 468 469 sig: 470 force_sig(signal, current); 471 } 472 473 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 474 { 475 unsigned long __user *vaddr; 476 unsigned long reg; 477 long offset; 478 int signal = 0; 479 480 /* 481 * analyse the sc instruction that just caused a ri exception 482 * and put the referenced address to addr. 483 */ 484 485 /* sign extend offset */ 486 offset = opcode & OFFSET; 487 offset <<= 16; 488 offset >>= 16; 489 490 vaddr = (unsigned long __user *) 491 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 492 reg = (opcode & RT) >> 16; 493 494 if ((unsigned long)vaddr & 3) { 495 signal = SIGBUS; 496 goto sig; 497 } 498 499 preempt_disable(); 500 501 if (ll_bit == 0 || ll_task != current) { 502 compute_return_epc(regs); 503 regs->regs[reg] = 0; 504 preempt_enable(); 505 return; 506 } 507 508 preempt_enable(); 509 510 if (put_user(regs->regs[reg], vaddr)) { 511 signal = SIGSEGV; 512 goto sig; 513 } 514 515 compute_return_epc(regs); 516 regs->regs[reg] = 1; 517 518 return; 519 520 sig: 521 force_sig(signal, current); 522 } 523 524 /* 525 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 526 * opcodes are supposed to result in coprocessor unusable exceptions if 527 * executed on ll/sc-less processors. That's the theory. In practice a 528 * few processors such as NEC's VR4100 throw reserved instruction exceptions 529 * instead, so we're doing the emulation thing in both exception handlers. 530 */ 531 static inline int simulate_llsc(struct pt_regs *regs) 532 { 533 unsigned int opcode; 534 535 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 536 goto out_sigsegv; 537 538 if ((opcode & OPCODE) == LL) { 539 simulate_ll(regs, opcode); 540 return 0; 541 } 542 if ((opcode & OPCODE) == SC) { 543 simulate_sc(regs, opcode); 544 return 0; 545 } 546 547 return -EFAULT; /* Strange things going on ... */ 548 549 out_sigsegv: 550 force_sig(SIGSEGV, current); 551 return -EFAULT; 552 } 553 554 /* 555 * Simulate trapping 'rdhwr' instructions to provide user accessible 556 * registers not implemented in hardware. The only current use of this 557 * is the thread area pointer. 558 */ 559 static inline int simulate_rdhwr(struct pt_regs *regs) 560 { 561 struct thread_info *ti = task_thread_info(current); 562 unsigned int opcode; 563 564 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 565 goto out_sigsegv; 566 567 if (unlikely(compute_return_epc(regs))) 568 return -EFAULT; 569 570 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 571 int rd = (opcode & RD) >> 11; 572 int rt = (opcode & RT) >> 16; 573 switch (rd) { 574 case 29: 575 regs->regs[rt] = ti->tp_value; 576 return 0; 577 default: 578 return -EFAULT; 579 } 580 } 581 582 /* Not ours. */ 583 return -EFAULT; 584 585 out_sigsegv: 586 force_sig(SIGSEGV, current); 587 return -EFAULT; 588 } 589 590 asmlinkage void do_ov(struct pt_regs *regs) 591 { 592 siginfo_t info; 593 594 die_if_kernel("Integer overflow", regs); 595 596 info.si_code = FPE_INTOVF; 597 info.si_signo = SIGFPE; 598 info.si_errno = 0; 599 info.si_addr = (void __user *) regs->cp0_epc; 600 force_sig_info(SIGFPE, &info, current); 601 } 602 603 /* 604 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 605 */ 606 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 607 { 608 die_if_kernel("FP exception in kernel code", regs); 609 610 if (fcr31 & FPU_CSR_UNI_X) { 611 int sig; 612 613 preempt_disable(); 614 615 #ifdef CONFIG_PREEMPT 616 if (!is_fpu_owner()) { 617 /* We might lose fpu before disabling preempt... */ 618 own_fpu(); 619 BUG_ON(!used_math()); 620 restore_fp(current); 621 } 622 #endif 623 /* 624 * Unimplemented operation exception. If we've got the full 625 * software emulator on-board, let's use it... 626 * 627 * Force FPU to dump state into task/thread context. We're 628 * moving a lot of data here for what is probably a single 629 * instruction, but the alternative is to pre-decode the FP 630 * register operands before invoking the emulator, which seems 631 * a bit extreme for what should be an infrequent event. 632 */ 633 save_fp(current); 634 /* Ensure 'resume' not overwrite saved fp context again. */ 635 lose_fpu(); 636 637 preempt_enable(); 638 639 /* Run the emulator */ 640 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); 641 642 preempt_disable(); 643 644 own_fpu(); /* Using the FPU again. */ 645 /* 646 * We can't allow the emulated instruction to leave any of 647 * the cause bit set in $fcr31. 648 */ 649 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 650 651 /* Restore the hardware register state */ 652 restore_fp(current); 653 654 preempt_enable(); 655 656 /* If something went wrong, signal */ 657 if (sig) 658 force_sig(sig, current); 659 660 return; 661 } 662 663 force_sig(SIGFPE, current); 664 } 665 666 asmlinkage void do_bp(struct pt_regs *regs) 667 { 668 unsigned int opcode, bcode; 669 siginfo_t info; 670 671 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 672 goto out_sigsegv; 673 674 /* 675 * There is the ancient bug in the MIPS assemblers that the break 676 * code starts left to bit 16 instead to bit 6 in the opcode. 677 * Gas is bug-compatible, but not always, grrr... 678 * We handle both cases with a simple heuristics. --macro 679 */ 680 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 681 if (bcode < (1 << 10)) 682 bcode <<= 10; 683 684 /* 685 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 686 * insns, even for break codes that indicate arithmetic failures. 687 * Weird ...) 688 * But should we continue the brokenness??? --macro 689 */ 690 switch (bcode) { 691 case BRK_OVERFLOW << 10: 692 case BRK_DIVZERO << 10: 693 die_if_kernel("Break instruction in kernel code", regs); 694 if (bcode == (BRK_DIVZERO << 10)) 695 info.si_code = FPE_INTDIV; 696 else 697 info.si_code = FPE_INTOVF; 698 info.si_signo = SIGFPE; 699 info.si_errno = 0; 700 info.si_addr = (void __user *) regs->cp0_epc; 701 force_sig_info(SIGFPE, &info, current); 702 break; 703 case BRK_BUG: 704 die("Kernel bug detected", regs); 705 break; 706 default: 707 die_if_kernel("Break instruction in kernel code", regs); 708 force_sig(SIGTRAP, current); 709 } 710 return; 711 712 out_sigsegv: 713 force_sig(SIGSEGV, current); 714 } 715 716 asmlinkage void do_tr(struct pt_regs *regs) 717 { 718 unsigned int opcode, tcode = 0; 719 siginfo_t info; 720 721 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 722 goto out_sigsegv; 723 724 /* Immediate versions don't provide a code. */ 725 if (!(opcode & OPCODE)) 726 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 727 728 /* 729 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 730 * insns, even for trap codes that indicate arithmetic failures. 731 * Weird ...) 732 * But should we continue the brokenness??? --macro 733 */ 734 switch (tcode) { 735 case BRK_OVERFLOW: 736 case BRK_DIVZERO: 737 die_if_kernel("Trap instruction in kernel code", regs); 738 if (tcode == BRK_DIVZERO) 739 info.si_code = FPE_INTDIV; 740 else 741 info.si_code = FPE_INTOVF; 742 info.si_signo = SIGFPE; 743 info.si_errno = 0; 744 info.si_addr = (void __user *) regs->cp0_epc; 745 force_sig_info(SIGFPE, &info, current); 746 break; 747 case BRK_BUG: 748 die("Kernel bug detected", regs); 749 break; 750 default: 751 die_if_kernel("Trap instruction in kernel code", regs); 752 force_sig(SIGTRAP, current); 753 } 754 return; 755 756 out_sigsegv: 757 force_sig(SIGSEGV, current); 758 } 759 760 asmlinkage void do_ri(struct pt_regs *regs) 761 { 762 die_if_kernel("Reserved instruction in kernel code", regs); 763 764 if (!cpu_has_llsc) 765 if (!simulate_llsc(regs)) 766 return; 767 768 if (!simulate_rdhwr(regs)) 769 return; 770 771 force_sig(SIGILL, current); 772 } 773 774 asmlinkage void do_cpu(struct pt_regs *regs) 775 { 776 unsigned int cpid; 777 778 die_if_kernel("do_cpu invoked from kernel context!", regs); 779 780 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 781 782 switch (cpid) { 783 case 0: 784 if (!cpu_has_llsc) 785 if (!simulate_llsc(regs)) 786 return; 787 788 if (!simulate_rdhwr(regs)) 789 return; 790 791 break; 792 793 case 1: 794 preempt_disable(); 795 796 own_fpu(); 797 if (used_math()) { /* Using the FPU again. */ 798 restore_fp(current); 799 } else { /* First time FPU user. */ 800 init_fpu(); 801 set_used_math(); 802 } 803 804 if (cpu_has_fpu) { 805 preempt_enable(); 806 } else { 807 int sig; 808 preempt_enable(); 809 sig = fpu_emulator_cop1Handler(regs, 810 ¤t->thread.fpu, 0); 811 if (sig) 812 force_sig(sig, current); 813 #ifdef CONFIG_MIPS_MT_FPAFF 814 else { 815 /* 816 * MIPS MT processors may have fewer FPU contexts 817 * than CPU threads. If we've emulated more than 818 * some threshold number of instructions, force 819 * migration to a "CPU" that has FP support. 820 */ 821 if(mt_fpemul_threshold > 0 822 && ((current->thread.emulated_fp++ 823 > mt_fpemul_threshold))) { 824 /* 825 * If there's no FPU present, or if the 826 * application has already restricted 827 * the allowed set to exclude any CPUs 828 * with FPUs, we'll skip the procedure. 829 */ 830 if (cpus_intersects(current->cpus_allowed, 831 mt_fpu_cpumask)) { 832 cpumask_t tmask; 833 834 cpus_and(tmask, 835 current->thread.user_cpus_allowed, 836 mt_fpu_cpumask); 837 set_cpus_allowed(current, tmask); 838 current->thread.mflags |= MF_FPUBOUND; 839 } 840 } 841 } 842 #endif /* CONFIG_MIPS_MT_FPAFF */ 843 } 844 845 return; 846 847 case 2: 848 case 3: 849 die_if_kernel("do_cpu invoked from kernel context!", regs); 850 break; 851 } 852 853 force_sig(SIGILL, current); 854 } 855 856 asmlinkage void do_mdmx(struct pt_regs *regs) 857 { 858 force_sig(SIGILL, current); 859 } 860 861 asmlinkage void do_watch(struct pt_regs *regs) 862 { 863 /* 864 * We use the watch exception where available to detect stack 865 * overflows. 866 */ 867 dump_tlb_all(); 868 show_regs(regs); 869 panic("Caught WATCH exception - probably caused by stack overflow."); 870 } 871 872 asmlinkage void do_mcheck(struct pt_regs *regs) 873 { 874 const int field = 2 * sizeof(unsigned long); 875 int multi_match = regs->cp0_status & ST0_TS; 876 877 show_regs(regs); 878 879 if (multi_match) { 880 printk("Index : %0x\n", read_c0_index()); 881 printk("Pagemask: %0x\n", read_c0_pagemask()); 882 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 883 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 884 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 885 printk("\n"); 886 dump_tlb_all(); 887 } 888 889 show_code((unsigned int *) regs->cp0_epc); 890 891 /* 892 * Some chips may have other causes of machine check (e.g. SB1 893 * graduation timer) 894 */ 895 panic("Caught Machine Check exception - %scaused by multiple " 896 "matching entries in the TLB.", 897 (multi_match) ? "" : "not "); 898 } 899 900 asmlinkage void do_mt(struct pt_regs *regs) 901 { 902 int subcode; 903 904 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 905 >> VPECONTROL_EXCPT_SHIFT; 906 switch (subcode) { 907 case 0: 908 printk(KERN_DEBUG "Thread Underflow\n"); 909 break; 910 case 1: 911 printk(KERN_DEBUG "Thread Overflow\n"); 912 break; 913 case 2: 914 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 915 break; 916 case 3: 917 printk(KERN_DEBUG "Gating Storage Exception\n"); 918 break; 919 case 4: 920 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 921 break; 922 case 5: 923 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 924 break; 925 default: 926 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 927 subcode); 928 break; 929 } 930 die_if_kernel("MIPS MT Thread exception in kernel", regs); 931 932 force_sig(SIGILL, current); 933 } 934 935 936 asmlinkage void do_dsp(struct pt_regs *regs) 937 { 938 if (cpu_has_dsp) 939 panic("Unexpected DSP exception\n"); 940 941 force_sig(SIGILL, current); 942 } 943 944 asmlinkage void do_reserved(struct pt_regs *regs) 945 { 946 /* 947 * Game over - no way to handle this if it ever occurs. Most probably 948 * caused by a new unknown cpu type or after another deadly 949 * hard/software error. 950 */ 951 show_regs(regs); 952 panic("Caught reserved exception %ld - should not happen.", 953 (regs->cp0_cause & 0x7f) >> 2); 954 } 955 956 asmlinkage void do_default_vi(struct pt_regs *regs) 957 { 958 show_regs(regs); 959 panic("Caught unexpected vectored interrupt."); 960 } 961 962 /* 963 * Some MIPS CPUs can enable/disable for cache parity detection, but do 964 * it different ways. 965 */ 966 static inline void parity_protection_init(void) 967 { 968 switch (current_cpu_data.cputype) { 969 case CPU_24K: 970 case CPU_34K: 971 case CPU_5KC: 972 write_c0_ecc(0x80000000); 973 back_to_back_c0_hazard(); 974 /* Set the PE bit (bit 31) in the c0_errctl register. */ 975 printk(KERN_INFO "Cache parity protection %sabled\n", 976 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 977 break; 978 case CPU_20KC: 979 case CPU_25KF: 980 /* Clear the DE bit (bit 16) in the c0_status register. */ 981 printk(KERN_INFO "Enable cache parity protection for " 982 "MIPS 20KC/25KF CPUs.\n"); 983 clear_c0_status(ST0_DE); 984 break; 985 default: 986 break; 987 } 988 } 989 990 asmlinkage void cache_parity_error(void) 991 { 992 const int field = 2 * sizeof(unsigned long); 993 unsigned int reg_val; 994 995 /* For the moment, report the problem and hang. */ 996 printk("Cache error exception:\n"); 997 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 998 reg_val = read_c0_cacheerr(); 999 printk("c0_cacheerr == %08x\n", reg_val); 1000 1001 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1002 reg_val & (1<<30) ? "secondary" : "primary", 1003 reg_val & (1<<31) ? "data" : "insn"); 1004 printk("Error bits: %s%s%s%s%s%s%s\n", 1005 reg_val & (1<<29) ? "ED " : "", 1006 reg_val & (1<<28) ? "ET " : "", 1007 reg_val & (1<<26) ? "EE " : "", 1008 reg_val & (1<<25) ? "EB " : "", 1009 reg_val & (1<<24) ? "EI " : "", 1010 reg_val & (1<<23) ? "E1 " : "", 1011 reg_val & (1<<22) ? "E0 " : ""); 1012 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1013 1014 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1015 if (reg_val & (1<<22)) 1016 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1017 1018 if (reg_val & (1<<23)) 1019 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1020 #endif 1021 1022 panic("Can't handle the cache error!"); 1023 } 1024 1025 /* 1026 * SDBBP EJTAG debug exception handler. 1027 * We skip the instruction and return to the next instruction. 1028 */ 1029 void ejtag_exception_handler(struct pt_regs *regs) 1030 { 1031 const int field = 2 * sizeof(unsigned long); 1032 unsigned long depc, old_epc; 1033 unsigned int debug; 1034 1035 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1036 depc = read_c0_depc(); 1037 debug = read_c0_debug(); 1038 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1039 if (debug & 0x80000000) { 1040 /* 1041 * In branch delay slot. 1042 * We cheat a little bit here and use EPC to calculate the 1043 * debug return address (DEPC). EPC is restored after the 1044 * calculation. 1045 */ 1046 old_epc = regs->cp0_epc; 1047 regs->cp0_epc = depc; 1048 __compute_return_epc(regs); 1049 depc = regs->cp0_epc; 1050 regs->cp0_epc = old_epc; 1051 } else 1052 depc += 4; 1053 write_c0_depc(depc); 1054 1055 #if 0 1056 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1057 write_c0_debug(debug | 0x100); 1058 #endif 1059 } 1060 1061 /* 1062 * NMI exception handler. 1063 */ 1064 void nmi_exception_handler(struct pt_regs *regs) 1065 { 1066 #ifdef CONFIG_MIPS_MT_SMTC 1067 unsigned long dvpret = dvpe(); 1068 bust_spinlocks(1); 1069 printk("NMI taken!!!!\n"); 1070 mips_mt_regdump(dvpret); 1071 #else 1072 bust_spinlocks(1); 1073 printk("NMI taken!!!!\n"); 1074 #endif /* CONFIG_MIPS_MT_SMTC */ 1075 die("NMI", regs); 1076 while(1) ; 1077 } 1078 1079 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1080 1081 unsigned long ebase; 1082 unsigned long exception_handlers[32]; 1083 unsigned long vi_handlers[64]; 1084 1085 /* 1086 * As a side effect of the way this is implemented we're limited 1087 * to interrupt handlers in the address range from 1088 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1089 */ 1090 void *set_except_vector(int n, void *addr) 1091 { 1092 unsigned long handler = (unsigned long) addr; 1093 unsigned long old_handler = exception_handlers[n]; 1094 1095 exception_handlers[n] = handler; 1096 if (n == 0 && cpu_has_divec) { 1097 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1098 (0x03ffffff & (handler >> 2)); 1099 flush_icache_range(ebase + 0x200, ebase + 0x204); 1100 } 1101 return (void *)old_handler; 1102 } 1103 1104 #ifdef CONFIG_CPU_MIPSR2_SRS 1105 /* 1106 * MIPSR2 shadow register set allocation 1107 * FIXME: SMP... 1108 */ 1109 1110 static struct shadow_registers { 1111 /* 1112 * Number of shadow register sets supported 1113 */ 1114 unsigned long sr_supported; 1115 /* 1116 * Bitmap of allocated shadow registers 1117 */ 1118 unsigned long sr_allocated; 1119 } shadow_registers; 1120 1121 static void mips_srs_init(void) 1122 { 1123 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1124 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1125 shadow_registers.sr_supported); 1126 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1127 } 1128 1129 int mips_srs_max(void) 1130 { 1131 return shadow_registers.sr_supported; 1132 } 1133 1134 int mips_srs_alloc(void) 1135 { 1136 struct shadow_registers *sr = &shadow_registers; 1137 int set; 1138 1139 again: 1140 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1141 if (set >= sr->sr_supported) 1142 return -1; 1143 1144 if (test_and_set_bit(set, &sr->sr_allocated)) 1145 goto again; 1146 1147 return set; 1148 } 1149 1150 void mips_srs_free(int set) 1151 { 1152 struct shadow_registers *sr = &shadow_registers; 1153 1154 clear_bit(set, &sr->sr_allocated); 1155 } 1156 1157 static void *set_vi_srs_handler(int n, void *addr, int srs) 1158 { 1159 unsigned long handler; 1160 unsigned long old_handler = vi_handlers[n]; 1161 u32 *w; 1162 unsigned char *b; 1163 1164 if (!cpu_has_veic && !cpu_has_vint) 1165 BUG(); 1166 1167 if (addr == NULL) { 1168 handler = (unsigned long) do_default_vi; 1169 srs = 0; 1170 } else 1171 handler = (unsigned long) addr; 1172 vi_handlers[n] = (unsigned long) addr; 1173 1174 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1175 1176 if (srs >= mips_srs_max()) 1177 panic("Shadow register set %d not supported", srs); 1178 1179 if (cpu_has_veic) { 1180 if (board_bind_eic_interrupt) 1181 board_bind_eic_interrupt (n, srs); 1182 } else if (cpu_has_vint) { 1183 /* SRSMap is only defined if shadow sets are implemented */ 1184 if (mips_srs_max() > 1) 1185 change_c0_srsmap (0xf << n*4, srs << n*4); 1186 } 1187 1188 if (srs == 0) { 1189 /* 1190 * If no shadow set is selected then use the default handler 1191 * that does normal register saving and a standard interrupt exit 1192 */ 1193 1194 extern char except_vec_vi, except_vec_vi_lui; 1195 extern char except_vec_vi_ori, except_vec_vi_end; 1196 #ifdef CONFIG_MIPS_MT_SMTC 1197 /* 1198 * We need to provide the SMTC vectored interrupt handler 1199 * not only with the address of the handler, but with the 1200 * Status.IM bit to be masked before going there. 1201 */ 1202 extern char except_vec_vi_mori; 1203 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1204 #endif /* CONFIG_MIPS_MT_SMTC */ 1205 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1206 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1207 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1208 1209 if (handler_len > VECTORSPACING) { 1210 /* 1211 * Sigh... panicing won't help as the console 1212 * is probably not configured :( 1213 */ 1214 panic ("VECTORSPACING too small"); 1215 } 1216 1217 memcpy (b, &except_vec_vi, handler_len); 1218 #ifdef CONFIG_MIPS_MT_SMTC 1219 if (n > 7) 1220 printk("Vector index %d exceeds SMTC maximum\n", n); 1221 w = (u32 *)(b + mori_offset); 1222 *w = (*w & 0xffff0000) | (0x100 << n); 1223 #endif /* CONFIG_MIPS_MT_SMTC */ 1224 w = (u32 *)(b + lui_offset); 1225 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1226 w = (u32 *)(b + ori_offset); 1227 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1228 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1229 } 1230 else { 1231 /* 1232 * In other cases jump directly to the interrupt handler 1233 * 1234 * It is the handlers responsibility to save registers if required 1235 * (eg hi/lo) and return from the exception using "eret" 1236 */ 1237 w = (u32 *)b; 1238 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1239 *w = 0; 1240 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1241 } 1242 1243 return (void *)old_handler; 1244 } 1245 1246 void *set_vi_handler(int n, void *addr) 1247 { 1248 return set_vi_srs_handler(n, addr, 0); 1249 } 1250 1251 #else 1252 1253 static inline void mips_srs_init(void) 1254 { 1255 } 1256 1257 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1258 1259 /* 1260 * This is used by native signal handling 1261 */ 1262 asmlinkage int (*save_fp_context)(struct sigcontext *sc); 1263 asmlinkage int (*restore_fp_context)(struct sigcontext *sc); 1264 1265 extern asmlinkage int _save_fp_context(struct sigcontext *sc); 1266 extern asmlinkage int _restore_fp_context(struct sigcontext *sc); 1267 1268 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); 1269 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); 1270 1271 #ifdef CONFIG_SMP 1272 static int smp_save_fp_context(struct sigcontext *sc) 1273 { 1274 return cpu_has_fpu 1275 ? _save_fp_context(sc) 1276 : fpu_emulator_save_context(sc); 1277 } 1278 1279 static int smp_restore_fp_context(struct sigcontext *sc) 1280 { 1281 return cpu_has_fpu 1282 ? _restore_fp_context(sc) 1283 : fpu_emulator_restore_context(sc); 1284 } 1285 #endif 1286 1287 static inline void signal_init(void) 1288 { 1289 #ifdef CONFIG_SMP 1290 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1291 save_fp_context = smp_save_fp_context; 1292 restore_fp_context = smp_restore_fp_context; 1293 #else 1294 if (cpu_has_fpu) { 1295 save_fp_context = _save_fp_context; 1296 restore_fp_context = _restore_fp_context; 1297 } else { 1298 save_fp_context = fpu_emulator_save_context; 1299 restore_fp_context = fpu_emulator_restore_context; 1300 } 1301 #endif 1302 } 1303 1304 #ifdef CONFIG_MIPS32_COMPAT 1305 1306 /* 1307 * This is used by 32-bit signal stuff on the 64-bit kernel 1308 */ 1309 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); 1310 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); 1311 1312 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); 1313 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); 1314 1315 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); 1316 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); 1317 1318 static inline void signal32_init(void) 1319 { 1320 if (cpu_has_fpu) { 1321 save_fp_context32 = _save_fp_context32; 1322 restore_fp_context32 = _restore_fp_context32; 1323 } else { 1324 save_fp_context32 = fpu_emulator_save_context32; 1325 restore_fp_context32 = fpu_emulator_restore_context32; 1326 } 1327 } 1328 #endif 1329 1330 extern void cpu_cache_init(void); 1331 extern void tlb_init(void); 1332 extern void flush_tlb_handlers(void); 1333 1334 void __init per_cpu_trap_init(void) 1335 { 1336 unsigned int cpu = smp_processor_id(); 1337 unsigned int status_set = ST0_CU0; 1338 #ifdef CONFIG_MIPS_MT_SMTC 1339 int secondaryTC = 0; 1340 int bootTC = (cpu == 0); 1341 1342 /* 1343 * Only do per_cpu_trap_init() for first TC of Each VPE. 1344 * Note that this hack assumes that the SMTC init code 1345 * assigns TCs consecutively and in ascending order. 1346 */ 1347 1348 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1349 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1350 secondaryTC = 1; 1351 #endif /* CONFIG_MIPS_MT_SMTC */ 1352 1353 /* 1354 * Disable coprocessors and select 32-bit or 64-bit addressing 1355 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1356 * flag that some firmware may have left set and the TS bit (for 1357 * IP27). Set XX for ISA IV code to work. 1358 */ 1359 #ifdef CONFIG_64BIT 1360 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1361 #endif 1362 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1363 status_set |= ST0_XX; 1364 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1365 status_set); 1366 1367 if (cpu_has_dsp) 1368 set_c0_status(ST0_MX); 1369 1370 #ifdef CONFIG_CPU_MIPSR2 1371 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ 1372 #endif 1373 1374 #ifdef CONFIG_MIPS_MT_SMTC 1375 if (!secondaryTC) { 1376 #endif /* CONFIG_MIPS_MT_SMTC */ 1377 1378 /* 1379 * Interrupt handling. 1380 */ 1381 if (cpu_has_veic || cpu_has_vint) { 1382 write_c0_ebase (ebase); 1383 /* Setting vector spacing enables EI/VI mode */ 1384 change_c0_intctl (0x3e0, VECTORSPACING); 1385 } 1386 if (cpu_has_divec) { 1387 if (cpu_has_mipsmt) { 1388 unsigned int vpflags = dvpe(); 1389 set_c0_cause(CAUSEF_IV); 1390 evpe(vpflags); 1391 } else 1392 set_c0_cause(CAUSEF_IV); 1393 } 1394 #ifdef CONFIG_MIPS_MT_SMTC 1395 } 1396 #endif /* CONFIG_MIPS_MT_SMTC */ 1397 1398 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1399 TLBMISS_HANDLER_SETUP(); 1400 1401 atomic_inc(&init_mm.mm_count); 1402 current->active_mm = &init_mm; 1403 BUG_ON(current->mm); 1404 enter_lazy_tlb(&init_mm, current); 1405 1406 #ifdef CONFIG_MIPS_MT_SMTC 1407 if (bootTC) { 1408 #endif /* CONFIG_MIPS_MT_SMTC */ 1409 cpu_cache_init(); 1410 tlb_init(); 1411 #ifdef CONFIG_MIPS_MT_SMTC 1412 } 1413 #endif /* CONFIG_MIPS_MT_SMTC */ 1414 } 1415 1416 /* Install CPU exception handler */ 1417 void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1418 { 1419 memcpy((void *)(ebase + offset), addr, size); 1420 flush_icache_range(ebase + offset, ebase + offset + size); 1421 } 1422 1423 /* Install uncached CPU exception handler */ 1424 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1425 { 1426 #ifdef CONFIG_32BIT 1427 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1428 #endif 1429 #ifdef CONFIG_64BIT 1430 unsigned long uncached_ebase = TO_UNCAC(ebase); 1431 #endif 1432 1433 memcpy((void *)(uncached_ebase + offset), addr, size); 1434 } 1435 1436 static int __initdata rdhwr_noopt; 1437 static int __init set_rdhwr_noopt(char *str) 1438 { 1439 rdhwr_noopt = 1; 1440 return 1; 1441 } 1442 1443 __setup("rdhwr_noopt", set_rdhwr_noopt); 1444 1445 void __init trap_init(void) 1446 { 1447 extern char except_vec3_generic, except_vec3_r4000; 1448 extern char except_vec4; 1449 unsigned long i; 1450 1451 if (cpu_has_veic || cpu_has_vint) 1452 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1453 else 1454 ebase = CAC_BASE; 1455 1456 mips_srs_init(); 1457 1458 per_cpu_trap_init(); 1459 1460 /* 1461 * Copy the generic exception handlers to their final destination. 1462 * This will be overriden later as suitable for a particular 1463 * configuration. 1464 */ 1465 set_handler(0x180, &except_vec3_generic, 0x80); 1466 1467 /* 1468 * Setup default vectors 1469 */ 1470 for (i = 0; i <= 31; i++) 1471 set_except_vector(i, handle_reserved); 1472 1473 /* 1474 * Copy the EJTAG debug exception vector handler code to it's final 1475 * destination. 1476 */ 1477 if (cpu_has_ejtag && board_ejtag_handler_setup) 1478 board_ejtag_handler_setup (); 1479 1480 /* 1481 * Only some CPUs have the watch exceptions. 1482 */ 1483 if (cpu_has_watch) 1484 set_except_vector(23, handle_watch); 1485 1486 /* 1487 * Initialise interrupt handlers 1488 */ 1489 if (cpu_has_veic || cpu_has_vint) { 1490 int nvec = cpu_has_veic ? 64 : 8; 1491 for (i = 0; i < nvec; i++) 1492 set_vi_handler(i, NULL); 1493 } 1494 else if (cpu_has_divec) 1495 set_handler(0x200, &except_vec4, 0x8); 1496 1497 /* 1498 * Some CPUs can enable/disable for cache parity detection, but does 1499 * it different ways. 1500 */ 1501 parity_protection_init(); 1502 1503 /* 1504 * The Data Bus Errors / Instruction Bus Errors are signaled 1505 * by external hardware. Therefore these two exceptions 1506 * may have board specific handlers. 1507 */ 1508 if (board_be_init) 1509 board_be_init(); 1510 1511 set_except_vector(0, handle_int); 1512 set_except_vector(1, handle_tlbm); 1513 set_except_vector(2, handle_tlbl); 1514 set_except_vector(3, handle_tlbs); 1515 1516 set_except_vector(4, handle_adel); 1517 set_except_vector(5, handle_ades); 1518 1519 set_except_vector(6, handle_ibe); 1520 set_except_vector(7, handle_dbe); 1521 1522 set_except_vector(8, handle_sys); 1523 set_except_vector(9, handle_bp); 1524 set_except_vector(10, rdhwr_noopt ? handle_ri : 1525 (cpu_has_vtag_icache ? 1526 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1527 set_except_vector(11, handle_cpu); 1528 set_except_vector(12, handle_ov); 1529 set_except_vector(13, handle_tr); 1530 1531 if (current_cpu_data.cputype == CPU_R6000 || 1532 current_cpu_data.cputype == CPU_R6000A) { 1533 /* 1534 * The R6000 is the only R-series CPU that features a machine 1535 * check exception (similar to the R4000 cache error) and 1536 * unaligned ldc1/sdc1 exception. The handlers have not been 1537 * written yet. Well, anyway there is no R6000 machine on the 1538 * current list of targets for Linux/MIPS. 1539 * (Duh, crap, there is someone with a triple R6k machine) 1540 */ 1541 //set_except_vector(14, handle_mc); 1542 //set_except_vector(15, handle_ndc); 1543 } 1544 1545 1546 if (board_nmi_handler_setup) 1547 board_nmi_handler_setup(); 1548 1549 if (cpu_has_fpu && !cpu_has_nofpuex) 1550 set_except_vector(15, handle_fpe); 1551 1552 set_except_vector(22, handle_mdmx); 1553 1554 if (cpu_has_mcheck) 1555 set_except_vector(24, handle_mcheck); 1556 1557 if (cpu_has_mipsmt) 1558 set_except_vector(25, handle_mt); 1559 1560 if (cpu_has_dsp) 1561 set_except_vector(26, handle_dsp); 1562 1563 if (cpu_has_vce) 1564 /* Special exception: R4[04]00 uses also the divec space. */ 1565 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1566 else if (cpu_has_4kex) 1567 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1568 else 1569 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1570 1571 signal_init(); 1572 #ifdef CONFIG_MIPS32_COMPAT 1573 signal32_init(); 1574 #endif 1575 1576 flush_icache_range(ebase, ebase + 0x400); 1577 flush_tlb_handlers(); 1578 } 1579