1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bug.h> 16 #include <linux/compiler.h> 17 #include <linux/context_tracking.h> 18 #include <linux/cpu_pm.h> 19 #include <linux/kexec.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mm.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/spinlock.h> 27 #include <linux/kallsyms.h> 28 #include <linux/bootmem.h> 29 #include <linux/interrupt.h> 30 #include <linux/ptrace.h> 31 #include <linux/kgdb.h> 32 #include <linux/kdebug.h> 33 #include <linux/kprobes.h> 34 #include <linux/notifier.h> 35 #include <linux/kdb.h> 36 #include <linux/irq.h> 37 #include <linux/perf_event.h> 38 39 #include <asm/bootinfo.h> 40 #include <asm/branch.h> 41 #include <asm/break.h> 42 #include <asm/cop2.h> 43 #include <asm/cpu.h> 44 #include <asm/cpu-type.h> 45 #include <asm/dsp.h> 46 #include <asm/fpu.h> 47 #include <asm/fpu_emulator.h> 48 #include <asm/idle.h> 49 #include <asm/mips-r2-to-r6-emul.h> 50 #include <asm/mipsregs.h> 51 #include <asm/mipsmtregs.h> 52 #include <asm/module.h> 53 #include <asm/msa.h> 54 #include <asm/pgtable.h> 55 #include <asm/ptrace.h> 56 #include <asm/sections.h> 57 #include <asm/tlbdebug.h> 58 #include <asm/traps.h> 59 #include <asm/uaccess.h> 60 #include <asm/watch.h> 61 #include <asm/mmu_context.h> 62 #include <asm/types.h> 63 #include <asm/stacktrace.h> 64 #include <asm/uasm.h> 65 66 extern void check_wait(void); 67 extern asmlinkage void rollback_handle_int(void); 68 extern asmlinkage void handle_int(void); 69 extern u32 handle_tlbl[]; 70 extern u32 handle_tlbs[]; 71 extern u32 handle_tlbm[]; 72 extern asmlinkage void handle_adel(void); 73 extern asmlinkage void handle_ades(void); 74 extern asmlinkage void handle_ibe(void); 75 extern asmlinkage void handle_dbe(void); 76 extern asmlinkage void handle_sys(void); 77 extern asmlinkage void handle_bp(void); 78 extern asmlinkage void handle_ri(void); 79 extern asmlinkage void handle_ri_rdhwr_vivt(void); 80 extern asmlinkage void handle_ri_rdhwr(void); 81 extern asmlinkage void handle_cpu(void); 82 extern asmlinkage void handle_ov(void); 83 extern asmlinkage void handle_tr(void); 84 extern asmlinkage void handle_msa_fpe(void); 85 extern asmlinkage void handle_fpe(void); 86 extern asmlinkage void handle_ftlb(void); 87 extern asmlinkage void handle_msa(void); 88 extern asmlinkage void handle_mdmx(void); 89 extern asmlinkage void handle_watch(void); 90 extern asmlinkage void handle_mt(void); 91 extern asmlinkage void handle_dsp(void); 92 extern asmlinkage void handle_mcheck(void); 93 extern asmlinkage void handle_reserved(void); 94 extern void tlb_do_page_fault_0(void); 95 96 void (*board_be_init)(void); 97 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 98 void (*board_nmi_handler_setup)(void); 99 void (*board_ejtag_handler_setup)(void); 100 void (*board_bind_eic_interrupt)(int irq, int regset); 101 void (*board_ebase_setup)(void); 102 void(*board_cache_error_setup)(void); 103 104 static void show_raw_backtrace(unsigned long reg29) 105 { 106 unsigned long *sp = (unsigned long *)(reg29 & ~3); 107 unsigned long addr; 108 109 printk("Call Trace:"); 110 #ifdef CONFIG_KALLSYMS 111 printk("\n"); 112 #endif 113 while (!kstack_end(sp)) { 114 unsigned long __user *p = 115 (unsigned long __user *)(unsigned long)sp++; 116 if (__get_user(addr, p)) { 117 printk(" (Bad stack address)"); 118 break; 119 } 120 if (__kernel_text_address(addr)) 121 print_ip_sym(addr); 122 } 123 printk("\n"); 124 } 125 126 #ifdef CONFIG_KALLSYMS 127 int raw_show_trace; 128 static int __init set_raw_show_trace(char *str) 129 { 130 raw_show_trace = 1; 131 return 1; 132 } 133 __setup("raw_show_trace", set_raw_show_trace); 134 #endif 135 136 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 137 { 138 unsigned long sp = regs->regs[29]; 139 unsigned long ra = regs->regs[31]; 140 unsigned long pc = regs->cp0_epc; 141 142 if (!task) 143 task = current; 144 145 if (raw_show_trace || !__kernel_text_address(pc)) { 146 show_raw_backtrace(sp); 147 return; 148 } 149 printk("Call Trace:\n"); 150 do { 151 print_ip_sym(pc); 152 pc = unwind_stack(task, &sp, pc, &ra); 153 } while (pc); 154 printk("\n"); 155 } 156 157 /* 158 * This routine abuses get_user()/put_user() to reference pointers 159 * with at least a bit of error checking ... 160 */ 161 static void show_stacktrace(struct task_struct *task, 162 const struct pt_regs *regs) 163 { 164 const int field = 2 * sizeof(unsigned long); 165 long stackdata; 166 int i; 167 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 168 169 printk("Stack :"); 170 i = 0; 171 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 172 if (i && ((i % (64 / field)) == 0)) 173 printk("\n "); 174 if (i > 39) { 175 printk(" ..."); 176 break; 177 } 178 179 if (__get_user(stackdata, sp++)) { 180 printk(" (Bad stack address)"); 181 break; 182 } 183 184 printk(" %0*lx", field, stackdata); 185 i++; 186 } 187 printk("\n"); 188 show_backtrace(task, regs); 189 } 190 191 void show_stack(struct task_struct *task, unsigned long *sp) 192 { 193 struct pt_regs regs; 194 if (sp) { 195 regs.regs[29] = (unsigned long)sp; 196 regs.regs[31] = 0; 197 regs.cp0_epc = 0; 198 } else { 199 if (task && task != current) { 200 regs.regs[29] = task->thread.reg29; 201 regs.regs[31] = 0; 202 regs.cp0_epc = task->thread.reg31; 203 #ifdef CONFIG_KGDB_KDB 204 } else if (atomic_read(&kgdb_active) != -1 && 205 kdb_current_regs) { 206 memcpy(®s, kdb_current_regs, sizeof(regs)); 207 #endif /* CONFIG_KGDB_KDB */ 208 } else { 209 prepare_frametrace(®s); 210 } 211 } 212 show_stacktrace(task, ®s); 213 } 214 215 static void show_code(unsigned int __user *pc) 216 { 217 long i; 218 unsigned short __user *pc16 = NULL; 219 220 printk("\nCode:"); 221 222 if ((unsigned long)pc & 1) 223 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 224 for(i = -3 ; i < 6 ; i++) { 225 unsigned int insn; 226 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 227 printk(" (Bad address in epc)\n"); 228 break; 229 } 230 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 231 } 232 } 233 234 static void __show_regs(const struct pt_regs *regs) 235 { 236 const int field = 2 * sizeof(unsigned long); 237 unsigned int cause = regs->cp0_cause; 238 int i; 239 240 show_regs_print_info(KERN_DEFAULT); 241 242 /* 243 * Saved main processor registers 244 */ 245 for (i = 0; i < 32; ) { 246 if ((i % 4) == 0) 247 printk("$%2d :", i); 248 if (i == 0) 249 printk(" %0*lx", field, 0UL); 250 else if (i == 26 || i == 27) 251 printk(" %*s", field, ""); 252 else 253 printk(" %0*lx", field, regs->regs[i]); 254 255 i++; 256 if ((i % 4) == 0) 257 printk("\n"); 258 } 259 260 #ifdef CONFIG_CPU_HAS_SMARTMIPS 261 printk("Acx : %0*lx\n", field, regs->acx); 262 #endif 263 printk("Hi : %0*lx\n", field, regs->hi); 264 printk("Lo : %0*lx\n", field, regs->lo); 265 266 /* 267 * Saved cp0 registers 268 */ 269 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 270 (void *) regs->cp0_epc); 271 printk(" %s\n", print_tainted()); 272 printk("ra : %0*lx %pS\n", field, regs->regs[31], 273 (void *) regs->regs[31]); 274 275 printk("Status: %08x ", (uint32_t) regs->cp0_status); 276 277 if (cpu_has_3kex) { 278 if (regs->cp0_status & ST0_KUO) 279 printk("KUo "); 280 if (regs->cp0_status & ST0_IEO) 281 printk("IEo "); 282 if (regs->cp0_status & ST0_KUP) 283 printk("KUp "); 284 if (regs->cp0_status & ST0_IEP) 285 printk("IEp "); 286 if (regs->cp0_status & ST0_KUC) 287 printk("KUc "); 288 if (regs->cp0_status & ST0_IEC) 289 printk("IEc "); 290 } else if (cpu_has_4kex) { 291 if (regs->cp0_status & ST0_KX) 292 printk("KX "); 293 if (regs->cp0_status & ST0_SX) 294 printk("SX "); 295 if (regs->cp0_status & ST0_UX) 296 printk("UX "); 297 switch (regs->cp0_status & ST0_KSU) { 298 case KSU_USER: 299 printk("USER "); 300 break; 301 case KSU_SUPERVISOR: 302 printk("SUPERVISOR "); 303 break; 304 case KSU_KERNEL: 305 printk("KERNEL "); 306 break; 307 default: 308 printk("BAD_MODE "); 309 break; 310 } 311 if (regs->cp0_status & ST0_ERL) 312 printk("ERL "); 313 if (regs->cp0_status & ST0_EXL) 314 printk("EXL "); 315 if (regs->cp0_status & ST0_IE) 316 printk("IE "); 317 } 318 printk("\n"); 319 320 printk("Cause : %08x\n", cause); 321 322 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 323 if (1 <= cause && cause <= 5) 324 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 325 326 printk("PrId : %08x (%s)\n", read_c0_prid(), 327 cpu_name_string()); 328 } 329 330 /* 331 * FIXME: really the generic show_regs should take a const pointer argument. 332 */ 333 void show_regs(struct pt_regs *regs) 334 { 335 __show_regs((struct pt_regs *)regs); 336 } 337 338 void show_registers(struct pt_regs *regs) 339 { 340 const int field = 2 * sizeof(unsigned long); 341 mm_segment_t old_fs = get_fs(); 342 343 __show_regs(regs); 344 print_modules(); 345 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 346 current->comm, current->pid, current_thread_info(), current, 347 field, current_thread_info()->tp_value); 348 if (cpu_has_userlocal) { 349 unsigned long tls; 350 351 tls = read_c0_userlocal(); 352 if (tls != current_thread_info()->tp_value) 353 printk("*HwTLS: %0*lx\n", field, tls); 354 } 355 356 if (!user_mode(regs)) 357 /* Necessary for getting the correct stack content */ 358 set_fs(KERNEL_DS); 359 show_stacktrace(current, regs); 360 show_code((unsigned int __user *) regs->cp0_epc); 361 printk("\n"); 362 set_fs(old_fs); 363 } 364 365 static int regs_to_trapnr(struct pt_regs *regs) 366 { 367 return (regs->cp0_cause >> 2) & 0x1f; 368 } 369 370 static DEFINE_RAW_SPINLOCK(die_lock); 371 372 void __noreturn die(const char *str, struct pt_regs *regs) 373 { 374 static int die_counter; 375 int sig = SIGSEGV; 376 377 oops_enter(); 378 379 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), 380 SIGSEGV) == NOTIFY_STOP) 381 sig = 0; 382 383 console_verbose(); 384 raw_spin_lock_irq(&die_lock); 385 bust_spinlocks(1); 386 387 printk("%s[#%d]:\n", str, ++die_counter); 388 show_registers(regs); 389 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 390 raw_spin_unlock_irq(&die_lock); 391 392 oops_exit(); 393 394 if (in_interrupt()) 395 panic("Fatal exception in interrupt"); 396 397 if (panic_on_oops) { 398 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 399 ssleep(5); 400 panic("Fatal exception"); 401 } 402 403 if (regs && kexec_should_crash(current)) 404 crash_kexec(regs); 405 406 do_exit(sig); 407 } 408 409 extern struct exception_table_entry __start___dbe_table[]; 410 extern struct exception_table_entry __stop___dbe_table[]; 411 412 __asm__( 413 " .section __dbe_table, \"a\"\n" 414 " .previous \n"); 415 416 /* Given an address, look for it in the exception tables. */ 417 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 418 { 419 const struct exception_table_entry *e; 420 421 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 422 if (!e) 423 e = search_module_dbetables(addr); 424 return e; 425 } 426 427 asmlinkage void do_be(struct pt_regs *regs) 428 { 429 const int field = 2 * sizeof(unsigned long); 430 const struct exception_table_entry *fixup = NULL; 431 int data = regs->cp0_cause & 4; 432 int action = MIPS_BE_FATAL; 433 enum ctx_state prev_state; 434 435 prev_state = exception_enter(); 436 /* XXX For now. Fixme, this searches the wrong table ... */ 437 if (data && !user_mode(regs)) 438 fixup = search_dbe_tables(exception_epc(regs)); 439 440 if (fixup) 441 action = MIPS_BE_FIXUP; 442 443 if (board_be_handler) 444 action = board_be_handler(regs, fixup != NULL); 445 446 switch (action) { 447 case MIPS_BE_DISCARD: 448 goto out; 449 case MIPS_BE_FIXUP: 450 if (fixup) { 451 regs->cp0_epc = fixup->nextinsn; 452 goto out; 453 } 454 break; 455 default: 456 break; 457 } 458 459 /* 460 * Assume it would be too dangerous to continue ... 461 */ 462 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 463 data ? "Data" : "Instruction", 464 field, regs->cp0_epc, field, regs->regs[31]); 465 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), 466 SIGBUS) == NOTIFY_STOP) 467 goto out; 468 469 die_if_kernel("Oops", regs); 470 force_sig(SIGBUS, current); 471 472 out: 473 exception_exit(prev_state); 474 } 475 476 /* 477 * ll/sc, rdhwr, sync emulation 478 */ 479 480 #define OPCODE 0xfc000000 481 #define BASE 0x03e00000 482 #define RT 0x001f0000 483 #define OFFSET 0x0000ffff 484 #define LL 0xc0000000 485 #define SC 0xe0000000 486 #define SPEC0 0x00000000 487 #define SPEC3 0x7c000000 488 #define RD 0x0000f800 489 #define FUNC 0x0000003f 490 #define SYNC 0x0000000f 491 #define RDHWR 0x0000003b 492 493 /* microMIPS definitions */ 494 #define MM_POOL32A_FUNC 0xfc00ffff 495 #define MM_RDHWR 0x00006b3c 496 #define MM_RS 0x001f0000 497 #define MM_RT 0x03e00000 498 499 /* 500 * The ll_bit is cleared by r*_switch.S 501 */ 502 503 unsigned int ll_bit; 504 struct task_struct *ll_task; 505 506 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 507 { 508 unsigned long value, __user *vaddr; 509 long offset; 510 511 /* 512 * analyse the ll instruction that just caused a ri exception 513 * and put the referenced address to addr. 514 */ 515 516 /* sign extend offset */ 517 offset = opcode & OFFSET; 518 offset <<= 16; 519 offset >>= 16; 520 521 vaddr = (unsigned long __user *) 522 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 523 524 if ((unsigned long)vaddr & 3) 525 return SIGBUS; 526 if (get_user(value, vaddr)) 527 return SIGSEGV; 528 529 preempt_disable(); 530 531 if (ll_task == NULL || ll_task == current) { 532 ll_bit = 1; 533 } else { 534 ll_bit = 0; 535 } 536 ll_task = current; 537 538 preempt_enable(); 539 540 regs->regs[(opcode & RT) >> 16] = value; 541 542 return 0; 543 } 544 545 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 546 { 547 unsigned long __user *vaddr; 548 unsigned long reg; 549 long offset; 550 551 /* 552 * analyse the sc instruction that just caused a ri exception 553 * and put the referenced address to addr. 554 */ 555 556 /* sign extend offset */ 557 offset = opcode & OFFSET; 558 offset <<= 16; 559 offset >>= 16; 560 561 vaddr = (unsigned long __user *) 562 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 563 reg = (opcode & RT) >> 16; 564 565 if ((unsigned long)vaddr & 3) 566 return SIGBUS; 567 568 preempt_disable(); 569 570 if (ll_bit == 0 || ll_task != current) { 571 regs->regs[reg] = 0; 572 preempt_enable(); 573 return 0; 574 } 575 576 preempt_enable(); 577 578 if (put_user(regs->regs[reg], vaddr)) 579 return SIGSEGV; 580 581 regs->regs[reg] = 1; 582 583 return 0; 584 } 585 586 /* 587 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 588 * opcodes are supposed to result in coprocessor unusable exceptions if 589 * executed on ll/sc-less processors. That's the theory. In practice a 590 * few processors such as NEC's VR4100 throw reserved instruction exceptions 591 * instead, so we're doing the emulation thing in both exception handlers. 592 */ 593 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 594 { 595 if ((opcode & OPCODE) == LL) { 596 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 597 1, regs, 0); 598 return simulate_ll(regs, opcode); 599 } 600 if ((opcode & OPCODE) == SC) { 601 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 602 1, regs, 0); 603 return simulate_sc(regs, opcode); 604 } 605 606 return -1; /* Must be something else ... */ 607 } 608 609 /* 610 * Simulate trapping 'rdhwr' instructions to provide user accessible 611 * registers not implemented in hardware. 612 */ 613 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 614 { 615 struct thread_info *ti = task_thread_info(current); 616 617 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 618 1, regs, 0); 619 switch (rd) { 620 case 0: /* CPU number */ 621 regs->regs[rt] = smp_processor_id(); 622 return 0; 623 case 1: /* SYNCI length */ 624 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 625 current_cpu_data.icache.linesz); 626 return 0; 627 case 2: /* Read count register */ 628 regs->regs[rt] = read_c0_count(); 629 return 0; 630 case 3: /* Count register resolution */ 631 switch (current_cpu_type()) { 632 case CPU_20KC: 633 case CPU_25KF: 634 regs->regs[rt] = 1; 635 break; 636 default: 637 regs->regs[rt] = 2; 638 } 639 return 0; 640 case 29: 641 regs->regs[rt] = ti->tp_value; 642 return 0; 643 default: 644 return -1; 645 } 646 } 647 648 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 649 { 650 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 651 int rd = (opcode & RD) >> 11; 652 int rt = (opcode & RT) >> 16; 653 654 simulate_rdhwr(regs, rd, rt); 655 return 0; 656 } 657 658 /* Not ours. */ 659 return -1; 660 } 661 662 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 663 { 664 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 665 int rd = (opcode & MM_RS) >> 16; 666 int rt = (opcode & MM_RT) >> 21; 667 simulate_rdhwr(regs, rd, rt); 668 return 0; 669 } 670 671 /* Not ours. */ 672 return -1; 673 } 674 675 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 676 { 677 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 678 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 679 1, regs, 0); 680 return 0; 681 } 682 683 return -1; /* Must be something else ... */ 684 } 685 686 asmlinkage void do_ov(struct pt_regs *regs) 687 { 688 enum ctx_state prev_state; 689 siginfo_t info; 690 691 prev_state = exception_enter(); 692 die_if_kernel("Integer overflow", regs); 693 694 info.si_code = FPE_INTOVF; 695 info.si_signo = SIGFPE; 696 info.si_errno = 0; 697 info.si_addr = (void __user *) regs->cp0_epc; 698 force_sig_info(SIGFPE, &info, current); 699 exception_exit(prev_state); 700 } 701 702 int process_fpemu_return(int sig, void __user *fault_addr) 703 { 704 /* 705 * We can't allow the emulated instruction to leave any of the cause 706 * bits set in FCSR. If they were then the kernel would take an FP 707 * exception when restoring FP context. 708 */ 709 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 710 711 if (sig == SIGSEGV || sig == SIGBUS) { 712 struct siginfo si = {0}; 713 si.si_addr = fault_addr; 714 si.si_signo = sig; 715 if (sig == SIGSEGV) { 716 down_read(¤t->mm->mmap_sem); 717 if (find_vma(current->mm, (unsigned long)fault_addr)) 718 si.si_code = SEGV_ACCERR; 719 else 720 si.si_code = SEGV_MAPERR; 721 up_read(¤t->mm->mmap_sem); 722 } else { 723 si.si_code = BUS_ADRERR; 724 } 725 force_sig_info(sig, &si, current); 726 return 1; 727 } else if (sig) { 728 force_sig(sig, current); 729 return 1; 730 } else { 731 return 0; 732 } 733 } 734 735 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 736 unsigned long old_epc, unsigned long old_ra) 737 { 738 union mips_instruction inst = { .word = opcode }; 739 void __user *fault_addr = NULL; 740 int sig; 741 742 /* If it's obviously not an FP instruction, skip it */ 743 switch (inst.i_format.opcode) { 744 case cop1_op: 745 case cop1x_op: 746 case lwc1_op: 747 case ldc1_op: 748 case swc1_op: 749 case sdc1_op: 750 break; 751 752 default: 753 return -1; 754 } 755 756 /* 757 * do_ri skipped over the instruction via compute_return_epc, undo 758 * that for the FPU emulator. 759 */ 760 regs->cp0_epc = old_epc; 761 regs->regs[31] = old_ra; 762 763 /* Save the FP context to struct thread_struct */ 764 lose_fpu(1); 765 766 /* Run the emulator */ 767 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 768 &fault_addr); 769 770 /* If something went wrong, signal */ 771 process_fpemu_return(sig, fault_addr); 772 773 /* Restore the hardware register state */ 774 own_fpu(1); 775 776 return 0; 777 } 778 779 /* 780 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 781 */ 782 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 783 { 784 enum ctx_state prev_state; 785 siginfo_t info = {0}; 786 787 prev_state = exception_enter(); 788 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 789 SIGFPE) == NOTIFY_STOP) 790 goto out; 791 792 /* Clear FCSR.Cause before enabling interrupts */ 793 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X); 794 local_irq_enable(); 795 796 die_if_kernel("FP exception in kernel code", regs); 797 798 if (fcr31 & FPU_CSR_UNI_X) { 799 int sig; 800 void __user *fault_addr = NULL; 801 802 /* 803 * Unimplemented operation exception. If we've got the full 804 * software emulator on-board, let's use it... 805 * 806 * Force FPU to dump state into task/thread context. We're 807 * moving a lot of data here for what is probably a single 808 * instruction, but the alternative is to pre-decode the FP 809 * register operands before invoking the emulator, which seems 810 * a bit extreme for what should be an infrequent event. 811 */ 812 /* Ensure 'resume' not overwrite saved fp context again. */ 813 lose_fpu(1); 814 815 /* Run the emulator */ 816 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 817 &fault_addr); 818 819 /* If something went wrong, signal */ 820 process_fpemu_return(sig, fault_addr); 821 822 /* Restore the hardware register state */ 823 own_fpu(1); /* Using the FPU again. */ 824 825 goto out; 826 } else if (fcr31 & FPU_CSR_INV_X) 827 info.si_code = FPE_FLTINV; 828 else if (fcr31 & FPU_CSR_DIV_X) 829 info.si_code = FPE_FLTDIV; 830 else if (fcr31 & FPU_CSR_OVF_X) 831 info.si_code = FPE_FLTOVF; 832 else if (fcr31 & FPU_CSR_UDF_X) 833 info.si_code = FPE_FLTUND; 834 else if (fcr31 & FPU_CSR_INE_X) 835 info.si_code = FPE_FLTRES; 836 else 837 info.si_code = __SI_FAULT; 838 info.si_signo = SIGFPE; 839 info.si_errno = 0; 840 info.si_addr = (void __user *) regs->cp0_epc; 841 force_sig_info(SIGFPE, &info, current); 842 843 out: 844 exception_exit(prev_state); 845 } 846 847 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 848 const char *str) 849 { 850 siginfo_t info; 851 char b[40]; 852 853 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 854 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 855 return; 856 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 857 858 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), 859 SIGTRAP) == NOTIFY_STOP) 860 return; 861 862 /* 863 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 864 * insns, even for trap and break codes that indicate arithmetic 865 * failures. Weird ... 866 * But should we continue the brokenness??? --macro 867 */ 868 switch (code) { 869 case BRK_OVERFLOW: 870 case BRK_DIVZERO: 871 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 872 die_if_kernel(b, regs); 873 if (code == BRK_DIVZERO) 874 info.si_code = FPE_INTDIV; 875 else 876 info.si_code = FPE_INTOVF; 877 info.si_signo = SIGFPE; 878 info.si_errno = 0; 879 info.si_addr = (void __user *) regs->cp0_epc; 880 force_sig_info(SIGFPE, &info, current); 881 break; 882 case BRK_BUG: 883 die_if_kernel("Kernel bug detected", regs); 884 force_sig(SIGTRAP, current); 885 break; 886 case BRK_MEMU: 887 /* 888 * Address errors may be deliberately induced by the FPU 889 * emulator to retake control of the CPU after executing the 890 * instruction in the delay slot of an emulated branch. 891 * 892 * Terminate if exception was recognized as a delay slot return 893 * otherwise handle as normal. 894 */ 895 if (do_dsemulret(regs)) 896 return; 897 898 die_if_kernel("Math emu break/trap", regs); 899 force_sig(SIGTRAP, current); 900 break; 901 default: 902 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 903 die_if_kernel(b, regs); 904 force_sig(SIGTRAP, current); 905 } 906 } 907 908 asmlinkage void do_bp(struct pt_regs *regs) 909 { 910 unsigned int opcode, bcode; 911 enum ctx_state prev_state; 912 unsigned long epc; 913 u16 instr[2]; 914 mm_segment_t seg; 915 916 seg = get_fs(); 917 if (!user_mode(regs)) 918 set_fs(KERNEL_DS); 919 920 prev_state = exception_enter(); 921 if (get_isa16_mode(regs->cp0_epc)) { 922 /* Calculate EPC. */ 923 epc = exception_epc(regs); 924 if (cpu_has_mmips) { 925 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || 926 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) 927 goto out_sigsegv; 928 opcode = (instr[0] << 16) | instr[1]; 929 } else { 930 /* MIPS16e mode */ 931 if (__get_user(instr[0], 932 (u16 __user *)msk_isa16_mode(epc))) 933 goto out_sigsegv; 934 bcode = (instr[0] >> 6) & 0x3f; 935 do_trap_or_bp(regs, bcode, "Break"); 936 goto out; 937 } 938 } else { 939 if (__get_user(opcode, 940 (unsigned int __user *) exception_epc(regs))) 941 goto out_sigsegv; 942 } 943 944 /* 945 * There is the ancient bug in the MIPS assemblers that the break 946 * code starts left to bit 16 instead to bit 6 in the opcode. 947 * Gas is bug-compatible, but not always, grrr... 948 * We handle both cases with a simple heuristics. --macro 949 */ 950 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 951 if (bcode >= (1 << 10)) 952 bcode >>= 10; 953 954 /* 955 * notify the kprobe handlers, if instruction is likely to 956 * pertain to them. 957 */ 958 switch (bcode) { 959 case BRK_KPROBE_BP: 960 if (notify_die(DIE_BREAK, "debug", regs, bcode, 961 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 962 goto out; 963 else 964 break; 965 case BRK_KPROBE_SSTEPBP: 966 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 967 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 968 goto out; 969 else 970 break; 971 default: 972 break; 973 } 974 975 do_trap_or_bp(regs, bcode, "Break"); 976 977 out: 978 set_fs(seg); 979 exception_exit(prev_state); 980 return; 981 982 out_sigsegv: 983 force_sig(SIGSEGV, current); 984 goto out; 985 } 986 987 asmlinkage void do_tr(struct pt_regs *regs) 988 { 989 u32 opcode, tcode = 0; 990 enum ctx_state prev_state; 991 u16 instr[2]; 992 mm_segment_t seg; 993 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 994 995 seg = get_fs(); 996 if (!user_mode(regs)) 997 set_fs(get_ds()); 998 999 prev_state = exception_enter(); 1000 if (get_isa16_mode(regs->cp0_epc)) { 1001 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1002 __get_user(instr[1], (u16 __user *)(epc + 2))) 1003 goto out_sigsegv; 1004 opcode = (instr[0] << 16) | instr[1]; 1005 /* Immediate versions don't provide a code. */ 1006 if (!(opcode & OPCODE)) 1007 tcode = (opcode >> 12) & ((1 << 4) - 1); 1008 } else { 1009 if (__get_user(opcode, (u32 __user *)epc)) 1010 goto out_sigsegv; 1011 /* Immediate versions don't provide a code. */ 1012 if (!(opcode & OPCODE)) 1013 tcode = (opcode >> 6) & ((1 << 10) - 1); 1014 } 1015 1016 do_trap_or_bp(regs, tcode, "Trap"); 1017 1018 out: 1019 set_fs(seg); 1020 exception_exit(prev_state); 1021 return; 1022 1023 out_sigsegv: 1024 force_sig(SIGSEGV, current); 1025 goto out; 1026 } 1027 1028 asmlinkage void do_ri(struct pt_regs *regs) 1029 { 1030 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1031 unsigned long old_epc = regs->cp0_epc; 1032 unsigned long old31 = regs->regs[31]; 1033 enum ctx_state prev_state; 1034 unsigned int opcode = 0; 1035 int status = -1; 1036 1037 /* 1038 * Avoid any kernel code. Just emulate the R2 instruction 1039 * as quickly as possible. 1040 */ 1041 if (mipsr2_emulation && cpu_has_mips_r6 && 1042 likely(user_mode(regs))) { 1043 if (likely(get_user(opcode, epc) >= 0)) { 1044 status = mipsr2_decoder(regs, opcode); 1045 switch (status) { 1046 case 0: 1047 case SIGEMT: 1048 task_thread_info(current)->r2_emul_return = 1; 1049 return; 1050 case SIGILL: 1051 goto no_r2_instr; 1052 default: 1053 process_fpemu_return(status, 1054 ¤t->thread.cp0_baduaddr); 1055 task_thread_info(current)->r2_emul_return = 1; 1056 return; 1057 } 1058 } 1059 } 1060 1061 no_r2_instr: 1062 1063 prev_state = exception_enter(); 1064 1065 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 1066 SIGILL) == NOTIFY_STOP) 1067 goto out; 1068 1069 die_if_kernel("Reserved instruction in kernel code", regs); 1070 1071 if (unlikely(compute_return_epc(regs) < 0)) 1072 goto out; 1073 1074 if (get_isa16_mode(regs->cp0_epc)) { 1075 unsigned short mmop[2] = { 0 }; 1076 1077 if (unlikely(get_user(mmop[0], epc) < 0)) 1078 status = SIGSEGV; 1079 if (unlikely(get_user(mmop[1], epc) < 0)) 1080 status = SIGSEGV; 1081 opcode = (mmop[0] << 16) | mmop[1]; 1082 1083 if (status < 0) 1084 status = simulate_rdhwr_mm(regs, opcode); 1085 } else { 1086 if (unlikely(get_user(opcode, epc) < 0)) 1087 status = SIGSEGV; 1088 1089 if (!cpu_has_llsc && status < 0) 1090 status = simulate_llsc(regs, opcode); 1091 1092 if (status < 0) 1093 status = simulate_rdhwr_normal(regs, opcode); 1094 1095 if (status < 0) 1096 status = simulate_sync(regs, opcode); 1097 1098 if (status < 0) 1099 status = simulate_fp(regs, opcode, old_epc, old31); 1100 } 1101 1102 if (status < 0) 1103 status = SIGILL; 1104 1105 if (unlikely(status > 0)) { 1106 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1107 regs->regs[31] = old31; 1108 force_sig(status, current); 1109 } 1110 1111 out: 1112 exception_exit(prev_state); 1113 } 1114 1115 /* 1116 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1117 * emulated more than some threshold number of instructions, force migration to 1118 * a "CPU" that has FP support. 1119 */ 1120 static void mt_ase_fp_affinity(void) 1121 { 1122 #ifdef CONFIG_MIPS_MT_FPAFF 1123 if (mt_fpemul_threshold > 0 && 1124 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1125 /* 1126 * If there's no FPU present, or if the application has already 1127 * restricted the allowed set to exclude any CPUs with FPUs, 1128 * we'll skip the procedure. 1129 */ 1130 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 1131 cpumask_t tmask; 1132 1133 current->thread.user_cpus_allowed 1134 = current->cpus_allowed; 1135 cpus_and(tmask, current->cpus_allowed, 1136 mt_fpu_cpumask); 1137 set_cpus_allowed_ptr(current, &tmask); 1138 set_thread_flag(TIF_FPUBOUND); 1139 } 1140 } 1141 #endif /* CONFIG_MIPS_MT_FPAFF */ 1142 } 1143 1144 /* 1145 * No lock; only written during early bootup by CPU 0. 1146 */ 1147 static RAW_NOTIFIER_HEAD(cu2_chain); 1148 1149 int __ref register_cu2_notifier(struct notifier_block *nb) 1150 { 1151 return raw_notifier_chain_register(&cu2_chain, nb); 1152 } 1153 1154 int cu2_notifier_call_chain(unsigned long val, void *v) 1155 { 1156 return raw_notifier_call_chain(&cu2_chain, val, v); 1157 } 1158 1159 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1160 void *data) 1161 { 1162 struct pt_regs *regs = data; 1163 1164 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1165 "instruction", regs); 1166 force_sig(SIGILL, current); 1167 1168 return NOTIFY_OK; 1169 } 1170 1171 static int wait_on_fp_mode_switch(atomic_t *p) 1172 { 1173 /* 1174 * The FP mode for this task is currently being switched. That may 1175 * involve modifications to the format of this tasks FP context which 1176 * make it unsafe to proceed with execution for the moment. Instead, 1177 * schedule some other task. 1178 */ 1179 schedule(); 1180 return 0; 1181 } 1182 1183 static int enable_restore_fp_context(int msa) 1184 { 1185 int err, was_fpu_owner, prior_msa; 1186 1187 /* 1188 * If an FP mode switch is currently underway, wait for it to 1189 * complete before proceeding. 1190 */ 1191 wait_on_atomic_t(¤t->mm->context.fp_mode_switching, 1192 wait_on_fp_mode_switch, TASK_KILLABLE); 1193 1194 if (!used_math()) { 1195 /* First time FP context user. */ 1196 preempt_disable(); 1197 err = init_fpu(); 1198 if (msa && !err) { 1199 enable_msa(); 1200 _init_msa_upper(); 1201 set_thread_flag(TIF_USEDMSA); 1202 set_thread_flag(TIF_MSA_CTX_LIVE); 1203 } 1204 preempt_enable(); 1205 if (!err) 1206 set_used_math(); 1207 return err; 1208 } 1209 1210 /* 1211 * This task has formerly used the FP context. 1212 * 1213 * If this thread has no live MSA vector context then we can simply 1214 * restore the scalar FP context. If it has live MSA vector context 1215 * (that is, it has or may have used MSA since last performing a 1216 * function call) then we'll need to restore the vector context. This 1217 * applies even if we're currently only executing a scalar FP 1218 * instruction. This is because if we were to later execute an MSA 1219 * instruction then we'd either have to: 1220 * 1221 * - Restore the vector context & clobber any registers modified by 1222 * scalar FP instructions between now & then. 1223 * 1224 * or 1225 * 1226 * - Not restore the vector context & lose the most significant bits 1227 * of all vector registers. 1228 * 1229 * Neither of those options is acceptable. We cannot restore the least 1230 * significant bits of the registers now & only restore the most 1231 * significant bits later because the most significant bits of any 1232 * vector registers whose aliased FP register is modified now will have 1233 * been zeroed. We'd have no way to know that when restoring the vector 1234 * context & thus may load an outdated value for the most significant 1235 * bits of a vector register. 1236 */ 1237 if (!msa && !thread_msa_context_live()) 1238 return own_fpu(1); 1239 1240 /* 1241 * This task is using or has previously used MSA. Thus we require 1242 * that Status.FR == 1. 1243 */ 1244 preempt_disable(); 1245 was_fpu_owner = is_fpu_owner(); 1246 err = own_fpu_inatomic(0); 1247 if (err) 1248 goto out; 1249 1250 enable_msa(); 1251 write_msa_csr(current->thread.fpu.msacsr); 1252 set_thread_flag(TIF_USEDMSA); 1253 1254 /* 1255 * If this is the first time that the task is using MSA and it has 1256 * previously used scalar FP in this time slice then we already nave 1257 * FP context which we shouldn't clobber. We do however need to clear 1258 * the upper 64b of each vector register so that this task has no 1259 * opportunity to see data left behind by another. 1260 */ 1261 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1262 if (!prior_msa && was_fpu_owner) { 1263 _init_msa_upper(); 1264 1265 goto out; 1266 } 1267 1268 if (!prior_msa) { 1269 /* 1270 * Restore the least significant 64b of each vector register 1271 * from the existing scalar FP context. 1272 */ 1273 _restore_fp(current); 1274 1275 /* 1276 * The task has not formerly used MSA, so clear the upper 64b 1277 * of each vector register such that it cannot see data left 1278 * behind by another task. 1279 */ 1280 _init_msa_upper(); 1281 } else { 1282 /* We need to restore the vector context. */ 1283 restore_msa(current); 1284 1285 /* Restore the scalar FP control & status register */ 1286 if (!was_fpu_owner) 1287 write_32bit_cp1_register(CP1_STATUS, 1288 current->thread.fpu.fcr31); 1289 } 1290 1291 out: 1292 preempt_enable(); 1293 1294 return 0; 1295 } 1296 1297 asmlinkage void do_cpu(struct pt_regs *regs) 1298 { 1299 enum ctx_state prev_state; 1300 unsigned int __user *epc; 1301 unsigned long old_epc, old31; 1302 unsigned int opcode; 1303 unsigned int cpid; 1304 int status, err; 1305 unsigned long __maybe_unused flags; 1306 1307 prev_state = exception_enter(); 1308 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1309 1310 if (cpid != 2) 1311 die_if_kernel("do_cpu invoked from kernel context!", regs); 1312 1313 switch (cpid) { 1314 case 0: 1315 epc = (unsigned int __user *)exception_epc(regs); 1316 old_epc = regs->cp0_epc; 1317 old31 = regs->regs[31]; 1318 opcode = 0; 1319 status = -1; 1320 1321 if (unlikely(compute_return_epc(regs) < 0)) 1322 goto out; 1323 1324 if (get_isa16_mode(regs->cp0_epc)) { 1325 unsigned short mmop[2] = { 0 }; 1326 1327 if (unlikely(get_user(mmop[0], epc) < 0)) 1328 status = SIGSEGV; 1329 if (unlikely(get_user(mmop[1], epc) < 0)) 1330 status = SIGSEGV; 1331 opcode = (mmop[0] << 16) | mmop[1]; 1332 1333 if (status < 0) 1334 status = simulate_rdhwr_mm(regs, opcode); 1335 } else { 1336 if (unlikely(get_user(opcode, epc) < 0)) 1337 status = SIGSEGV; 1338 1339 if (!cpu_has_llsc && status < 0) 1340 status = simulate_llsc(regs, opcode); 1341 1342 if (status < 0) 1343 status = simulate_rdhwr_normal(regs, opcode); 1344 } 1345 1346 if (status < 0) 1347 status = SIGILL; 1348 1349 if (unlikely(status > 0)) { 1350 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1351 regs->regs[31] = old31; 1352 force_sig(status, current); 1353 } 1354 1355 goto out; 1356 1357 case 3: 1358 /* 1359 * Old (MIPS I and MIPS II) processors will set this code 1360 * for COP1X opcode instructions that replaced the original 1361 * COP3 space. We don't limit COP1 space instructions in 1362 * the emulator according to the CPU ISA, so we want to 1363 * treat COP1X instructions consistently regardless of which 1364 * code the CPU chose. Therefore we redirect this trap to 1365 * the FP emulator too. 1366 * 1367 * Then some newer FPU-less processors use this code 1368 * erroneously too, so they are covered by this choice 1369 * as well. 1370 */ 1371 if (raw_cpu_has_fpu) 1372 break; 1373 /* Fall through. */ 1374 1375 case 1: 1376 err = enable_restore_fp_context(0); 1377 1378 if (!raw_cpu_has_fpu || err) { 1379 int sig; 1380 void __user *fault_addr = NULL; 1381 sig = fpu_emulator_cop1Handler(regs, 1382 ¤t->thread.fpu, 1383 0, &fault_addr); 1384 if (!process_fpemu_return(sig, fault_addr) && !err) 1385 mt_ase_fp_affinity(); 1386 } 1387 1388 goto out; 1389 1390 case 2: 1391 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1392 goto out; 1393 } 1394 1395 force_sig(SIGILL, current); 1396 1397 out: 1398 exception_exit(prev_state); 1399 } 1400 1401 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1402 { 1403 enum ctx_state prev_state; 1404 1405 prev_state = exception_enter(); 1406 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1407 regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP) 1408 goto out; 1409 1410 /* Clear MSACSR.Cause before enabling interrupts */ 1411 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1412 local_irq_enable(); 1413 1414 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1415 force_sig(SIGFPE, current); 1416 out: 1417 exception_exit(prev_state); 1418 } 1419 1420 asmlinkage void do_msa(struct pt_regs *regs) 1421 { 1422 enum ctx_state prev_state; 1423 int err; 1424 1425 prev_state = exception_enter(); 1426 1427 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1428 force_sig(SIGILL, current); 1429 goto out; 1430 } 1431 1432 die_if_kernel("do_msa invoked from kernel context!", regs); 1433 1434 err = enable_restore_fp_context(1); 1435 if (err) 1436 force_sig(SIGILL, current); 1437 out: 1438 exception_exit(prev_state); 1439 } 1440 1441 asmlinkage void do_mdmx(struct pt_regs *regs) 1442 { 1443 enum ctx_state prev_state; 1444 1445 prev_state = exception_enter(); 1446 force_sig(SIGILL, current); 1447 exception_exit(prev_state); 1448 } 1449 1450 /* 1451 * Called with interrupts disabled. 1452 */ 1453 asmlinkage void do_watch(struct pt_regs *regs) 1454 { 1455 enum ctx_state prev_state; 1456 u32 cause; 1457 1458 prev_state = exception_enter(); 1459 /* 1460 * Clear WP (bit 22) bit of cause register so we don't loop 1461 * forever. 1462 */ 1463 cause = read_c0_cause(); 1464 cause &= ~(1 << 22); 1465 write_c0_cause(cause); 1466 1467 /* 1468 * If the current thread has the watch registers loaded, save 1469 * their values and send SIGTRAP. Otherwise another thread 1470 * left the registers set, clear them and continue. 1471 */ 1472 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1473 mips_read_watch_registers(); 1474 local_irq_enable(); 1475 force_sig(SIGTRAP, current); 1476 } else { 1477 mips_clear_watch_registers(); 1478 local_irq_enable(); 1479 } 1480 exception_exit(prev_state); 1481 } 1482 1483 asmlinkage void do_mcheck(struct pt_regs *regs) 1484 { 1485 const int field = 2 * sizeof(unsigned long); 1486 int multi_match = regs->cp0_status & ST0_TS; 1487 enum ctx_state prev_state; 1488 1489 prev_state = exception_enter(); 1490 show_regs(regs); 1491 1492 if (multi_match) { 1493 pr_err("Index : %0x\n", read_c0_index()); 1494 pr_err("Pagemask: %0x\n", read_c0_pagemask()); 1495 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1496 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1497 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1498 pr_err("Wired : %0x\n", read_c0_wired()); 1499 pr_err("Pagegrain: %0x\n", read_c0_pagegrain()); 1500 if (cpu_has_htw) { 1501 pr_err("PWField : %0*lx\n", field, read_c0_pwfield()); 1502 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize()); 1503 pr_err("PWCtl : %0x\n", read_c0_pwctl()); 1504 } 1505 pr_err("\n"); 1506 dump_tlb_all(); 1507 } 1508 1509 show_code((unsigned int __user *) regs->cp0_epc); 1510 1511 /* 1512 * Some chips may have other causes of machine check (e.g. SB1 1513 * graduation timer) 1514 */ 1515 panic("Caught Machine Check exception - %scaused by multiple " 1516 "matching entries in the TLB.", 1517 (multi_match) ? "" : "not "); 1518 } 1519 1520 asmlinkage void do_mt(struct pt_regs *regs) 1521 { 1522 int subcode; 1523 1524 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1525 >> VPECONTROL_EXCPT_SHIFT; 1526 switch (subcode) { 1527 case 0: 1528 printk(KERN_DEBUG "Thread Underflow\n"); 1529 break; 1530 case 1: 1531 printk(KERN_DEBUG "Thread Overflow\n"); 1532 break; 1533 case 2: 1534 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1535 break; 1536 case 3: 1537 printk(KERN_DEBUG "Gating Storage Exception\n"); 1538 break; 1539 case 4: 1540 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1541 break; 1542 case 5: 1543 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1544 break; 1545 default: 1546 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1547 subcode); 1548 break; 1549 } 1550 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1551 1552 force_sig(SIGILL, current); 1553 } 1554 1555 1556 asmlinkage void do_dsp(struct pt_regs *regs) 1557 { 1558 if (cpu_has_dsp) 1559 panic("Unexpected DSP exception"); 1560 1561 force_sig(SIGILL, current); 1562 } 1563 1564 asmlinkage void do_reserved(struct pt_regs *regs) 1565 { 1566 /* 1567 * Game over - no way to handle this if it ever occurs. Most probably 1568 * caused by a new unknown cpu type or after another deadly 1569 * hard/software error. 1570 */ 1571 show_regs(regs); 1572 panic("Caught reserved exception %ld - should not happen.", 1573 (regs->cp0_cause & 0x7f) >> 2); 1574 } 1575 1576 static int __initdata l1parity = 1; 1577 static int __init nol1parity(char *s) 1578 { 1579 l1parity = 0; 1580 return 1; 1581 } 1582 __setup("nol1par", nol1parity); 1583 static int __initdata l2parity = 1; 1584 static int __init nol2parity(char *s) 1585 { 1586 l2parity = 0; 1587 return 1; 1588 } 1589 __setup("nol2par", nol2parity); 1590 1591 /* 1592 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1593 * it different ways. 1594 */ 1595 static inline void parity_protection_init(void) 1596 { 1597 switch (current_cpu_type()) { 1598 case CPU_24K: 1599 case CPU_34K: 1600 case CPU_74K: 1601 case CPU_1004K: 1602 case CPU_1074K: 1603 case CPU_INTERAPTIV: 1604 case CPU_PROAPTIV: 1605 case CPU_P5600: 1606 case CPU_QEMU_GENERIC: 1607 { 1608 #define ERRCTL_PE 0x80000000 1609 #define ERRCTL_L2P 0x00800000 1610 unsigned long errctl; 1611 unsigned int l1parity_present, l2parity_present; 1612 1613 errctl = read_c0_ecc(); 1614 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1615 1616 /* probe L1 parity support */ 1617 write_c0_ecc(errctl | ERRCTL_PE); 1618 back_to_back_c0_hazard(); 1619 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1620 1621 /* probe L2 parity support */ 1622 write_c0_ecc(errctl|ERRCTL_L2P); 1623 back_to_back_c0_hazard(); 1624 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1625 1626 if (l1parity_present && l2parity_present) { 1627 if (l1parity) 1628 errctl |= ERRCTL_PE; 1629 if (l1parity ^ l2parity) 1630 errctl |= ERRCTL_L2P; 1631 } else if (l1parity_present) { 1632 if (l1parity) 1633 errctl |= ERRCTL_PE; 1634 } else if (l2parity_present) { 1635 if (l2parity) 1636 errctl |= ERRCTL_L2P; 1637 } else { 1638 /* No parity available */ 1639 } 1640 1641 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1642 1643 write_c0_ecc(errctl); 1644 back_to_back_c0_hazard(); 1645 errctl = read_c0_ecc(); 1646 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1647 1648 if (l1parity_present) 1649 printk(KERN_INFO "Cache parity protection %sabled\n", 1650 (errctl & ERRCTL_PE) ? "en" : "dis"); 1651 1652 if (l2parity_present) { 1653 if (l1parity_present && l1parity) 1654 errctl ^= ERRCTL_L2P; 1655 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1656 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1657 } 1658 } 1659 break; 1660 1661 case CPU_5KC: 1662 case CPU_5KE: 1663 case CPU_LOONGSON1: 1664 write_c0_ecc(0x80000000); 1665 back_to_back_c0_hazard(); 1666 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1667 printk(KERN_INFO "Cache parity protection %sabled\n", 1668 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1669 break; 1670 case CPU_20KC: 1671 case CPU_25KF: 1672 /* Clear the DE bit (bit 16) in the c0_status register. */ 1673 printk(KERN_INFO "Enable cache parity protection for " 1674 "MIPS 20KC/25KF CPUs.\n"); 1675 clear_c0_status(ST0_DE); 1676 break; 1677 default: 1678 break; 1679 } 1680 } 1681 1682 asmlinkage void cache_parity_error(void) 1683 { 1684 const int field = 2 * sizeof(unsigned long); 1685 unsigned int reg_val; 1686 1687 /* For the moment, report the problem and hang. */ 1688 printk("Cache error exception:\n"); 1689 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1690 reg_val = read_c0_cacheerr(); 1691 printk("c0_cacheerr == %08x\n", reg_val); 1692 1693 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1694 reg_val & (1<<30) ? "secondary" : "primary", 1695 reg_val & (1<<31) ? "data" : "insn"); 1696 if ((cpu_has_mips_r2_r6) && 1697 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1698 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1699 reg_val & (1<<29) ? "ED " : "", 1700 reg_val & (1<<28) ? "ET " : "", 1701 reg_val & (1<<27) ? "ES " : "", 1702 reg_val & (1<<26) ? "EE " : "", 1703 reg_val & (1<<25) ? "EB " : "", 1704 reg_val & (1<<24) ? "EI " : "", 1705 reg_val & (1<<23) ? "E1 " : "", 1706 reg_val & (1<<22) ? "E0 " : ""); 1707 } else { 1708 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1709 reg_val & (1<<29) ? "ED " : "", 1710 reg_val & (1<<28) ? "ET " : "", 1711 reg_val & (1<<26) ? "EE " : "", 1712 reg_val & (1<<25) ? "EB " : "", 1713 reg_val & (1<<24) ? "EI " : "", 1714 reg_val & (1<<23) ? "E1 " : "", 1715 reg_val & (1<<22) ? "E0 " : ""); 1716 } 1717 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1718 1719 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1720 if (reg_val & (1<<22)) 1721 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1722 1723 if (reg_val & (1<<23)) 1724 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1725 #endif 1726 1727 panic("Can't handle the cache error!"); 1728 } 1729 1730 asmlinkage void do_ftlb(void) 1731 { 1732 const int field = 2 * sizeof(unsigned long); 1733 unsigned int reg_val; 1734 1735 /* For the moment, report the problem and hang. */ 1736 if ((cpu_has_mips_r2_r6) && 1737 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1738 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1739 read_c0_ecc()); 1740 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1741 reg_val = read_c0_cacheerr(); 1742 pr_err("c0_cacheerr == %08x\n", reg_val); 1743 1744 if ((reg_val & 0xc0000000) == 0xc0000000) { 1745 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1746 } else { 1747 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1748 reg_val & (1<<30) ? "secondary" : "primary", 1749 reg_val & (1<<31) ? "data" : "insn"); 1750 } 1751 } else { 1752 pr_err("FTLB error exception\n"); 1753 } 1754 /* Just print the cacheerr bits for now */ 1755 cache_parity_error(); 1756 } 1757 1758 /* 1759 * SDBBP EJTAG debug exception handler. 1760 * We skip the instruction and return to the next instruction. 1761 */ 1762 void ejtag_exception_handler(struct pt_regs *regs) 1763 { 1764 const int field = 2 * sizeof(unsigned long); 1765 unsigned long depc, old_epc, old_ra; 1766 unsigned int debug; 1767 1768 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1769 depc = read_c0_depc(); 1770 debug = read_c0_debug(); 1771 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1772 if (debug & 0x80000000) { 1773 /* 1774 * In branch delay slot. 1775 * We cheat a little bit here and use EPC to calculate the 1776 * debug return address (DEPC). EPC is restored after the 1777 * calculation. 1778 */ 1779 old_epc = regs->cp0_epc; 1780 old_ra = regs->regs[31]; 1781 regs->cp0_epc = depc; 1782 compute_return_epc(regs); 1783 depc = regs->cp0_epc; 1784 regs->cp0_epc = old_epc; 1785 regs->regs[31] = old_ra; 1786 } else 1787 depc += 4; 1788 write_c0_depc(depc); 1789 1790 #if 0 1791 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1792 write_c0_debug(debug | 0x100); 1793 #endif 1794 } 1795 1796 /* 1797 * NMI exception handler. 1798 * No lock; only written during early bootup by CPU 0. 1799 */ 1800 static RAW_NOTIFIER_HEAD(nmi_chain); 1801 1802 int register_nmi_notifier(struct notifier_block *nb) 1803 { 1804 return raw_notifier_chain_register(&nmi_chain, nb); 1805 } 1806 1807 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1808 { 1809 char str[100]; 1810 1811 raw_notifier_call_chain(&nmi_chain, 0, regs); 1812 bust_spinlocks(1); 1813 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1814 smp_processor_id(), regs->cp0_epc); 1815 regs->cp0_epc = read_c0_errorepc(); 1816 die(str, regs); 1817 } 1818 1819 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1820 1821 unsigned long ebase; 1822 unsigned long exception_handlers[32]; 1823 unsigned long vi_handlers[64]; 1824 1825 void __init *set_except_vector(int n, void *addr) 1826 { 1827 unsigned long handler = (unsigned long) addr; 1828 unsigned long old_handler; 1829 1830 #ifdef CONFIG_CPU_MICROMIPS 1831 /* 1832 * Only the TLB handlers are cache aligned with an even 1833 * address. All other handlers are on an odd address and 1834 * require no modification. Otherwise, MIPS32 mode will 1835 * be entered when handling any TLB exceptions. That 1836 * would be bad...since we must stay in microMIPS mode. 1837 */ 1838 if (!(handler & 0x1)) 1839 handler |= 1; 1840 #endif 1841 old_handler = xchg(&exception_handlers[n], handler); 1842 1843 if (n == 0 && cpu_has_divec) { 1844 #ifdef CONFIG_CPU_MICROMIPS 1845 unsigned long jump_mask = ~((1 << 27) - 1); 1846 #else 1847 unsigned long jump_mask = ~((1 << 28) - 1); 1848 #endif 1849 u32 *buf = (u32 *)(ebase + 0x200); 1850 unsigned int k0 = 26; 1851 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1852 uasm_i_j(&buf, handler & ~jump_mask); 1853 uasm_i_nop(&buf); 1854 } else { 1855 UASM_i_LA(&buf, k0, handler); 1856 uasm_i_jr(&buf, k0); 1857 uasm_i_nop(&buf); 1858 } 1859 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1860 } 1861 return (void *)old_handler; 1862 } 1863 1864 static void do_default_vi(void) 1865 { 1866 show_regs(get_irq_regs()); 1867 panic("Caught unexpected vectored interrupt."); 1868 } 1869 1870 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1871 { 1872 unsigned long handler; 1873 unsigned long old_handler = vi_handlers[n]; 1874 int srssets = current_cpu_data.srsets; 1875 u16 *h; 1876 unsigned char *b; 1877 1878 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1879 1880 if (addr == NULL) { 1881 handler = (unsigned long) do_default_vi; 1882 srs = 0; 1883 } else 1884 handler = (unsigned long) addr; 1885 vi_handlers[n] = handler; 1886 1887 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1888 1889 if (srs >= srssets) 1890 panic("Shadow register set %d not supported", srs); 1891 1892 if (cpu_has_veic) { 1893 if (board_bind_eic_interrupt) 1894 board_bind_eic_interrupt(n, srs); 1895 } else if (cpu_has_vint) { 1896 /* SRSMap is only defined if shadow sets are implemented */ 1897 if (srssets > 1) 1898 change_c0_srsmap(0xf << n*4, srs << n*4); 1899 } 1900 1901 if (srs == 0) { 1902 /* 1903 * If no shadow set is selected then use the default handler 1904 * that does normal register saving and standard interrupt exit 1905 */ 1906 extern char except_vec_vi, except_vec_vi_lui; 1907 extern char except_vec_vi_ori, except_vec_vi_end; 1908 extern char rollback_except_vec_vi; 1909 char *vec_start = using_rollback_handler() ? 1910 &rollback_except_vec_vi : &except_vec_vi; 1911 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1912 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1913 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1914 #else 1915 const int lui_offset = &except_vec_vi_lui - vec_start; 1916 const int ori_offset = &except_vec_vi_ori - vec_start; 1917 #endif 1918 const int handler_len = &except_vec_vi_end - vec_start; 1919 1920 if (handler_len > VECTORSPACING) { 1921 /* 1922 * Sigh... panicing won't help as the console 1923 * is probably not configured :( 1924 */ 1925 panic("VECTORSPACING too small"); 1926 } 1927 1928 set_handler(((unsigned long)b - ebase), vec_start, 1929 #ifdef CONFIG_CPU_MICROMIPS 1930 (handler_len - 1)); 1931 #else 1932 handler_len); 1933 #endif 1934 h = (u16 *)(b + lui_offset); 1935 *h = (handler >> 16) & 0xffff; 1936 h = (u16 *)(b + ori_offset); 1937 *h = (handler & 0xffff); 1938 local_flush_icache_range((unsigned long)b, 1939 (unsigned long)(b+handler_len)); 1940 } 1941 else { 1942 /* 1943 * In other cases jump directly to the interrupt handler. It 1944 * is the handler's responsibility to save registers if required 1945 * (eg hi/lo) and return from the exception using "eret". 1946 */ 1947 u32 insn; 1948 1949 h = (u16 *)b; 1950 /* j handler */ 1951 #ifdef CONFIG_CPU_MICROMIPS 1952 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 1953 #else 1954 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 1955 #endif 1956 h[0] = (insn >> 16) & 0xffff; 1957 h[1] = insn & 0xffff; 1958 h[2] = 0; 1959 h[3] = 0; 1960 local_flush_icache_range((unsigned long)b, 1961 (unsigned long)(b+8)); 1962 } 1963 1964 return (void *)old_handler; 1965 } 1966 1967 void *set_vi_handler(int n, vi_handler_t addr) 1968 { 1969 return set_vi_srs_handler(n, addr, 0); 1970 } 1971 1972 extern void tlb_init(void); 1973 1974 /* 1975 * Timer interrupt 1976 */ 1977 int cp0_compare_irq; 1978 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1979 int cp0_compare_irq_shift; 1980 1981 /* 1982 * Performance counter IRQ or -1 if shared with timer 1983 */ 1984 int cp0_perfcount_irq; 1985 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1986 1987 static int noulri; 1988 1989 static int __init ulri_disable(char *s) 1990 { 1991 pr_info("Disabling ulri\n"); 1992 noulri = 1; 1993 1994 return 1; 1995 } 1996 __setup("noulri", ulri_disable); 1997 1998 /* configure STATUS register */ 1999 static void configure_status(void) 2000 { 2001 /* 2002 * Disable coprocessors and select 32-bit or 64-bit addressing 2003 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2004 * flag that some firmware may have left set and the TS bit (for 2005 * IP27). Set XX for ISA IV code to work. 2006 */ 2007 unsigned int status_set = ST0_CU0; 2008 #ifdef CONFIG_64BIT 2009 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2010 #endif 2011 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2012 status_set |= ST0_XX; 2013 if (cpu_has_dsp) 2014 status_set |= ST0_MX; 2015 2016 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2017 status_set); 2018 } 2019 2020 /* configure HWRENA register */ 2021 static void configure_hwrena(void) 2022 { 2023 unsigned int hwrena = cpu_hwrena_impl_bits; 2024 2025 if (cpu_has_mips_r2_r6) 2026 hwrena |= 0x0000000f; 2027 2028 if (!noulri && cpu_has_userlocal) 2029 hwrena |= (1 << 29); 2030 2031 if (hwrena) 2032 write_c0_hwrena(hwrena); 2033 } 2034 2035 static void configure_exception_vector(void) 2036 { 2037 if (cpu_has_veic || cpu_has_vint) { 2038 unsigned long sr = set_c0_status(ST0_BEV); 2039 write_c0_ebase(ebase); 2040 write_c0_status(sr); 2041 /* Setting vector spacing enables EI/VI mode */ 2042 change_c0_intctl(0x3e0, VECTORSPACING); 2043 } 2044 if (cpu_has_divec) { 2045 if (cpu_has_mipsmt) { 2046 unsigned int vpflags = dvpe(); 2047 set_c0_cause(CAUSEF_IV); 2048 evpe(vpflags); 2049 } else 2050 set_c0_cause(CAUSEF_IV); 2051 } 2052 } 2053 2054 void per_cpu_trap_init(bool is_boot_cpu) 2055 { 2056 unsigned int cpu = smp_processor_id(); 2057 2058 configure_status(); 2059 configure_hwrena(); 2060 2061 configure_exception_vector(); 2062 2063 /* 2064 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2065 * 2066 * o read IntCtl.IPTI to determine the timer interrupt 2067 * o read IntCtl.IPPCI to determine the performance counter interrupt 2068 */ 2069 if (cpu_has_mips_r2_r6) { 2070 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2071 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2072 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2073 if (cp0_perfcount_irq == cp0_compare_irq) 2074 cp0_perfcount_irq = -1; 2075 } else { 2076 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2077 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2078 cp0_perfcount_irq = -1; 2079 } 2080 2081 if (!cpu_data[cpu].asid_cache) 2082 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 2083 2084 atomic_inc(&init_mm.mm_count); 2085 current->active_mm = &init_mm; 2086 BUG_ON(current->mm); 2087 enter_lazy_tlb(&init_mm, current); 2088 2089 /* Boot CPU's cache setup in setup_arch(). */ 2090 if (!is_boot_cpu) 2091 cpu_cache_init(); 2092 tlb_init(); 2093 TLBMISS_HANDLER_SETUP(); 2094 } 2095 2096 /* Install CPU exception handler */ 2097 void set_handler(unsigned long offset, void *addr, unsigned long size) 2098 { 2099 #ifdef CONFIG_CPU_MICROMIPS 2100 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2101 #else 2102 memcpy((void *)(ebase + offset), addr, size); 2103 #endif 2104 local_flush_icache_range(ebase + offset, ebase + offset + size); 2105 } 2106 2107 static char panic_null_cerr[] = 2108 "Trying to set NULL cache error exception handler"; 2109 2110 /* 2111 * Install uncached CPU exception handler. 2112 * This is suitable only for the cache error exception which is the only 2113 * exception handler that is being run uncached. 2114 */ 2115 void set_uncached_handler(unsigned long offset, void *addr, 2116 unsigned long size) 2117 { 2118 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2119 2120 if (!addr) 2121 panic(panic_null_cerr); 2122 2123 memcpy((void *)(uncached_ebase + offset), addr, size); 2124 } 2125 2126 static int __initdata rdhwr_noopt; 2127 static int __init set_rdhwr_noopt(char *str) 2128 { 2129 rdhwr_noopt = 1; 2130 return 1; 2131 } 2132 2133 __setup("rdhwr_noopt", set_rdhwr_noopt); 2134 2135 void __init trap_init(void) 2136 { 2137 extern char except_vec3_generic; 2138 extern char except_vec4; 2139 extern char except_vec3_r4000; 2140 unsigned long i; 2141 2142 check_wait(); 2143 2144 #if defined(CONFIG_KGDB) 2145 if (kgdb_early_setup) 2146 return; /* Already done */ 2147 #endif 2148 2149 if (cpu_has_veic || cpu_has_vint) { 2150 unsigned long size = 0x200 + VECTORSPACING*64; 2151 ebase = (unsigned long) 2152 __alloc_bootmem(size, 1 << fls(size), 0); 2153 } else { 2154 #ifdef CONFIG_KVM_GUEST 2155 #define KVM_GUEST_KSEG0 0x40000000 2156 ebase = KVM_GUEST_KSEG0; 2157 #else 2158 ebase = CKSEG0; 2159 #endif 2160 if (cpu_has_mips_r2_r6) 2161 ebase += (read_c0_ebase() & 0x3ffff000); 2162 } 2163 2164 if (cpu_has_mmips) { 2165 unsigned int config3 = read_c0_config3(); 2166 2167 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2168 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2169 else 2170 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2171 } 2172 2173 if (board_ebase_setup) 2174 board_ebase_setup(); 2175 per_cpu_trap_init(true); 2176 2177 /* 2178 * Copy the generic exception handlers to their final destination. 2179 * This will be overriden later as suitable for a particular 2180 * configuration. 2181 */ 2182 set_handler(0x180, &except_vec3_generic, 0x80); 2183 2184 /* 2185 * Setup default vectors 2186 */ 2187 for (i = 0; i <= 31; i++) 2188 set_except_vector(i, handle_reserved); 2189 2190 /* 2191 * Copy the EJTAG debug exception vector handler code to it's final 2192 * destination. 2193 */ 2194 if (cpu_has_ejtag && board_ejtag_handler_setup) 2195 board_ejtag_handler_setup(); 2196 2197 /* 2198 * Only some CPUs have the watch exceptions. 2199 */ 2200 if (cpu_has_watch) 2201 set_except_vector(23, handle_watch); 2202 2203 /* 2204 * Initialise interrupt handlers 2205 */ 2206 if (cpu_has_veic || cpu_has_vint) { 2207 int nvec = cpu_has_veic ? 64 : 8; 2208 for (i = 0; i < nvec; i++) 2209 set_vi_handler(i, NULL); 2210 } 2211 else if (cpu_has_divec) 2212 set_handler(0x200, &except_vec4, 0x8); 2213 2214 /* 2215 * Some CPUs can enable/disable for cache parity detection, but does 2216 * it different ways. 2217 */ 2218 parity_protection_init(); 2219 2220 /* 2221 * The Data Bus Errors / Instruction Bus Errors are signaled 2222 * by external hardware. Therefore these two exceptions 2223 * may have board specific handlers. 2224 */ 2225 if (board_be_init) 2226 board_be_init(); 2227 2228 set_except_vector(0, using_rollback_handler() ? rollback_handle_int 2229 : handle_int); 2230 set_except_vector(1, handle_tlbm); 2231 set_except_vector(2, handle_tlbl); 2232 set_except_vector(3, handle_tlbs); 2233 2234 set_except_vector(4, handle_adel); 2235 set_except_vector(5, handle_ades); 2236 2237 set_except_vector(6, handle_ibe); 2238 set_except_vector(7, handle_dbe); 2239 2240 set_except_vector(8, handle_sys); 2241 set_except_vector(9, handle_bp); 2242 set_except_vector(10, rdhwr_noopt ? handle_ri : 2243 (cpu_has_vtag_icache ? 2244 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 2245 set_except_vector(11, handle_cpu); 2246 set_except_vector(12, handle_ov); 2247 set_except_vector(13, handle_tr); 2248 set_except_vector(14, handle_msa_fpe); 2249 2250 if (current_cpu_type() == CPU_R6000 || 2251 current_cpu_type() == CPU_R6000A) { 2252 /* 2253 * The R6000 is the only R-series CPU that features a machine 2254 * check exception (similar to the R4000 cache error) and 2255 * unaligned ldc1/sdc1 exception. The handlers have not been 2256 * written yet. Well, anyway there is no R6000 machine on the 2257 * current list of targets for Linux/MIPS. 2258 * (Duh, crap, there is someone with a triple R6k machine) 2259 */ 2260 //set_except_vector(14, handle_mc); 2261 //set_except_vector(15, handle_ndc); 2262 } 2263 2264 2265 if (board_nmi_handler_setup) 2266 board_nmi_handler_setup(); 2267 2268 if (cpu_has_fpu && !cpu_has_nofpuex) 2269 set_except_vector(15, handle_fpe); 2270 2271 set_except_vector(16, handle_ftlb); 2272 2273 if (cpu_has_rixiex) { 2274 set_except_vector(19, tlb_do_page_fault_0); 2275 set_except_vector(20, tlb_do_page_fault_0); 2276 } 2277 2278 set_except_vector(21, handle_msa); 2279 set_except_vector(22, handle_mdmx); 2280 2281 if (cpu_has_mcheck) 2282 set_except_vector(24, handle_mcheck); 2283 2284 if (cpu_has_mipsmt) 2285 set_except_vector(25, handle_mt); 2286 2287 set_except_vector(26, handle_dsp); 2288 2289 if (board_cache_error_setup) 2290 board_cache_error_setup(); 2291 2292 if (cpu_has_vce) 2293 /* Special exception: R4[04]00 uses also the divec space. */ 2294 set_handler(0x180, &except_vec3_r4000, 0x100); 2295 else if (cpu_has_4kex) 2296 set_handler(0x180, &except_vec3_generic, 0x80); 2297 else 2298 set_handler(0x080, &except_vec3_generic, 0x80); 2299 2300 local_flush_icache_range(ebase, ebase + 0x400); 2301 2302 sort_extable(__start___dbe_table, __stop___dbe_table); 2303 2304 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2305 } 2306 2307 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2308 void *v) 2309 { 2310 switch (cmd) { 2311 case CPU_PM_ENTER_FAILED: 2312 case CPU_PM_EXIT: 2313 configure_status(); 2314 configure_hwrena(); 2315 configure_exception_vector(); 2316 2317 /* Restore register with CPU number for TLB handlers */ 2318 TLBMISS_HANDLER_RESTORE(); 2319 2320 break; 2321 } 2322 2323 return NOTIFY_OK; 2324 } 2325 2326 static struct notifier_block trap_pm_notifier_block = { 2327 .notifier_call = trap_pm_notifier, 2328 }; 2329 2330 static int __init trap_pm_init(void) 2331 { 2332 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2333 } 2334 arch_initcall(trap_pm_init); 2335