xref: /linux/arch/mips/kernel/head.S (revision 2b8232ce512105e28453f301d1510de8363bccd1) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
15 */
16#include <linux/init.h>
17#include <linux/threads.h>
18
19#include <asm/addrspace.h>
20#include <asm/asm.h>
21#include <asm/asmmacro.h>
22#include <asm/irqflags.h>
23#include <asm/regdef.h>
24#include <asm/page.h>
25#include <asm/mipsregs.h>
26#include <asm/stackframe.h>
27
28#include <kernel-entry-init.h>
29
30	.macro	ARC64_TWIDDLE_PC
31#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
32	/* We get launched at a XKPHYS address but the kernel is linked to
33	   run at a KSEG0 address, so jump there.  */
34	PTR_LA	t0, \@f
35	jr	t0
36\@:
37#endif
38	.endm
39
40	/*
41	 * inputs are the text nasid in t1, data nasid in t2.
42	 */
43	.macro MAPPED_KERNEL_SETUP_TLB
44#ifdef CONFIG_MAPPED_KERNEL
45	/*
46	 * This needs to read the nasid - assume 0 for now.
47	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
48	 * 0+DVG in tlblo_1.
49	 */
50	dli	t0, 0xffffffffc0000000
51	dmtc0	t0, CP0_ENTRYHI
52	li	t0, 0x1c000		# Offset of text into node memory
53	dsll	t1, NASID_SHFT		# Shift text nasid into place
54	dsll	t2, NASID_SHFT		# Same for data nasid
55	or	t1, t1, t0		# Physical load address of kernel text
56	or	t2, t2, t0		# Physical load address of kernel data
57	dsrl	t1, 12			# 4K pfn
58	dsrl	t2, 12			# 4K pfn
59	dsll	t1, 6			# Get pfn into place
60	dsll	t2, 6			# Get pfn into place
61	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
62	or	t0, t0, t1
63	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr
64	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
65	or	t0, t0, t2
66	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr
67	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M
68	mtc0	t0, CP0_PAGEMASK
69	li	t0, 0			# KMAP_INX
70	mtc0	t0, CP0_INDEX
71	li	t0, 1
72	mtc0	t0, CP0_WIRED
73	tlbwi
74#else
75	mtc0	zero, CP0_WIRED
76#endif
77	.endm
78
79	/*
80	 * For the moment disable interrupts, mark the kernel mode and
81	 * set ST0_KX so that the CPU does not spit fire when using
82	 * 64-bit addresses.  A full initialization of the CPU's status
83	 * register is done later in per_cpu_trap_init().
84	 */
85	.macro	setup_c0_status set clr
86	.set	push
87#ifdef CONFIG_MIPS_MT_SMTC
88	/*
89	 * For SMTC, we need to set privilege and disable interrupts only for
90	 * the current TC, using the TCStatus register.
91	 */
92	mfc0	t0, CP0_TCSTATUS
93	/* Fortunately CU 0 is in the same place in both registers */
94	/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
95	li	t1, ST0_CU0 | 0x08001c00
96	or	t0, t1
97	/* Clear TKSU, leave IXMT */
98	xori	t0, 0x00001800
99	mtc0	t0, CP0_TCSTATUS
100	_ehb
101	/* We need to leave the global IE bit set, but clear EXL...*/
102	mfc0	t0, CP0_STATUS
103	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
104	xor	t0, ST0_EXL | ST0_ERL | \clr
105	mtc0	t0, CP0_STATUS
106#else
107	mfc0	t0, CP0_STATUS
108	or	t0, ST0_CU0|\set|0x1f|\clr
109	xor	t0, 0x1f|\clr
110	mtc0	t0, CP0_STATUS
111	.set	noreorder
112	sll	zero,3				# ehb
113#endif
114	.set	pop
115	.endm
116
117	.macro	setup_c0_status_pri
118#ifdef CONFIG_64BIT
119	setup_c0_status ST0_KX 0
120#else
121	setup_c0_status 0 0
122#endif
123	.endm
124
125	.macro	setup_c0_status_sec
126#ifdef CONFIG_64BIT
127	setup_c0_status ST0_KX ST0_BEV
128#else
129	setup_c0_status 0 ST0_BEV
130#endif
131	.endm
132
133#ifndef CONFIG_NO_EXCEPT_FILL
134	/*
135	 * Reserved space for exception handlers.
136	 * Necessary for machines which link their kernels at KSEG0.
137	 */
138	.fill	0x400
139#endif
140
141EXPORT(_stext)
142
143#ifndef CONFIG_BOOT_RAW
144	/*
145	 * Give us a fighting chance of running if execution beings at the
146	 * kernel load address.  This is needed because this platform does
147	 * not have a ELF loader yet.
148	 */
149	__INIT
150#endif
151
152NESTED(kernel_entry, 16, sp)			# kernel entry point
153
154	kernel_entry_setup			# cpu specific setup
155
156	setup_c0_status_pri
157
158	ARC64_TWIDDLE_PC
159
160#ifdef CONFIG_MIPS_MT_SMTC
161	/*
162	 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
163	 * We still need to enable interrupts globally in Status,
164	 * and clear EXL/ERL.
165	 *
166	 * TCContext is used to track interrupt levels under
167	 * service in SMTC kernel. Clear for boot TC before
168	 * allowing any interrupts.
169	 */
170	mtc0	zero, CP0_TCCONTEXT
171
172	mfc0	t0, CP0_STATUS
173	ori	t0, t0, 0xff1f
174	xori	t0, t0, 0x001e
175	mtc0	t0, CP0_STATUS
176#endif /* CONFIG_MIPS_MT_SMTC */
177
178	PTR_LA		t0, __bss_start		# clear .bss
179	LONG_S		zero, (t0)
180	PTR_LA		t1, __bss_stop - LONGSIZE
1811:
182	PTR_ADDIU	t0, LONGSIZE
183	LONG_S		zero, (t0)
184	bne		t0, t1, 1b
185
186	LONG_S		a0, fw_arg0		# firmware arguments
187	LONG_S		a1, fw_arg1
188	LONG_S		a2, fw_arg2
189	LONG_S		a3, fw_arg3
190
191	MTC0		zero, CP0_CONTEXT	# clear context register
192	PTR_LA		$28, init_thread_union
193	PTR_LI		sp, _THREAD_SIZE - 32
194	PTR_ADDU	sp, $28
195	set_saved_sp	sp, t0, t1
196	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
197
198	j		start_kernel
199	END(kernel_entry)
200
201	__INIT
202
203#ifdef CONFIG_SMP
204/*
205 * SMP slave cpus entry point.  Board specific code for bootstrap calls this
206 * function after setting up the stack and gp registers.
207 */
208NESTED(smp_bootstrap, 16, sp)
209#ifdef CONFIG_MIPS_MT_SMTC
210	/*
211	 * Read-modify-writes of Status must be atomic, and this
212	 * is one case where CLI is invoked without EXL being
213	 * necessarily set. The CLI and setup_c0_status will
214	 * in fact be redundant for all but the first TC of
215	 * each VPE being booted.
216	 */
217	DMT	10	# dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
218	jal	mips_ihb
219#endif /* CONFIG_MIPS_MT_SMTC */
220	setup_c0_status_sec
221	smp_slave_setup
222#ifdef CONFIG_MIPS_MT_SMTC
223	andi	t2, t2, VPECONTROL_TE
224	beqz	t2, 2f
225	EMT		# emt
2262:
227#endif /* CONFIG_MIPS_MT_SMTC */
228	j	start_secondary
229	END(smp_bootstrap)
230#endif /* CONFIG_SMP */
231
232	__FINIT
233