1*384740dcSRalf Baechle /* 2*384740dcSRalf Baechle * Miscellaneous definitions used to initialise the interrupt vector table 3*384740dcSRalf Baechle * with the machine-specific interrupt routines. 4*384740dcSRalf Baechle * 5*384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 6*384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 7*384740dcSRalf Baechle * for more details. 8*384740dcSRalf Baechle * 9*384740dcSRalf Baechle * Copyright (C) 1997 by Paul M. Antoine. 10*384740dcSRalf Baechle * reworked 1998 by Harald Koerfgen. 11*384740dcSRalf Baechle * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki 12*384740dcSRalf Baechle */ 13*384740dcSRalf Baechle 14*384740dcSRalf Baechle #ifndef __ASM_DEC_INTERRUPTS_H 15*384740dcSRalf Baechle #define __ASM_DEC_INTERRUPTS_H 16*384740dcSRalf Baechle 17*384740dcSRalf Baechle #include <irq.h> 18*384740dcSRalf Baechle #include <asm/mipsregs.h> 19*384740dcSRalf Baechle 20*384740dcSRalf Baechle 21*384740dcSRalf Baechle /* 22*384740dcSRalf Baechle * The list of possible system devices which provide an 23*384740dcSRalf Baechle * interrupt. Not all devices exist on a given system. 24*384740dcSRalf Baechle */ 25*384740dcSRalf Baechle #define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ 26*384740dcSRalf Baechle 27*384740dcSRalf Baechle /* Ordinary interrupts */ 28*384740dcSRalf Baechle #define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ 29*384740dcSRalf Baechle #define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ 30*384740dcSRalf Baechle #define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ 31*384740dcSRalf Baechle #define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ 32*384740dcSRalf Baechle #define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ 33*384740dcSRalf Baechle #define DEC_IRQ_FPU 6 /* R3k FPU */ 34*384740dcSRalf Baechle #define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ 35*384740dcSRalf Baechle #define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ 36*384740dcSRalf Baechle #define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ 37*384740dcSRalf Baechle #define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ 38*384740dcSRalf Baechle #define DEC_IRQ_PSU 11 /* power supply unit warning */ 39*384740dcSRalf Baechle #define DEC_IRQ_RTC 12 /* DS1287 RTC */ 40*384740dcSRalf Baechle #define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ 41*384740dcSRalf Baechle #define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ 42*384740dcSRalf Baechle #define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ 43*384740dcSRalf Baechle #define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ 44*384740dcSRalf Baechle #define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ 45*384740dcSRalf Baechle #define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ 46*384740dcSRalf Baechle #define DEC_IRQ_TIMER 19 /* ARC periodic timer */ 47*384740dcSRalf Baechle #define DEC_IRQ_VIDEO 20 /* framebuffer */ 48*384740dcSRalf Baechle 49*384740dcSRalf Baechle /* I/O ASIC DMA interrupts */ 50*384740dcSRalf Baechle #define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ 51*384740dcSRalf Baechle #define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ 52*384740dcSRalf Baechle #define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ 53*384740dcSRalf Baechle #define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ 54*384740dcSRalf Baechle #define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ 55*384740dcSRalf Baechle #define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ 56*384740dcSRalf Baechle #define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ 57*384740dcSRalf Baechle #define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ 58*384740dcSRalf Baechle #define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ 59*384740dcSRalf Baechle #define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ 60*384740dcSRalf Baechle #define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ 61*384740dcSRalf Baechle #define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ 62*384740dcSRalf Baechle #define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ 63*384740dcSRalf Baechle #define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ 64*384740dcSRalf Baechle #define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ 65*384740dcSRalf Baechle #define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ 66*384740dcSRalf Baechle #define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ 67*384740dcSRalf Baechle #define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ 68*384740dcSRalf Baechle #define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ 69*384740dcSRalf Baechle #define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ 70*384740dcSRalf Baechle 71*384740dcSRalf Baechle /* TC5 & TC6 are virtual slots for KN02's onboard devices */ 72*384740dcSRalf Baechle #define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ 73*384740dcSRalf Baechle #define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ 74*384740dcSRalf Baechle 75*384740dcSRalf Baechle #define DEC_NR_INTS 41 76*384740dcSRalf Baechle 77*384740dcSRalf Baechle 78*384740dcSRalf Baechle /* Largest of cpu mask_nr tables. */ 79*384740dcSRalf Baechle #define DEC_MAX_CPU_INTS 6 80*384740dcSRalf Baechle /* Largest of asic mask_nr tables. */ 81*384740dcSRalf Baechle #define DEC_MAX_ASIC_INTS 9 82*384740dcSRalf Baechle 83*384740dcSRalf Baechle 84*384740dcSRalf Baechle /* 85*384740dcSRalf Baechle * CPU interrupt bits common to all systems. 86*384740dcSRalf Baechle */ 87*384740dcSRalf Baechle #define DEC_CPU_INR_FPU 7 /* R3k FPU */ 88*384740dcSRalf Baechle #define DEC_CPU_INR_SW1 1 /* software #1 */ 89*384740dcSRalf Baechle #define DEC_CPU_INR_SW0 0 /* software #0 */ 90*384740dcSRalf Baechle 91*384740dcSRalf Baechle #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ 92*384740dcSRalf Baechle 93*384740dcSRalf Baechle #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) 94*384740dcSRalf Baechle #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) 95*384740dcSRalf Baechle #define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) 96*384740dcSRalf Baechle 97*384740dcSRalf Baechle 98*384740dcSRalf Baechle #ifndef __ASSEMBLY__ 99*384740dcSRalf Baechle 100*384740dcSRalf Baechle /* 101*384740dcSRalf Baechle * Interrupt table structures to hide differences between systems. 102*384740dcSRalf Baechle */ 103*384740dcSRalf Baechle typedef union { int i; void *p; } int_ptr; 104*384740dcSRalf Baechle extern int dec_interrupt[DEC_NR_INTS]; 105*384740dcSRalf Baechle extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; 106*384740dcSRalf Baechle extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; 107*384740dcSRalf Baechle extern int cpu_fpu_mask; 108*384740dcSRalf Baechle 109*384740dcSRalf Baechle 110*384740dcSRalf Baechle /* 111*384740dcSRalf Baechle * Common interrupt routine prototypes for all DECStations 112*384740dcSRalf Baechle */ 113*384740dcSRalf Baechle extern void kn02_io_int(void); 114*384740dcSRalf Baechle extern void kn02xa_io_int(void); 115*384740dcSRalf Baechle extern void kn03_io_int(void); 116*384740dcSRalf Baechle extern void asic_dma_int(void); 117*384740dcSRalf Baechle extern void asic_all_int(void); 118*384740dcSRalf Baechle extern void kn02_all_int(void); 119*384740dcSRalf Baechle extern void cpu_all_int(void); 120*384740dcSRalf Baechle 121*384740dcSRalf Baechle extern void dec_intr_unimplemented(void); 122*384740dcSRalf Baechle extern void asic_intr_unimplemented(void); 123*384740dcSRalf Baechle 124*384740dcSRalf Baechle #endif /* __ASSEMBLY__ */ 125*384740dcSRalf Baechle 126*384740dcSRalf Baechle #endif 127