1 /* 2 * Setup pointers to hardware dependent routines. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 10 * 11 */ 12 #include <linux/config.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/init.h> 16 #include <linux/pm.h> 17 #include <linux/serial.h> 18 #include <linux/serial_core.h> 19 20 #include <asm/bootinfo.h> 21 #include <asm/time.h> 22 #include <asm/io.h> 23 #include <asm/irq.h> 24 #include <asm/processor.h> 25 #include <asm/reboot.h> 26 #include <asm/gt64120.h> 27 #include <asm/serial.h> 28 29 #include <asm/mach-cobalt/cobalt.h> 30 31 extern void cobalt_machine_restart(char *command); 32 extern void cobalt_machine_halt(void); 33 extern void cobalt_machine_power_off(void); 34 extern void cobalt_early_console(void); 35 36 int cobalt_board_id; 37 38 const char *get_system_type(void) 39 { 40 switch (cobalt_board_id) { 41 case COBALT_BRD_ID_QUBE1: 42 return "Cobalt Qube"; 43 case COBALT_BRD_ID_RAQ1: 44 return "Cobalt RaQ"; 45 case COBALT_BRD_ID_QUBE2: 46 return "Cobalt Qube2"; 47 case COBALT_BRD_ID_RAQ2: 48 return "Cobalt RaQ2"; 49 } 50 return "MIPS Cobalt"; 51 } 52 53 static void __init cobalt_timer_setup(struct irqaction *irq) 54 { 55 /* Load timer value for 1KHz (TCLK is 50MHz) */ 56 GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS); 57 58 /* Enable timer */ 59 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 60 61 /* Register interrupt */ 62 setup_irq(COBALT_GALILEO_IRQ, irq); 63 64 /* Enable interrupt */ 65 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 66 } 67 68 extern struct pci_ops gt64111_pci_ops; 69 70 static struct resource cobalt_mem_resource = { 71 .start = GT64111_MEM_BASE, 72 .end = GT64111_MEM_END, 73 .name = "PCI memory", 74 .flags = IORESOURCE_MEM 75 }; 76 77 static struct resource cobalt_io_resource = { 78 .start = 0x1000, 79 .end = 0xffff, 80 .name = "PCI I/O", 81 .flags = IORESOURCE_IO 82 }; 83 84 static struct resource cobalt_io_resources[] = { 85 { 86 .start = 0x00, 87 .end = 0x1f, 88 .name = "dma1", 89 .flags = IORESOURCE_BUSY 90 }, { 91 .start = 0x40, 92 .end = 0x5f, 93 .name = "timer", 94 .flags = IORESOURCE_BUSY 95 }, { 96 .start = 0x60, 97 .end = 0x6f, 98 .name = "keyboard", 99 .flags = IORESOURCE_BUSY 100 }, { 101 .start = 0x80, 102 .end = 0x8f, 103 .name = "dma page reg", 104 .flags = IORESOURCE_BUSY 105 }, { 106 .start = 0xc0, 107 .end = 0xdf, 108 .name = "dma2", 109 .flags = IORESOURCE_BUSY 110 }, 111 }; 112 113 #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource)) 114 115 static struct pci_controller cobalt_pci_controller = { 116 .pci_ops = >64111_pci_ops, 117 .mem_resource = &cobalt_mem_resource, 118 .mem_offset = 0, 119 .io_resource = &cobalt_io_resource, 120 .io_offset = 0 - GT64111_IO_BASE 121 }; 122 123 void __init plat_mem_setup(void) 124 { 125 static struct uart_port uart; 126 unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); 127 int i; 128 129 _machine_restart = cobalt_machine_restart; 130 _machine_halt = cobalt_machine_halt; 131 pm_power_off = cobalt_machine_power_off; 132 133 board_timer_setup = cobalt_timer_setup; 134 135 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 136 137 /* I/O port resource must include UART and LCD/buttons */ 138 ioport_resource.end = 0x0fffffff; 139 140 /* request I/O space for devices used on all i[345]86 PCs */ 141 for (i = 0; i < COBALT_IO_RESOURCES; i++) 142 request_resource(&ioport_resource, cobalt_io_resources + i); 143 144 /* Read the cobalt id register out of the PCI config space */ 145 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 146 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 147 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 148 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 149 150 printk("Cobalt board ID: %d\n", cobalt_board_id); 151 152 #ifdef CONFIG_PCI 153 register_pci_controller(&cobalt_pci_controller); 154 #endif 155 156 #ifdef CONFIG_SERIAL_8250 157 if (cobalt_board_id > COBALT_BRD_ID_RAQ1) { 158 159 #ifdef CONFIG_EARLY_PRINTK 160 cobalt_early_console(); 161 #endif 162 163 uart.line = 0; 164 uart.type = PORT_UNKNOWN; 165 uart.uartclk = 18432000; 166 uart.irq = COBALT_SERIAL_IRQ; 167 uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; 168 uart.iobase = 0xc800000; 169 uart.iotype = UPIO_PORT; 170 171 early_serial_setup(&uart); 172 } 173 #endif 174 } 175 176 /* 177 * Prom init. We read our one and only communication with the firmware. 178 * Grab the amount of installed memory. 179 * Better boot loaders (CoLo) pass a command line too :-) 180 */ 181 182 void __init prom_init(void) 183 { 184 int narg, indx, posn, nchr; 185 unsigned long memsz; 186 char **argv; 187 188 mips_machgroup = MACH_GROUP_COBALT; 189 190 memsz = fw_arg0 & 0x7fff0000; 191 narg = fw_arg0 & 0x0000ffff; 192 193 if (narg) { 194 arcs_cmdline[0] = '\0'; 195 argv = (char **) fw_arg1; 196 posn = 0; 197 for (indx = 1; indx < narg; ++indx) { 198 nchr = strlen(argv[indx]); 199 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline)) 200 break; 201 if (posn) 202 arcs_cmdline[posn++] = ' '; 203 strcpy(arcs_cmdline + posn, argv[indx]); 204 posn += nchr; 205 } 206 } 207 208 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 209 } 210 211 unsigned long __init prom_free_prom_memory(void) 212 { 213 /* Nothing to do! */ 214 return 0; 215 } 216