1*f86b9e03SGreg Ungerer /***************************************************************************/ 2*f86b9e03SGreg Ungerer 3*f86b9e03SGreg Ungerer /* 4*f86b9e03SGreg Ungerer * linux/arch/m68knommu/platform/520x/config.c 5*f86b9e03SGreg Ungerer * 6*f86b9e03SGreg Ungerer * Copyright (C) 2005, Freescale (www.freescale.com) 7*f86b9e03SGreg Ungerer * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com) 8*f86b9e03SGreg Ungerer * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com) 9*f86b9e03SGreg Ungerer * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) 10*f86b9e03SGreg Ungerer */ 11*f86b9e03SGreg Ungerer 12*f86b9e03SGreg Ungerer /***************************************************************************/ 13*f86b9e03SGreg Ungerer 14*f86b9e03SGreg Ungerer #include <linux/kernel.h> 15*f86b9e03SGreg Ungerer #include <linux/param.h> 16*f86b9e03SGreg Ungerer #include <linux/init.h> 17*f86b9e03SGreg Ungerer #include <linux/io.h> 18*f86b9e03SGreg Ungerer #include <asm/machdep.h> 19*f86b9e03SGreg Ungerer #include <asm/coldfire.h> 20*f86b9e03SGreg Ungerer #include <asm/mcfsim.h> 21*f86b9e03SGreg Ungerer #include <asm/mcfuart.h> 22*f86b9e03SGreg Ungerer #include <asm/mcfclk.h> 23*f86b9e03SGreg Ungerer 24*f86b9e03SGreg Ungerer /***************************************************************************/ 25*f86b9e03SGreg Ungerer 26*f86b9e03SGreg Ungerer DEFINE_CLK(0, "flexbus", 2, MCF_CLK); 27*f86b9e03SGreg Ungerer DEFINE_CLK(0, "fec.0", 12, MCF_CLK); 28*f86b9e03SGreg Ungerer DEFINE_CLK(0, "edma", 17, MCF_CLK); 29*f86b9e03SGreg Ungerer DEFINE_CLK(0, "intc.0", 18, MCF_CLK); 30*f86b9e03SGreg Ungerer DEFINE_CLK(0, "iack.0", 21, MCF_CLK); 31*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK); 32*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK); 33*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); 34*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 35*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); 36*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); 37*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); 38*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); 39*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); 40*f86b9e03SGreg Ungerer 41*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); 42*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); 43*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK); 44*f86b9e03SGreg Ungerer DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK); 45*f86b9e03SGreg Ungerer DEFINE_CLK(0, "pll.0", 36, MCF_CLK); 46*f86b9e03SGreg Ungerer DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK); 47*f86b9e03SGreg Ungerer DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK); 48*f86b9e03SGreg Ungerer DEFINE_CLK(0, "sdram.0", 42, MCF_CLK); 49*f86b9e03SGreg Ungerer 50*f86b9e03SGreg Ungerer struct clk *mcf_clks[] = { 51*f86b9e03SGreg Ungerer &__clk_0_2, /* flexbus */ 52*f86b9e03SGreg Ungerer &__clk_0_12, /* fec.0 */ 53*f86b9e03SGreg Ungerer &__clk_0_17, /* edma */ 54*f86b9e03SGreg Ungerer &__clk_0_18, /* intc.0 */ 55*f86b9e03SGreg Ungerer &__clk_0_21, /* iack.0 */ 56*f86b9e03SGreg Ungerer &__clk_0_22, /* mcfi2c.0 */ 57*f86b9e03SGreg Ungerer &__clk_0_23, /* mcfqspi.0 */ 58*f86b9e03SGreg Ungerer &__clk_0_24, /* mcfuart.0 */ 59*f86b9e03SGreg Ungerer &__clk_0_25, /* mcfuart.1 */ 60*f86b9e03SGreg Ungerer &__clk_0_26, /* mcfuart.2 */ 61*f86b9e03SGreg Ungerer &__clk_0_28, /* mcftmr.0 */ 62*f86b9e03SGreg Ungerer &__clk_0_29, /* mcftmr.1 */ 63*f86b9e03SGreg Ungerer &__clk_0_30, /* mcftmr.2 */ 64*f86b9e03SGreg Ungerer &__clk_0_31, /* mcftmr.3 */ 65*f86b9e03SGreg Ungerer 66*f86b9e03SGreg Ungerer &__clk_0_32, /* mcfpit.0 */ 67*f86b9e03SGreg Ungerer &__clk_0_33, /* mcfpit.1 */ 68*f86b9e03SGreg Ungerer &__clk_0_34, /* mcfeport.0 */ 69*f86b9e03SGreg Ungerer &__clk_0_35, /* mcfwdt.0 */ 70*f86b9e03SGreg Ungerer &__clk_0_36, /* pll.0 */ 71*f86b9e03SGreg Ungerer &__clk_0_40, /* sys.0 */ 72*f86b9e03SGreg Ungerer &__clk_0_41, /* gpio.0 */ 73*f86b9e03SGreg Ungerer &__clk_0_42, /* sdram.0 */ 74*f86b9e03SGreg Ungerer NULL, 75*f86b9e03SGreg Ungerer }; 76*f86b9e03SGreg Ungerer 77*f86b9e03SGreg Ungerer static struct clk * const enable_clks[] __initconst = { 78*f86b9e03SGreg Ungerer &__clk_0_2, /* flexbus */ 79*f86b9e03SGreg Ungerer &__clk_0_18, /* intc.0 */ 80*f86b9e03SGreg Ungerer &__clk_0_21, /* iack.0 */ 81*f86b9e03SGreg Ungerer &__clk_0_24, /* mcfuart.0 */ 82*f86b9e03SGreg Ungerer &__clk_0_25, /* mcfuart.1 */ 83*f86b9e03SGreg Ungerer &__clk_0_26, /* mcfuart.2 */ 84*f86b9e03SGreg Ungerer 85*f86b9e03SGreg Ungerer &__clk_0_32, /* mcfpit.0 */ 86*f86b9e03SGreg Ungerer &__clk_0_33, /* mcfpit.1 */ 87*f86b9e03SGreg Ungerer &__clk_0_34, /* mcfeport.0 */ 88*f86b9e03SGreg Ungerer &__clk_0_36, /* pll.0 */ 89*f86b9e03SGreg Ungerer &__clk_0_40, /* sys.0 */ 90*f86b9e03SGreg Ungerer &__clk_0_41, /* gpio.0 */ 91*f86b9e03SGreg Ungerer &__clk_0_42, /* sdram.0 */ 92*f86b9e03SGreg Ungerer }; 93*f86b9e03SGreg Ungerer 94*f86b9e03SGreg Ungerer static struct clk * const disable_clks[] __initconst = { 95*f86b9e03SGreg Ungerer &__clk_0_12, /* fec.0 */ 96*f86b9e03SGreg Ungerer &__clk_0_17, /* edma */ 97*f86b9e03SGreg Ungerer &__clk_0_22, /* mcfi2c.0 */ 98*f86b9e03SGreg Ungerer &__clk_0_23, /* mcfqspi.0 */ 99*f86b9e03SGreg Ungerer &__clk_0_28, /* mcftmr.0 */ 100*f86b9e03SGreg Ungerer &__clk_0_29, /* mcftmr.1 */ 101*f86b9e03SGreg Ungerer &__clk_0_30, /* mcftmr.2 */ 102*f86b9e03SGreg Ungerer &__clk_0_31, /* mcftmr.3 */ 103*f86b9e03SGreg Ungerer &__clk_0_35, /* mcfwdt.0 */ 104*f86b9e03SGreg Ungerer }; 105*f86b9e03SGreg Ungerer 106*f86b9e03SGreg Ungerer 107*f86b9e03SGreg Ungerer static void __init m520x_clk_init(void) 108*f86b9e03SGreg Ungerer { 109*f86b9e03SGreg Ungerer unsigned i; 110*f86b9e03SGreg Ungerer 111*f86b9e03SGreg Ungerer /* make sure these clocks are enabled */ 112*f86b9e03SGreg Ungerer for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) 113*f86b9e03SGreg Ungerer __clk_init_enabled(enable_clks[i]); 114*f86b9e03SGreg Ungerer /* make sure these clocks are disabled */ 115*f86b9e03SGreg Ungerer for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) 116*f86b9e03SGreg Ungerer __clk_init_disabled(disable_clks[i]); 117*f86b9e03SGreg Ungerer } 118*f86b9e03SGreg Ungerer 119*f86b9e03SGreg Ungerer /***************************************************************************/ 120*f86b9e03SGreg Ungerer 121*f86b9e03SGreg Ungerer static void __init m520x_qspi_init(void) 122*f86b9e03SGreg Ungerer { 123*f86b9e03SGreg Ungerer #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 124*f86b9e03SGreg Ungerer u16 par; 125*f86b9e03SGreg Ungerer /* setup Port QS for QSPI with gpio CS control */ 126*f86b9e03SGreg Ungerer writeb(0x3f, MCF_GPIO_PAR_QSPI); 127*f86b9e03SGreg Ungerer /* make U1CTS and U2RTS gpio for cs_control */ 128*f86b9e03SGreg Ungerer par = readw(MCF_GPIO_PAR_UART); 129*f86b9e03SGreg Ungerer par &= 0x00ff; 130*f86b9e03SGreg Ungerer writew(par, MCF_GPIO_PAR_UART); 131*f86b9e03SGreg Ungerer #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 132*f86b9e03SGreg Ungerer } 133*f86b9e03SGreg Ungerer 134*f86b9e03SGreg Ungerer /***************************************************************************/ 135*f86b9e03SGreg Ungerer 136*f86b9e03SGreg Ungerer static void __init m520x_uarts_init(void) 137*f86b9e03SGreg Ungerer { 138*f86b9e03SGreg Ungerer u16 par; 139*f86b9e03SGreg Ungerer u8 par2; 140*f86b9e03SGreg Ungerer 141*f86b9e03SGreg Ungerer /* UART0 and UART1 GPIO pin setup */ 142*f86b9e03SGreg Ungerer par = readw(MCF_GPIO_PAR_UART); 143*f86b9e03SGreg Ungerer par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0; 144*f86b9e03SGreg Ungerer par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1; 145*f86b9e03SGreg Ungerer writew(par, MCF_GPIO_PAR_UART); 146*f86b9e03SGreg Ungerer 147*f86b9e03SGreg Ungerer /* UART1 GPIO pin setup */ 148*f86b9e03SGreg Ungerer par2 = readb(MCF_GPIO_PAR_FECI2C); 149*f86b9e03SGreg Ungerer par2 &= ~0x0F; 150*f86b9e03SGreg Ungerer par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 | 151*f86b9e03SGreg Ungerer MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2; 152*f86b9e03SGreg Ungerer writeb(par2, MCF_GPIO_PAR_FECI2C); 153*f86b9e03SGreg Ungerer } 154*f86b9e03SGreg Ungerer 155*f86b9e03SGreg Ungerer /***************************************************************************/ 156*f86b9e03SGreg Ungerer 157*f86b9e03SGreg Ungerer static void __init m520x_fec_init(void) 158*f86b9e03SGreg Ungerer { 159*f86b9e03SGreg Ungerer u8 v; 160*f86b9e03SGreg Ungerer 161*f86b9e03SGreg Ungerer /* Set multi-function pins to ethernet mode */ 162*f86b9e03SGreg Ungerer v = readb(MCF_GPIO_PAR_FEC); 163*f86b9e03SGreg Ungerer writeb(v | 0xf0, MCF_GPIO_PAR_FEC); 164*f86b9e03SGreg Ungerer 165*f86b9e03SGreg Ungerer v = readb(MCF_GPIO_PAR_FECI2C); 166*f86b9e03SGreg Ungerer writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); 167*f86b9e03SGreg Ungerer } 168*f86b9e03SGreg Ungerer 169*f86b9e03SGreg Ungerer /***************************************************************************/ 170*f86b9e03SGreg Ungerer 171*f86b9e03SGreg Ungerer void __init config_BSP(char *commandp, int size) 172*f86b9e03SGreg Ungerer { 173*f86b9e03SGreg Ungerer mach_sched_init = hw_timer_init; 174*f86b9e03SGreg Ungerer m520x_clk_init(); 175*f86b9e03SGreg Ungerer m520x_uarts_init(); 176*f86b9e03SGreg Ungerer m520x_fec_init(); 177*f86b9e03SGreg Ungerer m520x_qspi_init(); 178*f86b9e03SGreg Ungerer } 179*f86b9e03SGreg Ungerer 180*f86b9e03SGreg Ungerer /***************************************************************************/ 181