1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 231 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 248 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 249 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 254 ARM64_FTR_END, 255 }; 256 257 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 259 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 291 ARM64_FTR_END, 292 }; 293 294 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 296 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 297 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 298 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 316 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 318 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 319 ARM64_FTR_END, 320 }; 321 322 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 326 /* 327 * Page size not being supported at Stage-2 is not fatal. You 328 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 329 * your favourite nesting hypervisor. 330 * 331 * There is a small corner case where the hypervisor explicitly 332 * advertises a given granule size at Stage-2 (value 2) on some 333 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 334 * vCPUs. Although this is not forbidden by the architecture, it 335 * indicates that the hypervisor is being silly (or buggy). 336 * 337 * We make no effort to cope with this and pretend that if these 338 * fields are inconsistent across vCPUs, then it isn't worth 339 * trying to bring KVM up. 340 */ 341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 344 /* 345 * We already refuse to boot CPUs that don't support our configured 346 * page size, so we can only detect mismatches for a page size other 347 * than the one we're currently using. Unfortunately, SoCs like this 348 * exist in the wild so, even though we don't like it, we'll have to go 349 * along with it and treat them as non-strict. 350 */ 351 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 352 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 354 355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 356 /* Linux shouldn't care about secure memory */ 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 360 /* 361 * Differing PARange is fine as long as all peripherals and memory are mapped 362 * within the minimum PARange of all CPUs 363 */ 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 365 ARM64_FTR_END, 366 }; 367 368 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 382 ARM64_FTR_END, 383 }; 384 385 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 396 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 401 ARM64_FTR_END, 402 }; 403 404 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 407 ARM64_FTR_END, 408 }; 409 410 static const struct arm64_ftr_bits ftr_ctr[] = { 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 417 /* 418 * Linux can handle differing I-cache policies. Userspace JITs will 419 * make use of *minLine. 420 * If we have differing I-cache policies, report it as the weakest - VIPT. 421 */ 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 424 ARM64_FTR_END, 425 }; 426 427 static struct arm64_ftr_override __ro_after_init no_override = { }; 428 429 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 430 .name = "SYS_CTR_EL0", 431 .ftr_bits = ftr_ctr, 432 .override = &no_override, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 441 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 444 ARM64_FTR_END, 445 }; 446 447 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 448 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 453 /* 454 * We can instantiate multiple PMU instances with different levels 455 * of support. 456 */ 457 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_mvfr0[] = { 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 471 ARM64_FTR_END, 472 }; 473 474 static const struct arm64_ftr_bits ftr_mvfr1[] = { 475 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 483 ARM64_FTR_END, 484 }; 485 486 static const struct arm64_ftr_bits ftr_mvfr2[] = { 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 489 ARM64_FTR_END, 490 }; 491 492 static const struct arm64_ftr_bits ftr_dczid[] = { 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 494 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_gmid[] = { 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_id_isar0[] = { 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_isar5[] = { 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 521 ARM64_FTR_END, 522 }; 523 524 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 532 533 /* 534 * SpecSEI = 1 indicates that the PE might generate an SError on an 535 * external abort on speculative read. It is safe to assume that an 536 * SError might be generated than it will not be. Hence it has been 537 * classified as FTR_HIGHER_SAFE. 538 */ 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_id_isar4[] = { 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 552 ARM64_FTR_END, 553 }; 554 555 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 557 ARM64_FTR_END, 558 }; 559 560 static const struct arm64_ftr_bits ftr_id_isar6[] = { 561 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 566 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 568 ARM64_FTR_END, 569 }; 570 571 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 600 /* [31:28] TraceFilt */ 601 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 612 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 /* 617 * Common ftr bits for a 32bit register with all hidden, strict 618 * attributes, with 4bit feature fields and a default safe value of 619 * 0. Covers the following 32bit registers: 620 * id_isar[1-3], id_mmfr[1-3] 621 */ 622 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 631 ARM64_FTR_END, 632 }; 633 634 /* Table for a single 32bit feature value */ 635 static const struct arm64_ftr_bits ftr_single32[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 637 ARM64_FTR_END, 638 }; 639 640 static const struct arm64_ftr_bits ftr_raz[] = { 641 ARM64_FTR_END, 642 }; 643 644 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 645 .sys_id = id, \ 646 .reg = &(struct arm64_ftr_reg){ \ 647 .name = id_str, \ 648 .override = (ovr), \ 649 .ftr_bits = &((table)[0]), \ 650 }} 651 652 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 653 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 654 655 #define ARM64_FTR_REG(id, table) \ 656 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 657 658 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; 659 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override; 660 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; 661 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override; 662 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override; 663 struct arm64_ftr_override __ro_after_init id_aa64isar1_override; 664 struct arm64_ftr_override __ro_after_init id_aa64isar2_override; 665 666 struct arm64_ftr_override arm64_sw_feature_override; 667 668 static const struct __ftr_reg_entry { 669 u32 sys_id; 670 struct arm64_ftr_reg *reg; 671 } arm64_ftr_regs[] = { 672 673 /* Op1 = 0, CRn = 0, CRm = 1 */ 674 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 675 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 676 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 677 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 678 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 679 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 680 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 681 682 /* Op1 = 0, CRn = 0, CRm = 2 */ 683 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 684 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 685 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 686 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 687 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 688 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 689 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 690 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 691 692 /* Op1 = 0, CRn = 0, CRm = 3 */ 693 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 694 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 695 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 696 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 697 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 698 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 699 700 /* Op1 = 0, CRn = 0, CRm = 4 */ 701 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 702 &id_aa64pfr0_override), 703 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 704 &id_aa64pfr1_override), 705 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 706 &id_aa64zfr0_override), 707 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 708 &id_aa64smfr0_override), 709 710 /* Op1 = 0, CRn = 0, CRm = 5 */ 711 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 712 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 713 714 /* Op1 = 0, CRn = 0, CRm = 6 */ 715 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 716 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 717 &id_aa64isar1_override), 718 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 719 &id_aa64isar2_override), 720 721 /* Op1 = 0, CRn = 0, CRm = 7 */ 722 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 723 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 724 &id_aa64mmfr1_override), 725 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 726 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 727 728 /* Op1 = 1, CRn = 0, CRm = 0 */ 729 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 730 731 /* Op1 = 3, CRn = 0, CRm = 0 */ 732 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 733 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 734 735 /* Op1 = 3, CRn = 14, CRm = 0 */ 736 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 737 }; 738 739 static int search_cmp_ftr_reg(const void *id, const void *regp) 740 { 741 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 742 } 743 744 /* 745 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 746 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 747 * ascending order of sys_id, we use binary search to find a matching 748 * entry. 749 * 750 * returns - Upon success, matching ftr_reg entry for id. 751 * - NULL on failure. It is upto the caller to decide 752 * the impact of a failure. 753 */ 754 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 755 { 756 const struct __ftr_reg_entry *ret; 757 758 ret = bsearch((const void *)(unsigned long)sys_id, 759 arm64_ftr_regs, 760 ARRAY_SIZE(arm64_ftr_regs), 761 sizeof(arm64_ftr_regs[0]), 762 search_cmp_ftr_reg); 763 if (ret) 764 return ret->reg; 765 return NULL; 766 } 767 768 /* 769 * get_arm64_ftr_reg - Looks up a feature register entry using 770 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 771 * 772 * returns - Upon success, matching ftr_reg entry for id. 773 * - NULL on failure but with an WARN_ON(). 774 */ 775 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 776 { 777 struct arm64_ftr_reg *reg; 778 779 reg = get_arm64_ftr_reg_nowarn(sys_id); 780 781 /* 782 * Requesting a non-existent register search is an error. Warn 783 * and let the caller handle it. 784 */ 785 WARN_ON(!reg); 786 return reg; 787 } 788 789 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 790 s64 ftr_val) 791 { 792 u64 mask = arm64_ftr_mask(ftrp); 793 794 reg &= ~mask; 795 reg |= (ftr_val << ftrp->shift) & mask; 796 return reg; 797 } 798 799 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 800 s64 cur) 801 { 802 s64 ret = 0; 803 804 switch (ftrp->type) { 805 case FTR_EXACT: 806 ret = ftrp->safe_val; 807 break; 808 case FTR_LOWER_SAFE: 809 ret = min(new, cur); 810 break; 811 case FTR_HIGHER_OR_ZERO_SAFE: 812 if (!cur || !new) 813 break; 814 fallthrough; 815 case FTR_HIGHER_SAFE: 816 ret = max(new, cur); 817 break; 818 default: 819 BUG(); 820 } 821 822 return ret; 823 } 824 825 static void __init sort_ftr_regs(void) 826 { 827 unsigned int i; 828 829 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 830 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 831 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 832 unsigned int j = 0; 833 834 /* 835 * Features here must be sorted in descending order with respect 836 * to their shift values and should not overlap with each other. 837 */ 838 for (; ftr_bits->width != 0; ftr_bits++, j++) { 839 unsigned int width = ftr_reg->ftr_bits[j].width; 840 unsigned int shift = ftr_reg->ftr_bits[j].shift; 841 unsigned int prev_shift; 842 843 WARN((shift + width) > 64, 844 "%s has invalid feature at shift %d\n", 845 ftr_reg->name, shift); 846 847 /* 848 * Skip the first feature. There is nothing to 849 * compare against for now. 850 */ 851 if (j == 0) 852 continue; 853 854 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 855 WARN((shift + width) > prev_shift, 856 "%s has feature overlap at shift %d\n", 857 ftr_reg->name, shift); 858 } 859 860 /* 861 * Skip the first register. There is nothing to 862 * compare against for now. 863 */ 864 if (i == 0) 865 continue; 866 /* 867 * Registers here must be sorted in ascending order with respect 868 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 869 * to work correctly. 870 */ 871 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 872 } 873 } 874 875 /* 876 * Initialise the CPU feature register from Boot CPU values. 877 * Also initiliases the strict_mask for the register. 878 * Any bits that are not covered by an arm64_ftr_bits entry are considered 879 * RES0 for the system-wide value, and must strictly match. 880 */ 881 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 882 { 883 u64 val = 0; 884 u64 strict_mask = ~0x0ULL; 885 u64 user_mask = 0; 886 u64 valid_mask = 0; 887 888 const struct arm64_ftr_bits *ftrp; 889 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 890 891 if (!reg) 892 return; 893 894 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 895 u64 ftr_mask = arm64_ftr_mask(ftrp); 896 s64 ftr_new = arm64_ftr_value(ftrp, new); 897 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 898 899 if ((ftr_mask & reg->override->mask) == ftr_mask) { 900 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 901 char *str = NULL; 902 903 if (ftr_ovr != tmp) { 904 /* Unsafe, remove the override */ 905 reg->override->mask &= ~ftr_mask; 906 reg->override->val &= ~ftr_mask; 907 tmp = ftr_ovr; 908 str = "ignoring override"; 909 } else if (ftr_new != tmp) { 910 /* Override was valid */ 911 ftr_new = tmp; 912 str = "forced"; 913 } else if (ftr_ovr == tmp) { 914 /* Override was the safe value */ 915 str = "already set"; 916 } 917 918 if (str) 919 pr_warn("%s[%d:%d]: %s to %llx\n", 920 reg->name, 921 ftrp->shift + ftrp->width - 1, 922 ftrp->shift, str, tmp); 923 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 924 reg->override->val &= ~ftr_mask; 925 pr_warn("%s[%d:%d]: impossible override, ignored\n", 926 reg->name, 927 ftrp->shift + ftrp->width - 1, 928 ftrp->shift); 929 } 930 931 val = arm64_ftr_set_value(ftrp, val, ftr_new); 932 933 valid_mask |= ftr_mask; 934 if (!ftrp->strict) 935 strict_mask &= ~ftr_mask; 936 if (ftrp->visible) 937 user_mask |= ftr_mask; 938 else 939 reg->user_val = arm64_ftr_set_value(ftrp, 940 reg->user_val, 941 ftrp->safe_val); 942 } 943 944 val &= valid_mask; 945 946 reg->sys_val = val; 947 reg->strict_mask = strict_mask; 948 reg->user_mask = user_mask; 949 } 950 951 extern const struct arm64_cpu_capabilities arm64_errata[]; 952 static const struct arm64_cpu_capabilities arm64_features[]; 953 954 static void __init 955 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 956 { 957 for (; caps->matches; caps++) { 958 if (WARN(caps->capability >= ARM64_NCAPS, 959 "Invalid capability %d\n", caps->capability)) 960 continue; 961 if (WARN(cpucap_ptrs[caps->capability], 962 "Duplicate entry for capability %d\n", 963 caps->capability)) 964 continue; 965 cpucap_ptrs[caps->capability] = caps; 966 } 967 } 968 969 static void __init init_cpucap_indirect_list(void) 970 { 971 init_cpucap_indirect_list_from_array(arm64_features); 972 init_cpucap_indirect_list_from_array(arm64_errata); 973 } 974 975 static void __init setup_boot_cpu_capabilities(void); 976 977 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 978 { 979 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 980 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 981 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 982 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 983 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 984 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 985 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 986 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 987 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 988 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 989 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 990 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 991 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 992 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 993 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 994 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 995 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 996 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 997 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 998 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 999 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1000 } 1001 1002 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1003 { 1004 /* Before we start using the tables, make sure it is sorted */ 1005 sort_ftr_regs(); 1006 1007 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1008 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1009 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1010 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1011 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1012 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1013 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1014 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1015 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1016 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1017 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1018 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1019 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1020 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1021 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1022 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1023 1024 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1025 init_32bit_cpu_features(&info->aarch32); 1026 1027 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1028 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1029 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1030 1031 vec_init_vq_map(ARM64_VEC_SVE); 1032 1033 cpacr_restore(cpacr); 1034 } 1035 1036 if (IS_ENABLED(CONFIG_ARM64_SME) && 1037 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1038 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1039 1040 /* 1041 * We mask out SMPS since even if the hardware 1042 * supports priorities the kernel does not at present 1043 * and we block access to them. 1044 */ 1045 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1046 vec_init_vq_map(ARM64_VEC_SME); 1047 1048 cpacr_restore(cpacr); 1049 } 1050 1051 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1052 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1053 1054 /* 1055 * Initialize the indirect array of CPU capabilities pointers before we 1056 * handle the boot CPU below. 1057 */ 1058 init_cpucap_indirect_list(); 1059 1060 /* 1061 * Detect and enable early CPU capabilities based on the boot CPU, 1062 * after we have initialised the CPU feature infrastructure. 1063 */ 1064 setup_boot_cpu_capabilities(); 1065 } 1066 1067 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1068 { 1069 const struct arm64_ftr_bits *ftrp; 1070 1071 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1072 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1073 s64 ftr_new = arm64_ftr_value(ftrp, new); 1074 1075 if (ftr_cur == ftr_new) 1076 continue; 1077 /* Find a safe value */ 1078 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1079 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1080 } 1081 1082 } 1083 1084 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1085 { 1086 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1087 1088 if (!regp) 1089 return 0; 1090 1091 update_cpu_ftr_reg(regp, val); 1092 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1093 return 0; 1094 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1095 regp->name, boot, cpu, val); 1096 return 1; 1097 } 1098 1099 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1100 { 1101 const struct arm64_ftr_bits *ftrp; 1102 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1103 1104 if (!regp) 1105 return; 1106 1107 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1108 if (ftrp->shift == field) { 1109 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1110 break; 1111 } 1112 } 1113 1114 /* Bogus field? */ 1115 WARN_ON(!ftrp->width); 1116 } 1117 1118 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1119 struct cpuinfo_arm64 *boot) 1120 { 1121 static bool boot_cpu_32bit_regs_overridden = false; 1122 1123 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1124 return; 1125 1126 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1127 return; 1128 1129 boot->aarch32 = info->aarch32; 1130 init_32bit_cpu_features(&boot->aarch32); 1131 boot_cpu_32bit_regs_overridden = true; 1132 } 1133 1134 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1135 struct cpuinfo_32bit *boot) 1136 { 1137 int taint = 0; 1138 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1139 1140 /* 1141 * If we don't have AArch32 at EL1, then relax the strictness of 1142 * EL1-dependent register fields to avoid spurious sanity check fails. 1143 */ 1144 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1145 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1146 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1147 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1148 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1149 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1150 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1151 } 1152 1153 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1154 info->reg_id_dfr0, boot->reg_id_dfr0); 1155 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1156 info->reg_id_dfr1, boot->reg_id_dfr1); 1157 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1158 info->reg_id_isar0, boot->reg_id_isar0); 1159 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1160 info->reg_id_isar1, boot->reg_id_isar1); 1161 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1162 info->reg_id_isar2, boot->reg_id_isar2); 1163 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1164 info->reg_id_isar3, boot->reg_id_isar3); 1165 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1166 info->reg_id_isar4, boot->reg_id_isar4); 1167 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1168 info->reg_id_isar5, boot->reg_id_isar5); 1169 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1170 info->reg_id_isar6, boot->reg_id_isar6); 1171 1172 /* 1173 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1174 * ACTLR formats could differ across CPUs and therefore would have to 1175 * be trapped for virtualization anyway. 1176 */ 1177 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1178 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1179 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1180 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1181 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1182 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1183 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1184 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1185 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1186 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1187 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1188 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1189 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1190 info->reg_id_pfr0, boot->reg_id_pfr0); 1191 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1192 info->reg_id_pfr1, boot->reg_id_pfr1); 1193 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1194 info->reg_id_pfr2, boot->reg_id_pfr2); 1195 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1196 info->reg_mvfr0, boot->reg_mvfr0); 1197 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1198 info->reg_mvfr1, boot->reg_mvfr1); 1199 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1200 info->reg_mvfr2, boot->reg_mvfr2); 1201 1202 return taint; 1203 } 1204 1205 /* 1206 * Update system wide CPU feature registers with the values from a 1207 * non-boot CPU. Also performs SANITY checks to make sure that there 1208 * aren't any insane variations from that of the boot CPU. 1209 */ 1210 void update_cpu_features(int cpu, 1211 struct cpuinfo_arm64 *info, 1212 struct cpuinfo_arm64 *boot) 1213 { 1214 int taint = 0; 1215 1216 /* 1217 * The kernel can handle differing I-cache policies, but otherwise 1218 * caches should look identical. Userspace JITs will make use of 1219 * *minLine. 1220 */ 1221 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1222 info->reg_ctr, boot->reg_ctr); 1223 1224 /* 1225 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1226 * could result in too much or too little memory being zeroed if a 1227 * process is preempted and migrated between CPUs. 1228 */ 1229 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1230 info->reg_dczid, boot->reg_dczid); 1231 1232 /* If different, timekeeping will be broken (especially with KVM) */ 1233 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1234 info->reg_cntfrq, boot->reg_cntfrq); 1235 1236 /* 1237 * The kernel uses self-hosted debug features and expects CPUs to 1238 * support identical debug features. We presently need CTX_CMPs, WRPs, 1239 * and BRPs to be identical. 1240 * ID_AA64DFR1 is currently RES0. 1241 */ 1242 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1243 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1244 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1245 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1246 /* 1247 * Even in big.LITTLE, processors should be identical instruction-set 1248 * wise. 1249 */ 1250 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1251 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1252 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1253 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1254 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1255 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1256 1257 /* 1258 * Differing PARange support is fine as long as all peripherals and 1259 * memory are mapped within the minimum PARange of all CPUs. 1260 * Linux should not care about secure memory. 1261 */ 1262 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1263 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1264 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1265 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1266 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1267 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1268 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1269 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1270 1271 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1272 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1273 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1274 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1275 1276 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1277 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1278 1279 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1280 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1281 1282 /* Probe vector lengths */ 1283 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1284 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1285 if (!system_capabilities_finalized()) { 1286 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1287 1288 vec_update_vq_map(ARM64_VEC_SVE); 1289 1290 cpacr_restore(cpacr); 1291 } 1292 } 1293 1294 if (IS_ENABLED(CONFIG_ARM64_SME) && 1295 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1296 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1297 1298 /* 1299 * We mask out SMPS since even if the hardware 1300 * supports priorities the kernel does not at present 1301 * and we block access to them. 1302 */ 1303 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1304 1305 /* Probe vector lengths */ 1306 if (!system_capabilities_finalized()) 1307 vec_update_vq_map(ARM64_VEC_SME); 1308 1309 cpacr_restore(cpacr); 1310 } 1311 1312 /* 1313 * The kernel uses the LDGM/STGM instructions and the number of tags 1314 * they read/write depends on the GMID_EL1.BS field. Check that the 1315 * value is the same on all CPUs. 1316 */ 1317 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1318 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1319 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1320 info->reg_gmid, boot->reg_gmid); 1321 } 1322 1323 /* 1324 * If we don't have AArch32 at all then skip the checks entirely 1325 * as the register values may be UNKNOWN and we're not going to be 1326 * using them for anything. 1327 * 1328 * This relies on a sanitised view of the AArch64 ID registers 1329 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1330 */ 1331 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1332 lazy_init_32bit_cpu_features(info, boot); 1333 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1334 &boot->aarch32); 1335 } 1336 1337 /* 1338 * Mismatched CPU features are a recipe for disaster. Don't even 1339 * pretend to support them. 1340 */ 1341 if (taint) { 1342 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1343 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1344 } 1345 } 1346 1347 u64 read_sanitised_ftr_reg(u32 id) 1348 { 1349 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1350 1351 if (!regp) 1352 return 0; 1353 return regp->sys_val; 1354 } 1355 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1356 1357 #define read_sysreg_case(r) \ 1358 case r: val = read_sysreg_s(r); break; 1359 1360 /* 1361 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1362 * Read the system register on the current CPU 1363 */ 1364 u64 __read_sysreg_by_encoding(u32 sys_id) 1365 { 1366 struct arm64_ftr_reg *regp; 1367 u64 val; 1368 1369 switch (sys_id) { 1370 read_sysreg_case(SYS_ID_PFR0_EL1); 1371 read_sysreg_case(SYS_ID_PFR1_EL1); 1372 read_sysreg_case(SYS_ID_PFR2_EL1); 1373 read_sysreg_case(SYS_ID_DFR0_EL1); 1374 read_sysreg_case(SYS_ID_DFR1_EL1); 1375 read_sysreg_case(SYS_ID_MMFR0_EL1); 1376 read_sysreg_case(SYS_ID_MMFR1_EL1); 1377 read_sysreg_case(SYS_ID_MMFR2_EL1); 1378 read_sysreg_case(SYS_ID_MMFR3_EL1); 1379 read_sysreg_case(SYS_ID_MMFR4_EL1); 1380 read_sysreg_case(SYS_ID_MMFR5_EL1); 1381 read_sysreg_case(SYS_ID_ISAR0_EL1); 1382 read_sysreg_case(SYS_ID_ISAR1_EL1); 1383 read_sysreg_case(SYS_ID_ISAR2_EL1); 1384 read_sysreg_case(SYS_ID_ISAR3_EL1); 1385 read_sysreg_case(SYS_ID_ISAR4_EL1); 1386 read_sysreg_case(SYS_ID_ISAR5_EL1); 1387 read_sysreg_case(SYS_ID_ISAR6_EL1); 1388 read_sysreg_case(SYS_MVFR0_EL1); 1389 read_sysreg_case(SYS_MVFR1_EL1); 1390 read_sysreg_case(SYS_MVFR2_EL1); 1391 1392 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1393 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1394 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1395 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1396 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1397 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1398 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1399 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1400 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1401 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1402 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1403 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1404 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1405 1406 read_sysreg_case(SYS_CNTFRQ_EL0); 1407 read_sysreg_case(SYS_CTR_EL0); 1408 read_sysreg_case(SYS_DCZID_EL0); 1409 1410 default: 1411 BUG(); 1412 return 0; 1413 } 1414 1415 regp = get_arm64_ftr_reg(sys_id); 1416 if (regp) { 1417 val &= ~regp->override->mask; 1418 val |= (regp->override->val & regp->override->mask); 1419 } 1420 1421 return val; 1422 } 1423 1424 #include <linux/irqchip/arm-gic-v3.h> 1425 1426 static bool 1427 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1428 { 1429 return true; 1430 } 1431 1432 static bool 1433 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1434 { 1435 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1436 entry->field_width, 1437 entry->sign); 1438 1439 return val >= entry->min_field_value; 1440 } 1441 1442 static u64 1443 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1444 { 1445 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1446 if (scope == SCOPE_SYSTEM) 1447 return read_sanitised_ftr_reg(entry->sys_reg); 1448 else 1449 return __read_sysreg_by_encoding(entry->sys_reg); 1450 } 1451 1452 static bool 1453 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1454 { 1455 int mask; 1456 struct arm64_ftr_reg *regp; 1457 u64 val = read_scoped_sysreg(entry, scope); 1458 1459 regp = get_arm64_ftr_reg(entry->sys_reg); 1460 if (!regp) 1461 return false; 1462 1463 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1464 entry->field_pos, 1465 entry->field_width); 1466 if (!mask) 1467 return false; 1468 1469 return feature_matches(val, entry); 1470 } 1471 1472 static bool 1473 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1474 { 1475 u64 val = read_scoped_sysreg(entry, scope); 1476 return feature_matches(val, entry); 1477 } 1478 1479 const struct cpumask *system_32bit_el0_cpumask(void) 1480 { 1481 if (!system_supports_32bit_el0()) 1482 return cpu_none_mask; 1483 1484 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1485 return cpu_32bit_el0_mask; 1486 1487 return cpu_possible_mask; 1488 } 1489 1490 static int __init parse_32bit_el0_param(char *str) 1491 { 1492 allow_mismatched_32bit_el0 = true; 1493 return 0; 1494 } 1495 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1496 1497 static ssize_t aarch32_el0_show(struct device *dev, 1498 struct device_attribute *attr, char *buf) 1499 { 1500 const struct cpumask *mask = system_32bit_el0_cpumask(); 1501 1502 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1503 } 1504 static const DEVICE_ATTR_RO(aarch32_el0); 1505 1506 static int __init aarch32_el0_sysfs_init(void) 1507 { 1508 struct device *dev_root; 1509 int ret = 0; 1510 1511 if (!allow_mismatched_32bit_el0) 1512 return 0; 1513 1514 dev_root = bus_get_dev_root(&cpu_subsys); 1515 if (dev_root) { 1516 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1517 put_device(dev_root); 1518 } 1519 return ret; 1520 } 1521 device_initcall(aarch32_el0_sysfs_init); 1522 1523 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1524 { 1525 if (!has_cpuid_feature(entry, scope)) 1526 return allow_mismatched_32bit_el0; 1527 1528 if (scope == SCOPE_SYSTEM) 1529 pr_info("detected: 32-bit EL0 Support\n"); 1530 1531 return true; 1532 } 1533 1534 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1535 { 1536 bool has_sre; 1537 1538 if (!has_cpuid_feature(entry, scope)) 1539 return false; 1540 1541 has_sre = gic_enable_sre(); 1542 if (!has_sre) 1543 pr_warn_once("%s present but disabled by higher exception level\n", 1544 entry->desc); 1545 1546 return has_sre; 1547 } 1548 1549 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1550 { 1551 u32 midr = read_cpuid_id(); 1552 1553 /* Cavium ThunderX pass 1.x and 2.x */ 1554 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1555 MIDR_CPU_VAR_REV(0, 0), 1556 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1557 } 1558 1559 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1560 int scope) 1561 { 1562 u64 ctr; 1563 1564 if (scope == SCOPE_SYSTEM) 1565 ctr = arm64_ftr_reg_ctrel0.sys_val; 1566 else 1567 ctr = read_cpuid_effective_cachetype(); 1568 1569 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1570 } 1571 1572 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1573 { 1574 /* 1575 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1576 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1577 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1578 * value. 1579 */ 1580 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1581 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1582 } 1583 1584 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1585 int scope) 1586 { 1587 u64 ctr; 1588 1589 if (scope == SCOPE_SYSTEM) 1590 ctr = arm64_ftr_reg_ctrel0.sys_val; 1591 else 1592 ctr = read_cpuid_cachetype(); 1593 1594 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1595 } 1596 1597 static bool __maybe_unused 1598 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1599 { 1600 /* 1601 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1602 * may share TLB entries with a CPU stuck in the crashed 1603 * kernel. 1604 */ 1605 if (is_kdump_kernel()) 1606 return false; 1607 1608 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1609 return false; 1610 1611 return has_cpuid_feature(entry, scope); 1612 } 1613 1614 /* 1615 * This check is triggered during the early boot before the cpufeature 1616 * is initialised. Checking the status on the local CPU allows the boot 1617 * CPU to detect the need for non-global mappings and thus avoiding a 1618 * pagetable re-write after all the CPUs are booted. This check will be 1619 * anyway run on individual CPUs, allowing us to get the consistent 1620 * state once the SMP CPUs are up and thus make the switch to non-global 1621 * mappings if required. 1622 */ 1623 bool kaslr_requires_kpti(void) 1624 { 1625 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1626 return false; 1627 1628 /* 1629 * E0PD does a similar job to KPTI so can be used instead 1630 * where available. 1631 */ 1632 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1633 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1634 if (cpuid_feature_extract_unsigned_field(mmfr2, 1635 ID_AA64MMFR2_EL1_E0PD_SHIFT)) 1636 return false; 1637 } 1638 1639 /* 1640 * Systems affected by Cavium erratum 24756 are incompatible 1641 * with KPTI. 1642 */ 1643 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1644 extern const struct midr_range cavium_erratum_27456_cpus[]; 1645 1646 if (is_midr_in_range_list(read_cpuid_id(), 1647 cavium_erratum_27456_cpus)) 1648 return false; 1649 } 1650 1651 return kaslr_enabled(); 1652 } 1653 1654 static bool __meltdown_safe = true; 1655 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1656 1657 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1658 int scope) 1659 { 1660 /* List of CPUs that are not vulnerable and don't need KPTI */ 1661 static const struct midr_range kpti_safe_list[] = { 1662 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1663 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1664 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1665 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1666 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1667 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1668 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1669 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1670 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1671 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1672 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1673 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1674 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1675 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1676 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1677 { /* sentinel */ } 1678 }; 1679 char const *str = "kpti command line option"; 1680 bool meltdown_safe; 1681 1682 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1683 1684 /* Defer to CPU feature registers */ 1685 if (has_cpuid_feature(entry, scope)) 1686 meltdown_safe = true; 1687 1688 if (!meltdown_safe) 1689 __meltdown_safe = false; 1690 1691 /* 1692 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1693 * ThunderX leads to apparent I-cache corruption of kernel text, which 1694 * ends as well as you might imagine. Don't even try. We cannot rely 1695 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1696 * because cpucap detection order may change. However, since we know 1697 * affected CPUs are always in a homogeneous configuration, it is 1698 * safe to rely on this_cpu_has_cap() here. 1699 */ 1700 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1701 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1702 __kpti_forced = -1; 1703 } 1704 1705 /* Useful for KASLR robustness */ 1706 if (kaslr_requires_kpti()) { 1707 if (!__kpti_forced) { 1708 str = "KASLR"; 1709 __kpti_forced = 1; 1710 } 1711 } 1712 1713 if (cpu_mitigations_off() && !__kpti_forced) { 1714 str = "mitigations=off"; 1715 __kpti_forced = -1; 1716 } 1717 1718 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1719 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1720 return false; 1721 } 1722 1723 /* Forced? */ 1724 if (__kpti_forced) { 1725 pr_info_once("kernel page table isolation forced %s by %s\n", 1726 __kpti_forced > 0 ? "ON" : "OFF", str); 1727 return __kpti_forced > 0; 1728 } 1729 1730 return !meltdown_safe; 1731 } 1732 1733 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1734 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1735 1736 extern 1737 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1738 phys_addr_t size, pgprot_t prot, 1739 phys_addr_t (*pgtable_alloc)(int), int flags); 1740 1741 static phys_addr_t __initdata kpti_ng_temp_alloc; 1742 1743 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1744 { 1745 kpti_ng_temp_alloc -= PAGE_SIZE; 1746 return kpti_ng_temp_alloc; 1747 } 1748 1749 static int __init __kpti_install_ng_mappings(void *__unused) 1750 { 1751 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1752 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1753 kpti_remap_fn *remap_fn; 1754 1755 int cpu = smp_processor_id(); 1756 int levels = CONFIG_PGTABLE_LEVELS; 1757 int order = order_base_2(levels); 1758 u64 kpti_ng_temp_pgd_pa = 0; 1759 pgd_t *kpti_ng_temp_pgd; 1760 u64 alloc = 0; 1761 1762 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1763 1764 if (!cpu) { 1765 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1766 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1767 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1768 1769 // 1770 // Create a minimal page table hierarchy that permits us to map 1771 // the swapper page tables temporarily as we traverse them. 1772 // 1773 // The physical pages are laid out as follows: 1774 // 1775 // +--------+-/-------+-/------ +-\\--------+ 1776 // : PTE[] : | PMD[] : | PUD[] : || PGD[] : 1777 // +--------+-\-------+-\------ +-//--------+ 1778 // ^ 1779 // The first page is mapped into this hierarchy at a PMD_SHIFT 1780 // aligned virtual address, so that we can manipulate the PTE 1781 // level entries while the mapping is active. The first entry 1782 // covers the PTE[] page itself, the remaining entries are free 1783 // to be used as a ad-hoc fixmap. 1784 // 1785 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1786 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1787 kpti_ng_pgd_alloc, 0); 1788 } 1789 1790 cpu_install_idmap(); 1791 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1792 cpu_uninstall_idmap(); 1793 1794 if (!cpu) { 1795 free_pages(alloc, order); 1796 arm64_use_ng_mappings = true; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static void __init kpti_install_ng_mappings(void) 1803 { 1804 /* 1805 * We don't need to rewrite the page-tables if either we've done 1806 * it already or we have KASLR enabled and therefore have not 1807 * created any global mappings at all. 1808 */ 1809 if (arm64_use_ng_mappings) 1810 return; 1811 1812 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1813 } 1814 1815 #else 1816 static inline void kpti_install_ng_mappings(void) 1817 { 1818 } 1819 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1820 1821 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1822 { 1823 if (__this_cpu_read(this_cpu_vector) == vectors) { 1824 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1825 1826 __this_cpu_write(this_cpu_vector, v); 1827 } 1828 1829 } 1830 1831 static int __init parse_kpti(char *str) 1832 { 1833 bool enabled; 1834 int ret = kstrtobool(str, &enabled); 1835 1836 if (ret) 1837 return ret; 1838 1839 __kpti_forced = enabled ? 1 : -1; 1840 return 0; 1841 } 1842 early_param("kpti", parse_kpti); 1843 1844 #ifdef CONFIG_ARM64_HW_AFDBM 1845 static struct cpumask dbm_cpus __read_mostly; 1846 1847 static inline void __cpu_enable_hw_dbm(void) 1848 { 1849 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1850 1851 write_sysreg(tcr, tcr_el1); 1852 isb(); 1853 local_flush_tlb_all(); 1854 } 1855 1856 static bool cpu_has_broken_dbm(void) 1857 { 1858 /* List of CPUs which have broken DBM support. */ 1859 static const struct midr_range cpus[] = { 1860 #ifdef CONFIG_ARM64_ERRATUM_1024718 1861 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1862 /* Kryo4xx Silver (rdpe => r1p0) */ 1863 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1864 #endif 1865 #ifdef CONFIG_ARM64_ERRATUM_2051678 1866 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1867 #endif 1868 {}, 1869 }; 1870 1871 return is_midr_in_range_list(read_cpuid_id(), cpus); 1872 } 1873 1874 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1875 { 1876 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1877 !cpu_has_broken_dbm(); 1878 } 1879 1880 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1881 { 1882 if (cpu_can_use_dbm(cap)) { 1883 __cpu_enable_hw_dbm(); 1884 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 1885 } 1886 } 1887 1888 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1889 int __unused) 1890 { 1891 /* 1892 * DBM is a non-conflicting feature. i.e, the kernel can safely 1893 * run a mix of CPUs with and without the feature. So, we 1894 * unconditionally enable the capability to allow any late CPU 1895 * to use the feature. We only enable the control bits on the 1896 * CPU, if it is supported. 1897 */ 1898 1899 return true; 1900 } 1901 1902 #endif 1903 1904 #ifdef CONFIG_ARM64_AMU_EXTN 1905 1906 /* 1907 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1908 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1909 * information regarding all the events that it supports. When a CPU bit is 1910 * set in the cpumask, the user of this feature can only rely on the presence 1911 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1912 * counters are enabled or access to these counters is enabled by code 1913 * executed at higher exception levels (firmware). 1914 */ 1915 static struct cpumask amu_cpus __read_mostly; 1916 1917 bool cpu_has_amu_feat(int cpu) 1918 { 1919 return cpumask_test_cpu(cpu, &amu_cpus); 1920 } 1921 1922 int get_cpu_with_amu_feat(void) 1923 { 1924 return cpumask_any(&amu_cpus); 1925 } 1926 1927 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1928 { 1929 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1930 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1931 1932 /* 0 reference values signal broken/disabled counters */ 1933 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1934 update_freq_counters_refs(); 1935 } 1936 } 1937 1938 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1939 int __unused) 1940 { 1941 /* 1942 * The AMU extension is a non-conflicting feature: the kernel can 1943 * safely run a mix of CPUs with and without support for the 1944 * activity monitors extension. Therefore, unconditionally enable 1945 * the capability to allow any late CPU to use the feature. 1946 * 1947 * With this feature unconditionally enabled, the cpu_enable 1948 * function will be called for all CPUs that match the criteria, 1949 * including secondary and hotplugged, marking this feature as 1950 * present on that respective CPU. The enable function will also 1951 * print a detection message. 1952 */ 1953 1954 return true; 1955 } 1956 #else 1957 int get_cpu_with_amu_feat(void) 1958 { 1959 return nr_cpu_ids; 1960 } 1961 #endif 1962 1963 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1964 { 1965 return is_kernel_in_hyp_mode(); 1966 } 1967 1968 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1969 { 1970 /* 1971 * Copy register values that aren't redirected by hardware. 1972 * 1973 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1974 * this value to tpidr_el2 before we patch the code. Once we've done 1975 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1976 * do anything here. 1977 */ 1978 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1979 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1980 } 1981 1982 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 1983 int scope) 1984 { 1985 if (kvm_get_mode() != KVM_MODE_NV) 1986 return false; 1987 1988 if (!has_cpuid_feature(cap, scope)) { 1989 pr_warn("unavailable: %s\n", cap->desc); 1990 return false; 1991 } 1992 1993 return true; 1994 } 1995 1996 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 1997 int __unused) 1998 { 1999 u64 val; 2000 2001 val = read_sysreg(id_aa64mmfr1_el1); 2002 if (!cpuid_feature_extract_unsigned_field(val, ID_AA64MMFR1_EL1_VH_SHIFT)) 2003 return false; 2004 2005 val = arm64_sw_feature_override.val & arm64_sw_feature_override.mask; 2006 return cpuid_feature_extract_unsigned_field(val, ARM64_SW_FEATURE_OVERRIDE_HVHE); 2007 } 2008 2009 #ifdef CONFIG_ARM64_PAN 2010 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2011 { 2012 /* 2013 * We modify PSTATE. This won't work from irq context as the PSTATE 2014 * is discarded once we return from the exception. 2015 */ 2016 WARN_ON_ONCE(in_interrupt()); 2017 2018 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2019 set_pstate_pan(1); 2020 } 2021 #endif /* CONFIG_ARM64_PAN */ 2022 2023 #ifdef CONFIG_ARM64_RAS_EXTN 2024 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2025 { 2026 /* Firmware may have left a deferred SError in this register. */ 2027 write_sysreg_s(0, SYS_DISR_EL1); 2028 } 2029 #endif /* CONFIG_ARM64_RAS_EXTN */ 2030 2031 #ifdef CONFIG_ARM64_PTR_AUTH 2032 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2033 { 2034 int boot_val, sec_val; 2035 2036 /* We don't expect to be called with SCOPE_SYSTEM */ 2037 WARN_ON(scope == SCOPE_SYSTEM); 2038 /* 2039 * The ptr-auth feature levels are not intercompatible with lower 2040 * levels. Hence we must match ptr-auth feature level of the secondary 2041 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2042 * from the sanitised register whereas direct register read is done for 2043 * the secondary CPUs. 2044 * The sanitised feature state is guaranteed to match that of the 2045 * boot CPU as a mismatched secondary CPU is parked before it gets 2046 * a chance to update the state, with the capability. 2047 */ 2048 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2049 entry->field_pos, entry->sign); 2050 if (scope & SCOPE_BOOT_CPU) 2051 return boot_val >= entry->min_field_value; 2052 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2053 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2054 entry->field_pos, entry->sign); 2055 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2056 } 2057 2058 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2059 int scope) 2060 { 2061 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2062 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2063 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2064 2065 return apa || apa3 || api; 2066 } 2067 2068 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2069 int __unused) 2070 { 2071 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2072 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2073 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2074 2075 return gpa || gpa3 || gpi; 2076 } 2077 #endif /* CONFIG_ARM64_PTR_AUTH */ 2078 2079 #ifdef CONFIG_ARM64_E0PD 2080 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2081 { 2082 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2083 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2084 } 2085 #endif /* CONFIG_ARM64_E0PD */ 2086 2087 #ifdef CONFIG_ARM64_PSEUDO_NMI 2088 static bool enable_pseudo_nmi; 2089 2090 static int __init early_enable_pseudo_nmi(char *p) 2091 { 2092 return kstrtobool(p, &enable_pseudo_nmi); 2093 } 2094 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 2095 2096 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2097 int scope) 2098 { 2099 /* 2100 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2101 * feature, so will be detected earlier. 2102 */ 2103 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2104 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2105 return false; 2106 2107 return enable_pseudo_nmi; 2108 } 2109 2110 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2111 int scope) 2112 { 2113 /* 2114 * If we're not using priority masking then we won't be poking PMR_EL1, 2115 * and there's no need to relax synchronization of writes to it, and 2116 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2117 * that. 2118 * 2119 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2120 * feature, so will be detected earlier. 2121 */ 2122 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2123 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2124 return false; 2125 2126 /* 2127 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2128 * hint for interrupt distribution, a DSB is not necessary when 2129 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2130 * 2131 * Linux itself doesn't use 1:N distribution, so has no need to 2132 * set PMHE. The only reason to have it set is if EL3 requires it 2133 * (and we can't change it). 2134 */ 2135 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2136 } 2137 #endif 2138 2139 #ifdef CONFIG_ARM64_BTI 2140 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2141 { 2142 /* 2143 * Use of X16/X17 for tail-calls and trampolines that jump to 2144 * function entry points using BR is a requirement for 2145 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2146 * So, be strict and forbid other BRs using other registers to 2147 * jump onto a PACIxSP instruction: 2148 */ 2149 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2150 isb(); 2151 } 2152 #endif /* CONFIG_ARM64_BTI */ 2153 2154 #ifdef CONFIG_ARM64_MTE 2155 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2156 { 2157 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2158 2159 mte_cpu_setup(); 2160 2161 /* 2162 * Clear the tags in the zero page. This needs to be done via the 2163 * linear map which has the Tagged attribute. 2164 */ 2165 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2166 mte_clear_page_tags(lm_alias(empty_zero_page)); 2167 set_page_mte_tagged(ZERO_PAGE(0)); 2168 } 2169 2170 kasan_init_hw_tags_cpu(); 2171 } 2172 #endif /* CONFIG_ARM64_MTE */ 2173 2174 static void user_feature_fixup(void) 2175 { 2176 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2177 struct arm64_ftr_reg *regp; 2178 2179 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2180 if (regp) 2181 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2182 } 2183 } 2184 2185 static void elf_hwcap_fixup(void) 2186 { 2187 #ifdef CONFIG_COMPAT 2188 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2189 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2190 #endif /* CONFIG_COMPAT */ 2191 } 2192 2193 #ifdef CONFIG_KVM 2194 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2195 { 2196 return kvm_get_mode() == KVM_MODE_PROTECTED; 2197 } 2198 #endif /* CONFIG_KVM */ 2199 2200 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2201 { 2202 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2203 } 2204 2205 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2206 { 2207 set_pstate_dit(1); 2208 } 2209 2210 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2211 { 2212 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2213 } 2214 2215 /* Internal helper functions to match cpu capability type */ 2216 static bool 2217 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2218 { 2219 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2220 } 2221 2222 static bool 2223 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2224 { 2225 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2226 } 2227 2228 static bool 2229 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2230 { 2231 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2232 } 2233 2234 static const struct arm64_cpu_capabilities arm64_features[] = { 2235 { 2236 .capability = ARM64_ALWAYS_BOOT, 2237 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2238 .matches = has_always, 2239 }, 2240 { 2241 .capability = ARM64_ALWAYS_SYSTEM, 2242 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2243 .matches = has_always, 2244 }, 2245 { 2246 .desc = "GIC system register CPU interface", 2247 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2248 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2249 .matches = has_useable_gicv3_cpuif, 2250 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2251 }, 2252 { 2253 .desc = "Enhanced Counter Virtualization", 2254 .capability = ARM64_HAS_ECV, 2255 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2256 .matches = has_cpuid_feature, 2257 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2258 }, 2259 { 2260 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2261 .capability = ARM64_HAS_ECV_CNTPOFF, 2262 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2263 .matches = has_cpuid_feature, 2264 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2265 }, 2266 #ifdef CONFIG_ARM64_PAN 2267 { 2268 .desc = "Privileged Access Never", 2269 .capability = ARM64_HAS_PAN, 2270 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2271 .matches = has_cpuid_feature, 2272 .cpu_enable = cpu_enable_pan, 2273 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2274 }, 2275 #endif /* CONFIG_ARM64_PAN */ 2276 #ifdef CONFIG_ARM64_EPAN 2277 { 2278 .desc = "Enhanced Privileged Access Never", 2279 .capability = ARM64_HAS_EPAN, 2280 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2281 .matches = has_cpuid_feature, 2282 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2283 }, 2284 #endif /* CONFIG_ARM64_EPAN */ 2285 #ifdef CONFIG_ARM64_LSE_ATOMICS 2286 { 2287 .desc = "LSE atomic instructions", 2288 .capability = ARM64_HAS_LSE_ATOMICS, 2289 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2290 .matches = has_cpuid_feature, 2291 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2292 }, 2293 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2294 { 2295 .desc = "Software prefetching using PRFM", 2296 .capability = ARM64_HAS_NO_HW_PREFETCH, 2297 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2298 .matches = has_no_hw_prefetch, 2299 }, 2300 { 2301 .desc = "Virtualization Host Extensions", 2302 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2303 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2304 .matches = runs_at_el2, 2305 .cpu_enable = cpu_copy_el2regs, 2306 }, 2307 { 2308 .desc = "Nested Virtualization Support", 2309 .capability = ARM64_HAS_NESTED_VIRT, 2310 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2311 .matches = has_nested_virt_support, 2312 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) 2313 }, 2314 { 2315 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2316 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2317 .matches = has_32bit_el0, 2318 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2319 }, 2320 #ifdef CONFIG_KVM 2321 { 2322 .desc = "32-bit EL1 Support", 2323 .capability = ARM64_HAS_32BIT_EL1, 2324 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2325 .matches = has_cpuid_feature, 2326 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2327 }, 2328 { 2329 .desc = "Protected KVM", 2330 .capability = ARM64_KVM_PROTECTED_MODE, 2331 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2332 .matches = is_kvm_protected_mode, 2333 }, 2334 { 2335 .desc = "HCRX_EL2 register", 2336 .capability = ARM64_HAS_HCX, 2337 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2338 .matches = has_cpuid_feature, 2339 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2340 }, 2341 #endif 2342 { 2343 .desc = "Kernel page table isolation (KPTI)", 2344 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2345 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2346 .cpu_enable = cpu_enable_kpti, 2347 .matches = unmap_kernel_at_el0, 2348 /* 2349 * The ID feature fields below are used to indicate that 2350 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2351 * more details. 2352 */ 2353 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2354 }, 2355 { 2356 .capability = ARM64_HAS_FPSIMD, 2357 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2358 .matches = has_cpuid_feature, 2359 .cpu_enable = cpu_enable_fpsimd, 2360 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2361 }, 2362 #ifdef CONFIG_ARM64_PMEM 2363 { 2364 .desc = "Data cache clean to Point of Persistence", 2365 .capability = ARM64_HAS_DCPOP, 2366 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2367 .matches = has_cpuid_feature, 2368 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2369 }, 2370 { 2371 .desc = "Data cache clean to Point of Deep Persistence", 2372 .capability = ARM64_HAS_DCPODP, 2373 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2374 .matches = has_cpuid_feature, 2375 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2376 }, 2377 #endif 2378 #ifdef CONFIG_ARM64_SVE 2379 { 2380 .desc = "Scalable Vector Extension", 2381 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2382 .capability = ARM64_SVE, 2383 .cpu_enable = cpu_enable_sve, 2384 .matches = has_cpuid_feature, 2385 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2386 }, 2387 #endif /* CONFIG_ARM64_SVE */ 2388 #ifdef CONFIG_ARM64_RAS_EXTN 2389 { 2390 .desc = "RAS Extension Support", 2391 .capability = ARM64_HAS_RAS_EXTN, 2392 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2393 .matches = has_cpuid_feature, 2394 .cpu_enable = cpu_clear_disr, 2395 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2396 }, 2397 #endif /* CONFIG_ARM64_RAS_EXTN */ 2398 #ifdef CONFIG_ARM64_AMU_EXTN 2399 { 2400 .desc = "Activity Monitors Unit (AMU)", 2401 .capability = ARM64_HAS_AMU_EXTN, 2402 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2403 .matches = has_amu, 2404 .cpu_enable = cpu_amu_enable, 2405 .cpus = &amu_cpus, 2406 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2407 }, 2408 #endif /* CONFIG_ARM64_AMU_EXTN */ 2409 { 2410 .desc = "Data cache clean to the PoU not required for I/D coherence", 2411 .capability = ARM64_HAS_CACHE_IDC, 2412 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2413 .matches = has_cache_idc, 2414 .cpu_enable = cpu_emulate_effective_ctr, 2415 }, 2416 { 2417 .desc = "Instruction cache invalidation not required for I/D coherence", 2418 .capability = ARM64_HAS_CACHE_DIC, 2419 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2420 .matches = has_cache_dic, 2421 }, 2422 { 2423 .desc = "Stage-2 Force Write-Back", 2424 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2425 .capability = ARM64_HAS_STAGE2_FWB, 2426 .matches = has_cpuid_feature, 2427 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2428 }, 2429 { 2430 .desc = "ARMv8.4 Translation Table Level", 2431 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2432 .capability = ARM64_HAS_ARMv8_4_TTL, 2433 .matches = has_cpuid_feature, 2434 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2435 }, 2436 { 2437 .desc = "TLB range maintenance instructions", 2438 .capability = ARM64_HAS_TLB_RANGE, 2439 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2440 .matches = has_cpuid_feature, 2441 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2442 }, 2443 #ifdef CONFIG_ARM64_HW_AFDBM 2444 { 2445 .desc = "Hardware dirty bit management", 2446 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2447 .capability = ARM64_HW_DBM, 2448 .matches = has_hw_dbm, 2449 .cpu_enable = cpu_enable_hw_dbm, 2450 .cpus = &dbm_cpus, 2451 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2452 }, 2453 #endif 2454 { 2455 .desc = "CRC32 instructions", 2456 .capability = ARM64_HAS_CRC32, 2457 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2458 .matches = has_cpuid_feature, 2459 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2460 }, 2461 { 2462 .desc = "Speculative Store Bypassing Safe (SSBS)", 2463 .capability = ARM64_SSBS, 2464 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2465 .matches = has_cpuid_feature, 2466 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2467 }, 2468 #ifdef CONFIG_ARM64_CNP 2469 { 2470 .desc = "Common not Private translations", 2471 .capability = ARM64_HAS_CNP, 2472 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2473 .matches = has_useable_cnp, 2474 .cpu_enable = cpu_enable_cnp, 2475 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2476 }, 2477 #endif 2478 { 2479 .desc = "Speculation barrier (SB)", 2480 .capability = ARM64_HAS_SB, 2481 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2482 .matches = has_cpuid_feature, 2483 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2484 }, 2485 #ifdef CONFIG_ARM64_PTR_AUTH 2486 { 2487 .desc = "Address authentication (architected QARMA5 algorithm)", 2488 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2489 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2490 .matches = has_address_auth_cpucap, 2491 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2492 }, 2493 { 2494 .desc = "Address authentication (architected QARMA3 algorithm)", 2495 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2496 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2497 .matches = has_address_auth_cpucap, 2498 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2499 }, 2500 { 2501 .desc = "Address authentication (IMP DEF algorithm)", 2502 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2503 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2504 .matches = has_address_auth_cpucap, 2505 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2506 }, 2507 { 2508 .capability = ARM64_HAS_ADDRESS_AUTH, 2509 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2510 .matches = has_address_auth_metacap, 2511 }, 2512 { 2513 .desc = "Generic authentication (architected QARMA5 algorithm)", 2514 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2515 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2516 .matches = has_cpuid_feature, 2517 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2518 }, 2519 { 2520 .desc = "Generic authentication (architected QARMA3 algorithm)", 2521 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2522 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2523 .matches = has_cpuid_feature, 2524 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2525 }, 2526 { 2527 .desc = "Generic authentication (IMP DEF algorithm)", 2528 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2529 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2530 .matches = has_cpuid_feature, 2531 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2532 }, 2533 { 2534 .capability = ARM64_HAS_GENERIC_AUTH, 2535 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2536 .matches = has_generic_auth, 2537 }, 2538 #endif /* CONFIG_ARM64_PTR_AUTH */ 2539 #ifdef CONFIG_ARM64_PSEUDO_NMI 2540 { 2541 /* 2542 * Depends on having GICv3 2543 */ 2544 .desc = "IRQ priority masking", 2545 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2546 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2547 .matches = can_use_gic_priorities, 2548 }, 2549 { 2550 /* 2551 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2552 */ 2553 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2554 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2555 .matches = has_gic_prio_relaxed_sync, 2556 }, 2557 #endif 2558 #ifdef CONFIG_ARM64_E0PD 2559 { 2560 .desc = "E0PD", 2561 .capability = ARM64_HAS_E0PD, 2562 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2563 .cpu_enable = cpu_enable_e0pd, 2564 .matches = has_cpuid_feature, 2565 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2566 }, 2567 #endif 2568 { 2569 .desc = "Random Number Generator", 2570 .capability = ARM64_HAS_RNG, 2571 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2572 .matches = has_cpuid_feature, 2573 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2574 }, 2575 #ifdef CONFIG_ARM64_BTI 2576 { 2577 .desc = "Branch Target Identification", 2578 .capability = ARM64_BTI, 2579 #ifdef CONFIG_ARM64_BTI_KERNEL 2580 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2581 #else 2582 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2583 #endif 2584 .matches = has_cpuid_feature, 2585 .cpu_enable = bti_enable, 2586 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2587 }, 2588 #endif 2589 #ifdef CONFIG_ARM64_MTE 2590 { 2591 .desc = "Memory Tagging Extension", 2592 .capability = ARM64_MTE, 2593 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2594 .matches = has_cpuid_feature, 2595 .cpu_enable = cpu_enable_mte, 2596 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2597 }, 2598 { 2599 .desc = "Asymmetric MTE Tag Check Fault", 2600 .capability = ARM64_MTE_ASYMM, 2601 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2602 .matches = has_cpuid_feature, 2603 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2604 }, 2605 #endif /* CONFIG_ARM64_MTE */ 2606 { 2607 .desc = "RCpc load-acquire (LDAPR)", 2608 .capability = ARM64_HAS_LDAPR, 2609 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2610 .matches = has_cpuid_feature, 2611 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2612 }, 2613 { 2614 .desc = "Fine Grained Traps", 2615 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2616 .capability = ARM64_HAS_FGT, 2617 .matches = has_cpuid_feature, 2618 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2619 }, 2620 #ifdef CONFIG_ARM64_SME 2621 { 2622 .desc = "Scalable Matrix Extension", 2623 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2624 .capability = ARM64_SME, 2625 .matches = has_cpuid_feature, 2626 .cpu_enable = cpu_enable_sme, 2627 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2628 }, 2629 /* FA64 should be sorted after the base SME capability */ 2630 { 2631 .desc = "FA64", 2632 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2633 .capability = ARM64_SME_FA64, 2634 .matches = has_cpuid_feature, 2635 .cpu_enable = cpu_enable_fa64, 2636 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2637 }, 2638 { 2639 .desc = "SME2", 2640 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2641 .capability = ARM64_SME2, 2642 .matches = has_cpuid_feature, 2643 .cpu_enable = cpu_enable_sme2, 2644 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2645 }, 2646 #endif /* CONFIG_ARM64_SME */ 2647 { 2648 .desc = "WFx with timeout", 2649 .capability = ARM64_HAS_WFXT, 2650 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2651 .matches = has_cpuid_feature, 2652 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2653 }, 2654 { 2655 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2656 .capability = ARM64_HAS_TIDCP1, 2657 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2658 .matches = has_cpuid_feature, 2659 .cpu_enable = cpu_trap_el0_impdef, 2660 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2661 }, 2662 { 2663 .desc = "Data independent timing control (DIT)", 2664 .capability = ARM64_HAS_DIT, 2665 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2666 .matches = has_cpuid_feature, 2667 .cpu_enable = cpu_enable_dit, 2668 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2669 }, 2670 { 2671 .desc = "Memory Copy and Memory Set instructions", 2672 .capability = ARM64_HAS_MOPS, 2673 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2674 .matches = has_cpuid_feature, 2675 .cpu_enable = cpu_enable_mops, 2676 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2677 }, 2678 { 2679 .capability = ARM64_HAS_TCR2, 2680 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2681 .matches = has_cpuid_feature, 2682 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2683 }, 2684 { 2685 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2686 .capability = ARM64_HAS_S1PIE, 2687 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2688 .matches = has_cpuid_feature, 2689 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2690 }, 2691 { 2692 .desc = "VHE for hypervisor only", 2693 .capability = ARM64_KVM_HVHE, 2694 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2695 .matches = hvhe_possible, 2696 }, 2697 { 2698 .desc = "Enhanced Virtualization Traps", 2699 .capability = ARM64_HAS_EVT, 2700 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2701 .matches = has_cpuid_feature, 2702 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2703 }, 2704 {}, 2705 }; 2706 2707 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2708 .matches = has_user_cpuid_feature, \ 2709 ARM64_CPUID_FIELDS(reg, field, min_value) 2710 2711 #define __HWCAP_CAP(name, cap_type, cap) \ 2712 .desc = name, \ 2713 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2714 .hwcap_type = cap_type, \ 2715 .hwcap = cap, \ 2716 2717 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2718 { \ 2719 __HWCAP_CAP(#cap, cap_type, cap) \ 2720 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2721 } 2722 2723 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2724 { \ 2725 __HWCAP_CAP(#cap, cap_type, cap) \ 2726 .matches = cpucap_multi_entry_cap_matches, \ 2727 .match_list = list, \ 2728 } 2729 2730 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2731 { \ 2732 __HWCAP_CAP(#cap, cap_type, cap) \ 2733 .matches = match, \ 2734 } 2735 2736 #ifdef CONFIG_ARM64_PTR_AUTH 2737 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2738 { 2739 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2740 }, 2741 { 2742 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2743 }, 2744 { 2745 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2746 }, 2747 {}, 2748 }; 2749 2750 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2751 { 2752 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2753 }, 2754 { 2755 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2756 }, 2757 { 2758 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2759 }, 2760 {}, 2761 }; 2762 #endif 2763 2764 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2765 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2766 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2767 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2768 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2769 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2770 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2771 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2772 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2773 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2774 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2775 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2776 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2777 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2778 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2779 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2780 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2781 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2782 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2783 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2784 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2785 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2786 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2787 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2788 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2789 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2790 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2791 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2792 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2793 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 2794 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2795 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2796 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2797 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2798 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2799 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2800 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2801 #ifdef CONFIG_ARM64_SVE 2802 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2803 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2804 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2805 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2806 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2807 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2808 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 2809 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2810 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2811 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2812 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2813 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2814 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2815 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2816 #endif 2817 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2818 #ifdef CONFIG_ARM64_BTI 2819 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2820 #endif 2821 #ifdef CONFIG_ARM64_PTR_AUTH 2822 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2823 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2824 #endif 2825 #ifdef CONFIG_ARM64_MTE 2826 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2827 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2828 #endif /* CONFIG_ARM64_MTE */ 2829 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2830 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2831 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2832 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2833 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2834 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2835 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 2836 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 2837 #ifdef CONFIG_ARM64_SME 2838 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2839 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2840 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2841 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2842 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2843 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2844 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2845 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2846 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2847 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2848 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2849 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2850 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2851 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2852 #endif /* CONFIG_ARM64_SME */ 2853 {}, 2854 }; 2855 2856 #ifdef CONFIG_COMPAT 2857 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2858 { 2859 /* 2860 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2861 * in line with that of arm32 as in vfp_init(). We make sure that the 2862 * check is future proof, by making sure value is non-zero. 2863 */ 2864 u32 mvfr1; 2865 2866 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2867 if (scope == SCOPE_SYSTEM) 2868 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2869 else 2870 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2871 2872 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2873 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2874 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2875 } 2876 #endif 2877 2878 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2879 #ifdef CONFIG_COMPAT 2880 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2881 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2882 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2883 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2884 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2885 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2886 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2887 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2888 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2889 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2890 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2891 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2892 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2893 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2894 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2895 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2896 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2897 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2898 #endif 2899 {}, 2900 }; 2901 2902 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2903 { 2904 switch (cap->hwcap_type) { 2905 case CAP_HWCAP: 2906 cpu_set_feature(cap->hwcap); 2907 break; 2908 #ifdef CONFIG_COMPAT 2909 case CAP_COMPAT_HWCAP: 2910 compat_elf_hwcap |= (u32)cap->hwcap; 2911 break; 2912 case CAP_COMPAT_HWCAP2: 2913 compat_elf_hwcap2 |= (u32)cap->hwcap; 2914 break; 2915 #endif 2916 default: 2917 WARN_ON(1); 2918 break; 2919 } 2920 } 2921 2922 /* Check if we have a particular HWCAP enabled */ 2923 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2924 { 2925 bool rc; 2926 2927 switch (cap->hwcap_type) { 2928 case CAP_HWCAP: 2929 rc = cpu_have_feature(cap->hwcap); 2930 break; 2931 #ifdef CONFIG_COMPAT 2932 case CAP_COMPAT_HWCAP: 2933 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2934 break; 2935 case CAP_COMPAT_HWCAP2: 2936 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2937 break; 2938 #endif 2939 default: 2940 WARN_ON(1); 2941 rc = false; 2942 } 2943 2944 return rc; 2945 } 2946 2947 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2948 { 2949 /* We support emulation of accesses to CPU ID feature registers */ 2950 cpu_set_named_feature(CPUID); 2951 for (; hwcaps->matches; hwcaps++) 2952 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2953 cap_set_elf_hwcap(hwcaps); 2954 } 2955 2956 static void update_cpu_capabilities(u16 scope_mask) 2957 { 2958 int i; 2959 const struct arm64_cpu_capabilities *caps; 2960 2961 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2962 for (i = 0; i < ARM64_NCAPS; i++) { 2963 caps = cpucap_ptrs[i]; 2964 if (!caps || !(caps->type & scope_mask) || 2965 cpus_have_cap(caps->capability) || 2966 !caps->matches(caps, cpucap_default_scope(caps))) 2967 continue; 2968 2969 if (caps->desc && !caps->cpus) 2970 pr_info("detected: %s\n", caps->desc); 2971 2972 __set_bit(caps->capability, system_cpucaps); 2973 2974 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2975 set_bit(caps->capability, boot_cpucaps); 2976 } 2977 } 2978 2979 /* 2980 * Enable all the available capabilities on this CPU. The capabilities 2981 * with BOOT_CPU scope are handled separately and hence skipped here. 2982 */ 2983 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2984 { 2985 int i; 2986 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2987 2988 for_each_available_cap(i) { 2989 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 2990 2991 if (WARN_ON(!cap)) 2992 continue; 2993 2994 if (!(cap->type & non_boot_scope)) 2995 continue; 2996 2997 if (cap->cpu_enable) 2998 cap->cpu_enable(cap); 2999 } 3000 return 0; 3001 } 3002 3003 /* 3004 * Run through the enabled capabilities and enable() it on all active 3005 * CPUs 3006 */ 3007 static void __init enable_cpu_capabilities(u16 scope_mask) 3008 { 3009 int i; 3010 const struct arm64_cpu_capabilities *caps; 3011 bool boot_scope; 3012 3013 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3014 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3015 3016 for (i = 0; i < ARM64_NCAPS; i++) { 3017 unsigned int num; 3018 3019 caps = cpucap_ptrs[i]; 3020 if (!caps || !(caps->type & scope_mask)) 3021 continue; 3022 num = caps->capability; 3023 if (!cpus_have_cap(num)) 3024 continue; 3025 3026 if (boot_scope && caps->cpu_enable) 3027 /* 3028 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3029 * before any secondary CPU boots. Thus, each secondary 3030 * will enable the capability as appropriate via 3031 * check_local_cpu_capabilities(). The only exception is 3032 * the boot CPU, for which the capability must be 3033 * enabled here. This approach avoids costly 3034 * stop_machine() calls for this case. 3035 */ 3036 caps->cpu_enable(caps); 3037 } 3038 3039 /* 3040 * For all non-boot scope capabilities, use stop_machine() 3041 * as it schedules the work allowing us to modify PSTATE, 3042 * instead of on_each_cpu() which uses an IPI, giving us a 3043 * PSTATE that disappears when we return. 3044 */ 3045 if (!boot_scope) 3046 stop_machine(cpu_enable_non_boot_scope_capabilities, 3047 NULL, cpu_online_mask); 3048 } 3049 3050 /* 3051 * Run through the list of capabilities to check for conflicts. 3052 * If the system has already detected a capability, take necessary 3053 * action on this CPU. 3054 */ 3055 static void verify_local_cpu_caps(u16 scope_mask) 3056 { 3057 int i; 3058 bool cpu_has_cap, system_has_cap; 3059 const struct arm64_cpu_capabilities *caps; 3060 3061 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3062 3063 for (i = 0; i < ARM64_NCAPS; i++) { 3064 caps = cpucap_ptrs[i]; 3065 if (!caps || !(caps->type & scope_mask)) 3066 continue; 3067 3068 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3069 system_has_cap = cpus_have_cap(caps->capability); 3070 3071 if (system_has_cap) { 3072 /* 3073 * Check if the new CPU misses an advertised feature, 3074 * which is not safe to miss. 3075 */ 3076 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3077 break; 3078 /* 3079 * We have to issue cpu_enable() irrespective of 3080 * whether the CPU has it or not, as it is enabeld 3081 * system wide. It is upto the call back to take 3082 * appropriate action on this CPU. 3083 */ 3084 if (caps->cpu_enable) 3085 caps->cpu_enable(caps); 3086 } else { 3087 /* 3088 * Check if the CPU has this capability if it isn't 3089 * safe to have when the system doesn't. 3090 */ 3091 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3092 break; 3093 } 3094 } 3095 3096 if (i < ARM64_NCAPS) { 3097 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3098 smp_processor_id(), caps->capability, 3099 caps->desc, system_has_cap, cpu_has_cap); 3100 3101 if (cpucap_panic_on_conflict(caps)) 3102 cpu_panic_kernel(); 3103 else 3104 cpu_die_early(); 3105 } 3106 } 3107 3108 /* 3109 * Check for CPU features that are used in early boot 3110 * based on the Boot CPU value. 3111 */ 3112 static void check_early_cpu_features(void) 3113 { 3114 verify_cpu_asid_bits(); 3115 3116 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3117 } 3118 3119 static void 3120 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3121 { 3122 3123 for (; caps->matches; caps++) 3124 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3125 pr_crit("CPU%d: missing HWCAP: %s\n", 3126 smp_processor_id(), caps->desc); 3127 cpu_die_early(); 3128 } 3129 } 3130 3131 static void verify_local_elf_hwcaps(void) 3132 { 3133 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3134 3135 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3136 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3137 } 3138 3139 static void verify_sve_features(void) 3140 { 3141 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3142 3143 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3144 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3145 smp_processor_id()); 3146 cpu_die_early(); 3147 } 3148 3149 cpacr_restore(cpacr); 3150 } 3151 3152 static void verify_sme_features(void) 3153 { 3154 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3155 3156 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3157 pr_crit("CPU%d: SME: vector length support mismatch\n", 3158 smp_processor_id()); 3159 cpu_die_early(); 3160 } 3161 3162 cpacr_restore(cpacr); 3163 } 3164 3165 static void verify_hyp_capabilities(void) 3166 { 3167 u64 safe_mmfr1, mmfr0, mmfr1; 3168 int parange, ipa_max; 3169 unsigned int safe_vmid_bits, vmid_bits; 3170 3171 if (!IS_ENABLED(CONFIG_KVM)) 3172 return; 3173 3174 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3175 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3176 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3177 3178 /* Verify VMID bits */ 3179 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3180 vmid_bits = get_vmid_bits(mmfr1); 3181 if (vmid_bits < safe_vmid_bits) { 3182 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3183 cpu_die_early(); 3184 } 3185 3186 /* Verify IPA range */ 3187 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3188 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3189 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3190 if (ipa_max < get_kvm_ipa_limit()) { 3191 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3192 cpu_die_early(); 3193 } 3194 } 3195 3196 /* 3197 * Run through the enabled system capabilities and enable() it on this CPU. 3198 * The capabilities were decided based on the available CPUs at the boot time. 3199 * Any new CPU should match the system wide status of the capability. If the 3200 * new CPU doesn't have a capability which the system now has enabled, we 3201 * cannot do anything to fix it up and could cause unexpected failures. So 3202 * we park the CPU. 3203 */ 3204 static void verify_local_cpu_capabilities(void) 3205 { 3206 /* 3207 * The capabilities with SCOPE_BOOT_CPU are checked from 3208 * check_early_cpu_features(), as they need to be verified 3209 * on all secondary CPUs. 3210 */ 3211 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3212 verify_local_elf_hwcaps(); 3213 3214 if (system_supports_sve()) 3215 verify_sve_features(); 3216 3217 if (system_supports_sme()) 3218 verify_sme_features(); 3219 3220 if (is_hyp_mode_available()) 3221 verify_hyp_capabilities(); 3222 } 3223 3224 void check_local_cpu_capabilities(void) 3225 { 3226 /* 3227 * All secondary CPUs should conform to the early CPU features 3228 * in use by the kernel based on boot CPU. 3229 */ 3230 check_early_cpu_features(); 3231 3232 /* 3233 * If we haven't finalised the system capabilities, this CPU gets 3234 * a chance to update the errata work arounds and local features. 3235 * Otherwise, this CPU should verify that it has all the system 3236 * advertised capabilities. 3237 */ 3238 if (!system_capabilities_finalized()) 3239 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3240 else 3241 verify_local_cpu_capabilities(); 3242 } 3243 3244 static void __init setup_boot_cpu_capabilities(void) 3245 { 3246 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 3247 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3248 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 3249 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3250 } 3251 3252 bool this_cpu_has_cap(unsigned int n) 3253 { 3254 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3255 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3256 3257 if (cap) 3258 return cap->matches(cap, SCOPE_LOCAL_CPU); 3259 } 3260 3261 return false; 3262 } 3263 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3264 3265 /* 3266 * This helper function is used in a narrow window when, 3267 * - The system wide safe registers are set with all the SMP CPUs and, 3268 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3269 */ 3270 static bool __maybe_unused __system_matches_cap(unsigned int n) 3271 { 3272 if (n < ARM64_NCAPS) { 3273 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3274 3275 if (cap) 3276 return cap->matches(cap, SCOPE_SYSTEM); 3277 } 3278 return false; 3279 } 3280 3281 void cpu_set_feature(unsigned int num) 3282 { 3283 set_bit(num, elf_hwcap); 3284 } 3285 3286 bool cpu_have_feature(unsigned int num) 3287 { 3288 return test_bit(num, elf_hwcap); 3289 } 3290 EXPORT_SYMBOL_GPL(cpu_have_feature); 3291 3292 unsigned long cpu_get_elf_hwcap(void) 3293 { 3294 /* 3295 * We currently only populate the first 32 bits of AT_HWCAP. Please 3296 * note that for userspace compatibility we guarantee that bits 62 3297 * and 63 will always be returned as 0. 3298 */ 3299 return elf_hwcap[0]; 3300 } 3301 3302 unsigned long cpu_get_elf_hwcap2(void) 3303 { 3304 return elf_hwcap[1]; 3305 } 3306 3307 void __init setup_system_features(void) 3308 { 3309 int i; 3310 /* 3311 * The system-wide safe feature feature register values have been 3312 * finalized. Finalize and log the available system capabilities. 3313 */ 3314 update_cpu_capabilities(SCOPE_SYSTEM); 3315 if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 3316 !cpus_have_cap(ARM64_HAS_PAN)) 3317 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3318 3319 /* 3320 * Enable all the available capabilities which have not been enabled 3321 * already. 3322 */ 3323 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3324 3325 kpti_install_ng_mappings(); 3326 3327 sve_setup(); 3328 sme_setup(); 3329 3330 /* 3331 * Check for sane CTR_EL0.CWG value. 3332 */ 3333 if (!cache_type_cwg()) 3334 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3335 ARCH_DMA_MINALIGN); 3336 3337 for (i = 0; i < ARM64_NCAPS; i++) { 3338 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3339 3340 if (caps && caps->cpus && caps->desc && 3341 cpumask_any(caps->cpus) < nr_cpu_ids) 3342 pr_info("detected: %s on CPU%*pbl\n", 3343 caps->desc, cpumask_pr_args(caps->cpus)); 3344 } 3345 } 3346 3347 void __init setup_user_features(void) 3348 { 3349 user_feature_fixup(); 3350 3351 setup_elf_hwcaps(arm64_elf_hwcaps); 3352 3353 if (system_supports_32bit_el0()) { 3354 setup_elf_hwcaps(compat_elf_hwcaps); 3355 elf_hwcap_fixup(); 3356 } 3357 3358 minsigstksz_setup(); 3359 } 3360 3361 static int enable_mismatched_32bit_el0(unsigned int cpu) 3362 { 3363 /* 3364 * The first 32-bit-capable CPU we detected and so can no longer 3365 * be offlined by userspace. -1 indicates we haven't yet onlined 3366 * a 32-bit-capable CPU. 3367 */ 3368 static int lucky_winner = -1; 3369 3370 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3371 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3372 3373 if (cpu_32bit) { 3374 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3375 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3376 } 3377 3378 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3379 return 0; 3380 3381 if (lucky_winner >= 0) 3382 return 0; 3383 3384 /* 3385 * We've detected a mismatch. We need to keep one of our CPUs with 3386 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3387 * every CPU in the system for a 32-bit task. 3388 */ 3389 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3390 cpu_active_mask); 3391 get_cpu_device(lucky_winner)->offline_disabled = true; 3392 setup_elf_hwcaps(compat_elf_hwcaps); 3393 elf_hwcap_fixup(); 3394 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3395 cpu, lucky_winner); 3396 return 0; 3397 } 3398 3399 static int __init init_32bit_el0_mask(void) 3400 { 3401 if (!allow_mismatched_32bit_el0) 3402 return 0; 3403 3404 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3405 return -ENOMEM; 3406 3407 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3408 "arm64/mismatched_32bit_el0:online", 3409 enable_mismatched_32bit_el0, NULL); 3410 } 3411 subsys_initcall_sync(init_32bit_el0_mask); 3412 3413 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3414 { 3415 cpu_enable_swapper_cnp(); 3416 } 3417 3418 /* 3419 * We emulate only the following system register space. 3420 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3421 * See Table C5-6 System instruction encodings for System register accesses, 3422 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3423 */ 3424 static inline bool __attribute_const__ is_emulated(u32 id) 3425 { 3426 return (sys_reg_Op0(id) == 0x3 && 3427 sys_reg_CRn(id) == 0x0 && 3428 sys_reg_Op1(id) == 0x0 && 3429 (sys_reg_CRm(id) == 0 || 3430 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3431 } 3432 3433 /* 3434 * With CRm == 0, reg should be one of : 3435 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3436 */ 3437 static inline int emulate_id_reg(u32 id, u64 *valp) 3438 { 3439 switch (id) { 3440 case SYS_MIDR_EL1: 3441 *valp = read_cpuid_id(); 3442 break; 3443 case SYS_MPIDR_EL1: 3444 *valp = SYS_MPIDR_SAFE_VAL; 3445 break; 3446 case SYS_REVIDR_EL1: 3447 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3448 *valp = 0; 3449 break; 3450 default: 3451 return -EINVAL; 3452 } 3453 3454 return 0; 3455 } 3456 3457 static int emulate_sys_reg(u32 id, u64 *valp) 3458 { 3459 struct arm64_ftr_reg *regp; 3460 3461 if (!is_emulated(id)) 3462 return -EINVAL; 3463 3464 if (sys_reg_CRm(id) == 0) 3465 return emulate_id_reg(id, valp); 3466 3467 regp = get_arm64_ftr_reg_nowarn(id); 3468 if (regp) 3469 *valp = arm64_ftr_reg_user_value(regp); 3470 else 3471 /* 3472 * The untracked registers are either IMPLEMENTATION DEFINED 3473 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3474 */ 3475 *valp = 0; 3476 return 0; 3477 } 3478 3479 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3480 { 3481 int rc; 3482 u64 val; 3483 3484 rc = emulate_sys_reg(sys_reg, &val); 3485 if (!rc) { 3486 pt_regs_write_reg(regs, rt, val); 3487 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3488 } 3489 return rc; 3490 } 3491 3492 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3493 { 3494 u32 sys_reg, rt; 3495 3496 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3497 return false; 3498 3499 /* 3500 * sys_reg values are defined as used in mrs/msr instruction. 3501 * shift the imm value to get the encoding. 3502 */ 3503 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3504 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3505 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3506 } 3507 3508 enum mitigation_state arm64_get_meltdown_state(void) 3509 { 3510 if (__meltdown_safe) 3511 return SPECTRE_UNAFFECTED; 3512 3513 if (arm64_kernel_unmapped_at_el0()) 3514 return SPECTRE_MITIGATED; 3515 3516 return SPECTRE_VULNERABLE; 3517 } 3518 3519 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3520 char *buf) 3521 { 3522 switch (arm64_get_meltdown_state()) { 3523 case SPECTRE_UNAFFECTED: 3524 return sprintf(buf, "Not affected\n"); 3525 3526 case SPECTRE_MITIGATED: 3527 return sprintf(buf, "Mitigation: PTI\n"); 3528 3529 default: 3530 return sprintf(buf, "Vulnerable\n"); 3531 } 3532 } 3533