1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 15/dts-v1/; 16/plugin/; 17 18&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 19 #address-cells = <1>; 20 #size-cells = <0>; 21 pinctrl-names = "default", "gpio"; 22 pinctrl-0 = <&pinctrl_i2c1_default>; 23 pinctrl-1 = <&pinctrl_i2c1_gpio>; 24 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 25 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 26 27 /* u14 - 0x40 - ina260 */ 28 /* u43 - 0x2d - usb5744 */ 29 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 30}; 31 32&amba { 33 si5332_0: si5332_0 { /* u17 */ 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <125000000>; 37 }; 38 39 si5332_1: si5332_1 { /* u17 */ 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <25000000>; 43 }; 44 45 si5332_2: si5332_2 { /* u17 */ 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <48000000>; 49 }; 50 51 si5332_3: si5332_3 { /* u17 */ 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <24000000>; 55 }; 56 57 si5332_4: si5332_4 { /* u17 */ 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <26000000>; 61 }; 62 63 si5332_5: si5332_5 { /* u17 */ 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <27000000>; 67 }; 68}; 69 70/* DP/USB 3.0 */ 71&psgtr { 72 status = "okay"; 73 /* pcie, usb3, sata */ 74 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 75 clock-names = "ref0", "ref1", "ref2"; 76}; 77 78&zynqmp_dpsub { 79 status = "disabled"; 80 phy-names = "dp-phy0", "dp-phy1"; 81 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 82}; 83 84&zynqmp_dpdma { 85 status = "okay"; 86}; 87 88&usb0 { 89 status = "okay"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_usb0_default>; 92 phy-names = "usb3-phy"; 93 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 94}; 95 96&dwc3_0 { 97 status = "okay"; 98 dr_mode = "host"; 99 snps,usb3_lpm_capable; 100 maximum-speed = "super-speed"; 101}; 102 103&sdhci1 { /* on CC with tuned parameters */ 104 status = "okay"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_sdhci1_default>; 107 /* 108 * SD 3.0 requires level shifter and this property 109 * should be removed if the board has level shifter and 110 * need to work in UHS mode 111 */ 112 no-1-8-v; 113 disable-wp; 114 xlnx,mio-bank = <1>; 115 clk-phase-sd-hs = <126>, <60>; 116 clk-phase-uhs-sdr25 = <120>, <60>; 117 clk-phase-uhs-ddr50 = <126>, <48>; 118 assigned-clock-rates = <187498123>; 119}; 120 121&gem3 { /* required by spec */ 122 status = "okay"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_gem3_default>; 125 phy-handle = <&phy0>; 126 phy-mode = "rgmii-id"; 127 128 mdio: mdio { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 132 phy0: ethernet-phy@1 { 133 #phy-cells = <1>; 134 reg = <1>; 135 compatible = "ethernet-phy-id2000.a231"; 136 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 137 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 138 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 139 ti,dp83867-rxctrl-strap-quirk; 140 reset-assert-us = <100>; 141 reset-deassert-us = <280>; 142 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 143 }; 144 }; 145}; 146 147&pinctrl0 { /* required by spec */ 148 status = "okay"; 149 150 pinctrl_uart1_default: uart1-default { 151 conf { 152 groups = "uart1_9_grp"; 153 slew-rate = <SLEW_RATE_SLOW>; 154 power-source = <IO_STANDARD_LVCMOS18>; 155 drive-strength = <12>; 156 }; 157 158 conf-rx { 159 pins = "MIO37"; 160 bias-high-impedance; 161 }; 162 163 conf-tx { 164 pins = "MIO36"; 165 bias-disable; 166 }; 167 168 mux { 169 groups = "uart1_9_grp"; 170 function = "uart1"; 171 }; 172 }; 173 174 pinctrl_i2c1_default: i2c1-default { 175 conf { 176 groups = "i2c1_6_grp"; 177 bias-pull-up; 178 slew-rate = <SLEW_RATE_SLOW>; 179 power-source = <IO_STANDARD_LVCMOS18>; 180 }; 181 182 mux { 183 groups = "i2c1_6_grp"; 184 function = "i2c1"; 185 }; 186 }; 187 188 pinctrl_i2c1_gpio: i2c1-gpio { 189 conf { 190 groups = "gpio0_24_grp", "gpio0_25_grp"; 191 slew-rate = <SLEW_RATE_SLOW>; 192 power-source = <IO_STANDARD_LVCMOS18>; 193 }; 194 195 mux { 196 groups = "gpio0_24_grp", "gpio0_25_grp"; 197 function = "gpio0"; 198 }; 199 }; 200 201 pinctrl_gem3_default: gem3-default { 202 conf { 203 groups = "ethernet3_0_grp"; 204 slew-rate = <SLEW_RATE_SLOW>; 205 power-source = <IO_STANDARD_LVCMOS18>; 206 }; 207 208 conf-rx { 209 pins = "MIO70", "MIO72", "MIO74"; 210 bias-high-impedance; 211 low-power-disable; 212 }; 213 214 conf-bootstrap { 215 pins = "MIO71", "MIO73", "MIO75"; 216 bias-disable; 217 low-power-disable; 218 }; 219 220 conf-tx { 221 pins = "MIO64", "MIO65", "MIO66", 222 "MIO67", "MIO68", "MIO69"; 223 bias-disable; 224 low-power-enable; 225 }; 226 227 conf-mdio { 228 groups = "mdio3_0_grp"; 229 slew-rate = <SLEW_RATE_SLOW>; 230 power-source = <IO_STANDARD_LVCMOS18>; 231 bias-disable; 232 }; 233 234 mux-mdio { 235 function = "mdio3"; 236 groups = "mdio3_0_grp"; 237 }; 238 239 mux { 240 function = "ethernet3"; 241 groups = "ethernet3_0_grp"; 242 }; 243 }; 244 245 pinctrl_usb0_default: usb0-default { 246 conf { 247 groups = "usb0_0_grp"; 248 slew-rate = <SLEW_RATE_SLOW>; 249 power-source = <IO_STANDARD_LVCMOS18>; 250 }; 251 252 conf-rx { 253 pins = "MIO52", "MIO53", "MIO55"; 254 bias-high-impedance; 255 }; 256 257 conf-tx { 258 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 259 "MIO60", "MIO61", "MIO62", "MIO63"; 260 bias-disable; 261 }; 262 263 mux { 264 groups = "usb0_0_grp"; 265 function = "usb0"; 266 }; 267 }; 268 269 pinctrl_sdhci1_default: sdhci1-default { 270 conf { 271 groups = "sdio1_0_grp"; 272 slew-rate = <SLEW_RATE_SLOW>; 273 power-source = <IO_STANDARD_LVCMOS18>; 274 bias-disable; 275 }; 276 277 conf-cd { 278 groups = "sdio1_cd_0_grp"; 279 bias-high-impedance; 280 bias-pull-up; 281 slew-rate = <SLEW_RATE_SLOW>; 282 power-source = <IO_STANDARD_LVCMOS18>; 283 }; 284 285 mux-cd { 286 groups = "sdio1_cd_0_grp"; 287 function = "sdio1_cd"; 288 }; 289 290 mux { 291 groups = "sdio1_0_grp"; 292 function = "sdio1"; 293 }; 294 }; 295}; 296 297&uart1 { 298 status = "okay"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_uart1_default>; 301}; 302