1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for KV260 revA Carrier Card 4 * 5 * (C) Copyright 2020 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 14 15/dts-v1/; 16/plugin/; 17 18&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 19 #address-cells = <1>; 20 #size-cells = <0>; 21 pinctrl-names = "default", "gpio"; 22 pinctrl-0 = <&pinctrl_i2c1_default>; 23 pinctrl-1 = <&pinctrl_i2c1_gpio>; 24 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; 25 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; 26 27 /* u14 - 0x40 - ina260 */ 28 /* u43 - 0x2d - usb5744 */ 29 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ 30}; 31 32&amba { 33 si5332_0: si5332_0 { /* u17 */ 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <125000000>; 37 }; 38 39 si5332_1: si5332_1 { /* u17 */ 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <25000000>; 43 }; 44 45 si5332_2: si5332_2 { /* u17 */ 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <48000000>; 49 }; 50 51 si5332_3: si5332_3 { /* u17 */ 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <24000000>; 55 }; 56 57 si5332_4: si5332_4 { /* u17 */ 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <26000000>; 61 }; 62 63 si5332_5: si5332_5 { /* u17 */ 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <27000000>; 67 }; 68}; 69 70/* DP/USB 3.0 */ 71&psgtr { 72 status = "okay"; 73 /* pcie, usb3, sata */ 74 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; 75 clock-names = "ref0", "ref1", "ref2"; 76}; 77 78&zynqmp_dpsub { 79 status = "okay"; 80 phy-names = "dp-phy0", "dp-phy1"; 81 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; 82 assigned-clock-rates = <27000000>, <25000000>, <300000000>; 83}; 84 85&zynqmp_dpdma { 86 status = "okay"; 87 assigned-clock-rates = <600000000>; 88}; 89 90&usb0 { 91 status = "okay"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_usb0_default>; 94 phy-names = "usb3-phy"; 95 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 96}; 97 98&dwc3_0 { 99 status = "okay"; 100 dr_mode = "host"; 101 snps,usb3_lpm_capable; 102 maximum-speed = "super-speed"; 103}; 104 105&sdhci1 { /* on CC with tuned parameters */ 106 status = "okay"; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_sdhci1_default>; 109 /* 110 * SD 3.0 requires level shifter and this property 111 * should be removed if the board has level shifter and 112 * need to work in UHS mode 113 */ 114 no-1-8-v; 115 disable-wp; 116 xlnx,mio-bank = <1>; 117 clk-phase-sd-hs = <126>, <60>; 118 clk-phase-uhs-sdr25 = <120>, <60>; 119 clk-phase-uhs-ddr50 = <126>, <48>; 120 assigned-clock-rates = <187498123>; 121 bus-width = <4>; 122}; 123 124&gem3 { /* required by spec */ 125 status = "okay"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_gem3_default>; 128 phy-handle = <&phy0>; 129 phy-mode = "rgmii-id"; 130 131 mdio: mdio { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 phy0: ethernet-phy@1 { 136 #phy-cells = <1>; 137 reg = <1>; 138 compatible = "ethernet-phy-id2000.a231"; 139 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 140 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 141 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 142 ti,dp83867-rxctrl-strap-quirk; 143 reset-assert-us = <100>; 144 reset-deassert-us = <280>; 145 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; 146 }; 147 }; 148}; 149 150&pinctrl0 { /* required by spec */ 151 status = "okay"; 152 153 pinctrl_uart1_default: uart1-default { 154 conf { 155 groups = "uart1_9_grp"; 156 slew-rate = <SLEW_RATE_SLOW>; 157 power-source = <IO_STANDARD_LVCMOS18>; 158 drive-strength = <12>; 159 }; 160 161 conf-rx { 162 pins = "MIO37"; 163 bias-high-impedance; 164 }; 165 166 conf-tx { 167 pins = "MIO36"; 168 bias-disable; 169 }; 170 171 mux { 172 groups = "uart1_9_grp"; 173 function = "uart1"; 174 }; 175 }; 176 177 pinctrl_i2c1_default: i2c1-default { 178 conf { 179 groups = "i2c1_6_grp"; 180 bias-pull-up; 181 slew-rate = <SLEW_RATE_SLOW>; 182 power-source = <IO_STANDARD_LVCMOS18>; 183 }; 184 185 mux { 186 groups = "i2c1_6_grp"; 187 function = "i2c1"; 188 }; 189 }; 190 191 pinctrl_i2c1_gpio: i2c1-gpio { 192 conf { 193 groups = "gpio0_24_grp", "gpio0_25_grp"; 194 slew-rate = <SLEW_RATE_SLOW>; 195 power-source = <IO_STANDARD_LVCMOS18>; 196 }; 197 198 mux { 199 groups = "gpio0_24_grp", "gpio0_25_grp"; 200 function = "gpio0"; 201 }; 202 }; 203 204 pinctrl_gem3_default: gem3-default { 205 conf { 206 groups = "ethernet3_0_grp"; 207 slew-rate = <SLEW_RATE_SLOW>; 208 power-source = <IO_STANDARD_LVCMOS18>; 209 }; 210 211 conf-rx { 212 pins = "MIO70", "MIO72", "MIO74"; 213 bias-high-impedance; 214 low-power-disable; 215 }; 216 217 conf-bootstrap { 218 pins = "MIO71", "MIO73", "MIO75"; 219 bias-disable; 220 low-power-disable; 221 }; 222 223 conf-tx { 224 pins = "MIO64", "MIO65", "MIO66", 225 "MIO67", "MIO68", "MIO69"; 226 bias-disable; 227 low-power-enable; 228 }; 229 230 conf-mdio { 231 groups = "mdio3_0_grp"; 232 slew-rate = <SLEW_RATE_SLOW>; 233 power-source = <IO_STANDARD_LVCMOS18>; 234 bias-disable; 235 }; 236 237 mux-mdio { 238 function = "mdio3"; 239 groups = "mdio3_0_grp"; 240 }; 241 242 mux { 243 function = "ethernet3"; 244 groups = "ethernet3_0_grp"; 245 }; 246 }; 247 248 pinctrl_usb0_default: usb0-default { 249 conf { 250 groups = "usb0_0_grp"; 251 slew-rate = <SLEW_RATE_SLOW>; 252 power-source = <IO_STANDARD_LVCMOS18>; 253 }; 254 255 conf-rx { 256 pins = "MIO52", "MIO53", "MIO55"; 257 bias-high-impedance; 258 }; 259 260 conf-tx { 261 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 262 "MIO60", "MIO61", "MIO62", "MIO63"; 263 bias-disable; 264 }; 265 266 mux { 267 groups = "usb0_0_grp"; 268 function = "usb0"; 269 }; 270 }; 271 272 pinctrl_sdhci1_default: sdhci1-default { 273 conf { 274 groups = "sdio1_0_grp"; 275 slew-rate = <SLEW_RATE_SLOW>; 276 power-source = <IO_STANDARD_LVCMOS18>; 277 bias-disable; 278 }; 279 280 conf-cd { 281 groups = "sdio1_cd_0_grp"; 282 bias-high-impedance; 283 bias-pull-up; 284 slew-rate = <SLEW_RATE_SLOW>; 285 power-source = <IO_STANDARD_LVCMOS18>; 286 }; 287 288 mux-cd { 289 groups = "sdio1_cd_0_grp"; 290 function = "sdio1_cd"; 291 }; 292 293 mux { 294 groups = "sdio1_0_grp"; 295 function = "sdio1"; 296 }; 297 }; 298}; 299 300&uart1 { 301 status = "okay"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_uart1_default>; 304}; 305