1*b87c44ddSNishanth Menon// SPDX-License-Identifier: GPL-2.0-only OR MIT 2d361ed88SLokesh Vutla/* 3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family Main Domain peripherals 4d361ed88SLokesh Vutla * 5*b87c44ddSNishanth Menon * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6d361ed88SLokesh Vutla */ 7d361ed88SLokesh Vutla 84c1b22a9SKishon Vijay Abraham I/ { 94c1b22a9SKishon Vijay Abraham I serdes_refclk: serdes-refclk { 104c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 114c1b22a9SKishon Vijay Abraham I compatible = "fixed-clock"; 124c1b22a9SKishon Vijay Abraham I }; 134c1b22a9SKishon Vijay Abraham I}; 144c1b22a9SKishon Vijay Abraham I 15d361ed88SLokesh Vutla&cbass_main { 16d361ed88SLokesh Vutla msmc_ram: sram@70000000 { 17d361ed88SLokesh Vutla compatible = "mmio-sram"; 18d361ed88SLokesh Vutla reg = <0x00 0x70000000 0x00 0x100000>; 19d361ed88SLokesh Vutla #address-cells = <1>; 20d361ed88SLokesh Vutla #size-cells = <1>; 21d361ed88SLokesh Vutla ranges = <0x00 0x00 0x70000000 0x100000>; 22d361ed88SLokesh Vutla 23d361ed88SLokesh Vutla atf-sram@0 { 24d361ed88SLokesh Vutla reg = <0x00 0x20000>; 25d361ed88SLokesh Vutla }; 26d361ed88SLokesh Vutla }; 27d361ed88SLokesh Vutla 2815092952SRoger Quadros scm_conf: scm-conf@100000 { 2915092952SRoger Quadros compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 3015092952SRoger Quadros reg = <0x00 0x00100000 0x00 0x1c000>; 3115092952SRoger Quadros #address-cells = <1>; 3215092952SRoger Quadros #size-cells = <1>; 3315092952SRoger Quadros ranges = <0x00 0x00 0x00100000 0x1c000>; 3415092952SRoger Quadros 354d398490SKishon Vijay Abraham I serdes_ln_ctrl: mux-controller@4080 { 3615092952SRoger Quadros compatible = "mmio-mux"; 3715092952SRoger Quadros #mux-control-cells = <1>; 3815092952SRoger Quadros mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 3915092952SRoger Quadros <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 4015092952SRoger Quadros }; 419a09e6e9SRoger Quadros 42d3bac980SSiddharth Vadapalli cpsw0_phy_gmii_sel: phy@4044 { 43d3bac980SSiddharth Vadapalli compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44d3bac980SSiddharth Vadapalli ti,qsgmii-main-ports = <1>; 45d3bac980SSiddharth Vadapalli reg = <0x4044 0x10>; 46d3bac980SSiddharth Vadapalli #phy-cells = <1>; 47d3bac980SSiddharth Vadapalli }; 48d3bac980SSiddharth Vadapalli 499a09e6e9SRoger Quadros usb_serdes_mux: mux-controller@4000 { 509a09e6e9SRoger Quadros compatible = "mmio-mux"; 519a09e6e9SRoger Quadros #mux-control-cells = <1>; 529a09e6e9SRoger Quadros mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 539a09e6e9SRoger Quadros }; 5415092952SRoger Quadros }; 5515092952SRoger Quadros 56d361ed88SLokesh Vutla gic500: interrupt-controller@1800000 { 57d361ed88SLokesh Vutla compatible = "arm,gic-v3"; 58d361ed88SLokesh Vutla #address-cells = <2>; 59d361ed88SLokesh Vutla #size-cells = <2>; 60d361ed88SLokesh Vutla ranges; 61d361ed88SLokesh Vutla #interrupt-cells = <3>; 62d361ed88SLokesh Vutla interrupt-controller; 63d361ed88SLokesh Vutla reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 641a307cc2SNishanth Menon <0x00 0x01900000 0x00 0x100000>, /* GICR */ 651a307cc2SNishanth Menon <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 661a307cc2SNishanth Menon <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 671a307cc2SNishanth Menon <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 68d361ed88SLokesh Vutla 69d361ed88SLokesh Vutla /* vcpumntirq: virtual CPU interface maintenance interrupt */ 70d361ed88SLokesh Vutla interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71d361ed88SLokesh Vutla 72d361ed88SLokesh Vutla gic_its: msi-controller@1820000 { 73d361ed88SLokesh Vutla compatible = "arm,gic-v3-its"; 74d361ed88SLokesh Vutla reg = <0x00 0x01820000 0x00 0x10000>; 75d361ed88SLokesh Vutla socionext,synquacer-pre-its = <0x1000000 0x400000>; 76d361ed88SLokesh Vutla msi-controller; 77d361ed88SLokesh Vutla #msi-cells = <1>; 78d361ed88SLokesh Vutla }; 79d361ed88SLokesh Vutla }; 80d361ed88SLokesh Vutla 81cab12badSNishanth Menon main_gpio_intr: interrupt-controller@a00000 { 82d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 83cab12badSNishanth Menon reg = <0x00 0x00a00000 0x00 0x800>; 84d361ed88SLokesh Vutla ti,intr-trigger-type = <1>; 85d361ed88SLokesh Vutla interrupt-controller; 86d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 87d361ed88SLokesh Vutla #interrupt-cells = <1>; 88d361ed88SLokesh Vutla ti,sci = <&dmsc>; 89d361ed88SLokesh Vutla ti,sci-dev-id = <131>; 90d361ed88SLokesh Vutla ti,interrupt-ranges = <8 392 56>; 91d361ed88SLokesh Vutla }; 92d361ed88SLokesh Vutla 93d361ed88SLokesh Vutla main_navss: bus@30000000 { 946507bfa7SVignesh Raghavendra compatible = "simple-bus"; 95d361ed88SLokesh Vutla #address-cells = <2>; 96d361ed88SLokesh Vutla #size-cells = <2>; 97d361ed88SLokesh Vutla ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 98d361ed88SLokesh Vutla ti,sci-dev-id = <199>; 9952ae30f5SVignesh Raghavendra dma-coherent; 10052ae30f5SVignesh Raghavendra dma-ranges; 101d361ed88SLokesh Vutla 102cab12badSNishanth Menon main_navss_intr: interrupt-controller@310e0000 { 103d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 104cab12badSNishanth Menon reg = <0x00 0x310e0000 0x00 0x4000>; 105d361ed88SLokesh Vutla ti,intr-trigger-type = <4>; 106d361ed88SLokesh Vutla interrupt-controller; 107d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 108d361ed88SLokesh Vutla #interrupt-cells = <1>; 109d361ed88SLokesh Vutla ti,sci = <&dmsc>; 110d361ed88SLokesh Vutla ti,sci-dev-id = <213>; 111d361ed88SLokesh Vutla ti,interrupt-ranges = <0 64 64>, 112d361ed88SLokesh Vutla <64 448 64>, 113d361ed88SLokesh Vutla <128 672 64>; 114d361ed88SLokesh Vutla }; 115d361ed88SLokesh Vutla 116d361ed88SLokesh Vutla main_udmass_inta: msi-controller@33d00000 { 117d361ed88SLokesh Vutla compatible = "ti,sci-inta"; 118d361ed88SLokesh Vutla reg = <0x00 0x33d00000 0x00 0x100000>; 119d361ed88SLokesh Vutla interrupt-controller; 120d361ed88SLokesh Vutla #interrupt-cells = <0>; 121d361ed88SLokesh Vutla interrupt-parent = <&main_navss_intr>; 122d361ed88SLokesh Vutla msi-controller; 123d361ed88SLokesh Vutla ti,sci = <&dmsc>; 124d361ed88SLokesh Vutla ti,sci-dev-id = <209>; 125d361ed88SLokesh Vutla ti,interrupt-ranges = <0 0 256>; 126d361ed88SLokesh Vutla }; 127d361ed88SLokesh Vutla 128d361ed88SLokesh Vutla secure_proxy_main: mailbox@32c00000 { 129d361ed88SLokesh Vutla compatible = "ti,am654-secure-proxy"; 130d361ed88SLokesh Vutla #mbox-cells = <1>; 131d361ed88SLokesh Vutla reg-names = "target_data", "rt", "scfg"; 132d361ed88SLokesh Vutla reg = <0x00 0x32c00000 0x00 0x100000>, 133d361ed88SLokesh Vutla <0x00 0x32400000 0x00 0x100000>, 134d361ed88SLokesh Vutla <0x00 0x32800000 0x00 0x100000>; 135d361ed88SLokesh Vutla interrupt-names = "rx_011"; 136d361ed88SLokesh Vutla interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137d361ed88SLokesh Vutla }; 13846374264SPeter Ujfalusi 1391d7a01c4SSuman Anna hwspinlock: spinlock@30e00000 { 1401d7a01c4SSuman Anna compatible = "ti,am654-hwspinlock"; 1411d7a01c4SSuman Anna reg = <0x00 0x30e00000 0x00 0x1000>; 1421d7a01c4SSuman Anna #hwlock-cells = <1>; 1431d7a01c4SSuman Anna }; 1441d7a01c4SSuman Anna 145d15d1cfbSSuman Anna mailbox0_cluster0: mailbox@31f80000 { 146d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 147d15d1cfbSSuman Anna reg = <0x00 0x31f80000 0x00 0x200>; 148d15d1cfbSSuman Anna #mbox-cells = <1>; 149d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 150d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 151d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 15274f0f58dSAndrew Davis status = "disabled"; 153d15d1cfbSSuman Anna }; 154d15d1cfbSSuman Anna 155d15d1cfbSSuman Anna mailbox0_cluster1: mailbox@31f81000 { 156d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 157d15d1cfbSSuman Anna reg = <0x00 0x31f81000 0x00 0x200>; 158d15d1cfbSSuman Anna #mbox-cells = <1>; 159d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 160d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 161d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 16274f0f58dSAndrew Davis status = "disabled"; 163d15d1cfbSSuman Anna }; 164d15d1cfbSSuman Anna 165d15d1cfbSSuman Anna mailbox0_cluster2: mailbox@31f82000 { 166d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 167d15d1cfbSSuman Anna reg = <0x00 0x31f82000 0x00 0x200>; 168d15d1cfbSSuman Anna #mbox-cells = <1>; 169d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 170d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 171d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 17274f0f58dSAndrew Davis status = "disabled"; 173d15d1cfbSSuman Anna }; 174d15d1cfbSSuman Anna 175d15d1cfbSSuman Anna mailbox0_cluster3: mailbox@31f83000 { 176d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 177d15d1cfbSSuman Anna reg = <0x00 0x31f83000 0x00 0x200>; 178d15d1cfbSSuman Anna #mbox-cells = <1>; 179d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 180d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 181d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 18274f0f58dSAndrew Davis status = "disabled"; 183d15d1cfbSSuman Anna }; 184d15d1cfbSSuman Anna 185d15d1cfbSSuman Anna mailbox0_cluster4: mailbox@31f84000 { 186d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 187d15d1cfbSSuman Anna reg = <0x00 0x31f84000 0x00 0x200>; 188d15d1cfbSSuman Anna #mbox-cells = <1>; 189d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 190d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 191d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 19274f0f58dSAndrew Davis status = "disabled"; 193d15d1cfbSSuman Anna }; 194d15d1cfbSSuman Anna 195d15d1cfbSSuman Anna mailbox0_cluster5: mailbox@31f85000 { 196d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 197d15d1cfbSSuman Anna reg = <0x00 0x31f85000 0x00 0x200>; 198d15d1cfbSSuman Anna #mbox-cells = <1>; 199d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 200d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 201d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 20274f0f58dSAndrew Davis status = "disabled"; 203d15d1cfbSSuman Anna }; 204d15d1cfbSSuman Anna 205d15d1cfbSSuman Anna mailbox0_cluster6: mailbox@31f86000 { 206d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 207d15d1cfbSSuman Anna reg = <0x00 0x31f86000 0x00 0x200>; 208d15d1cfbSSuman Anna #mbox-cells = <1>; 209d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 210d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 211d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 21274f0f58dSAndrew Davis status = "disabled"; 213d15d1cfbSSuman Anna }; 214d15d1cfbSSuman Anna 215d15d1cfbSSuman Anna mailbox0_cluster7: mailbox@31f87000 { 216d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 217d15d1cfbSSuman Anna reg = <0x00 0x31f87000 0x00 0x200>; 218d15d1cfbSSuman Anna #mbox-cells = <1>; 219d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 220d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 221d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 22274f0f58dSAndrew Davis status = "disabled"; 223d15d1cfbSSuman Anna }; 224d15d1cfbSSuman Anna 225d15d1cfbSSuman Anna mailbox0_cluster8: mailbox@31f88000 { 226d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 227d15d1cfbSSuman Anna reg = <0x00 0x31f88000 0x00 0x200>; 228d15d1cfbSSuman Anna #mbox-cells = <1>; 229d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 230d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 231d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 23274f0f58dSAndrew Davis status = "disabled"; 233d15d1cfbSSuman Anna }; 234d15d1cfbSSuman Anna 235d15d1cfbSSuman Anna mailbox0_cluster9: mailbox@31f89000 { 236d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 237d15d1cfbSSuman Anna reg = <0x00 0x31f89000 0x00 0x200>; 238d15d1cfbSSuman Anna #mbox-cells = <1>; 239d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 240d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 241d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 24274f0f58dSAndrew Davis status = "disabled"; 243d15d1cfbSSuman Anna }; 244d15d1cfbSSuman Anna 245d15d1cfbSSuman Anna mailbox0_cluster10: mailbox@31f8a000 { 246d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 247d15d1cfbSSuman Anna reg = <0x00 0x31f8a000 0x00 0x200>; 248d15d1cfbSSuman Anna #mbox-cells = <1>; 249d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 250d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 251d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 25274f0f58dSAndrew Davis status = "disabled"; 253d15d1cfbSSuman Anna }; 254d15d1cfbSSuman Anna 255d15d1cfbSSuman Anna mailbox0_cluster11: mailbox@31f8b000 { 256d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 257d15d1cfbSSuman Anna reg = <0x00 0x31f8b000 0x00 0x200>; 258d15d1cfbSSuman Anna #mbox-cells = <1>; 259d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 260d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 261d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 26274f0f58dSAndrew Davis status = "disabled"; 263d15d1cfbSSuman Anna }; 264d15d1cfbSSuman Anna 26546374264SPeter Ujfalusi main_ringacc: ringacc@3c000000 { 26646374264SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 26746374264SPeter Ujfalusi reg = <0x00 0x3c000000 0x00 0x400000>, 26846374264SPeter Ujfalusi <0x00 0x38000000 0x00 0x400000>, 26946374264SPeter Ujfalusi <0x00 0x31120000 0x00 0x100>, 270702110c2SVignesh Raghavendra <0x00 0x33000000 0x00 0x40000>, 271702110c2SVignesh Raghavendra <0x00 0x31080000 0x00 0x40000>; 272702110c2SVignesh Raghavendra reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 27346374264SPeter Ujfalusi ti,num-rings = <1024>; 27446374264SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 27546374264SPeter Ujfalusi ti,sci = <&dmsc>; 27646374264SPeter Ujfalusi ti,sci-dev-id = <211>; 27746374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 27846374264SPeter Ujfalusi }; 27946374264SPeter Ujfalusi 28046374264SPeter Ujfalusi main_udmap: dma-controller@31150000 { 28146374264SPeter Ujfalusi compatible = "ti,j721e-navss-main-udmap"; 28246374264SPeter Ujfalusi reg = <0x00 0x31150000 0x00 0x100>, 28346374264SPeter Ujfalusi <0x00 0x34000000 0x00 0x100000>, 2841b62a3cfSManorit Chawdhry <0x00 0x35000000 0x00 0x100000>, 2851b62a3cfSManorit Chawdhry <0x00 0x30b00000 0x00 0x4000>, 2861b62a3cfSManorit Chawdhry <0x00 0x30c00000 0x00 0x4000>, 2871b62a3cfSManorit Chawdhry <0x00 0x30d00000 0x00 0x4000>; 2881b62a3cfSManorit Chawdhry reg-names = "gcfg", "rchanrt", "tchanrt", 2891b62a3cfSManorit Chawdhry "tchan", "rchan", "rflow"; 29046374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 29146374264SPeter Ujfalusi #dma-cells = <1>; 29246374264SPeter Ujfalusi 29346374264SPeter Ujfalusi ti,sci = <&dmsc>; 29446374264SPeter Ujfalusi ti,sci-dev-id = <212>; 29546374264SPeter Ujfalusi ti,ringacc = <&main_ringacc>; 29646374264SPeter Ujfalusi 29746374264SPeter Ujfalusi ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 29846374264SPeter Ujfalusi <0x0f>, /* TX_HCHAN */ 29946374264SPeter Ujfalusi <0x10>; /* TX_UHCHAN */ 30046374264SPeter Ujfalusi ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 30146374264SPeter Ujfalusi <0x0b>, /* RX_HCHAN */ 30246374264SPeter Ujfalusi <0x0c>; /* RX_UHCHAN */ 30346374264SPeter Ujfalusi ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 30446374264SPeter Ujfalusi }; 305c5d73d8dSGrygorii Strashko 306c5d73d8dSGrygorii Strashko cpts@310d0000 { 307c5d73d8dSGrygorii Strashko compatible = "ti,j721e-cpts"; 308c5d73d8dSGrygorii Strashko reg = <0x00 0x310d0000 0x00 0x400>; 309c5d73d8dSGrygorii Strashko reg-names = "cpts"; 310c5d73d8dSGrygorii Strashko clocks = <&k3_clks 201 1>; 311c5d73d8dSGrygorii Strashko clock-names = "cpts"; 312c5d73d8dSGrygorii Strashko interrupts-extended = <&main_navss_intr 391>; 313c5d73d8dSGrygorii Strashko interrupt-names = "cpts"; 314c5d73d8dSGrygorii Strashko ti,cpts-periodic-outputs = <6>; 315c5d73d8dSGrygorii Strashko ti,cpts-ext-ts-inputs = <8>; 316c5d73d8dSGrygorii Strashko }; 317d361ed88SLokesh Vutla }; 318d361ed88SLokesh Vutla 319d3bac980SSiddharth Vadapalli cpsw0: ethernet@c000000 { 320d3bac980SSiddharth Vadapalli compatible = "ti,j7200-cpswxg-nuss"; 321d3bac980SSiddharth Vadapalli #address-cells = <2>; 322d3bac980SSiddharth Vadapalli #size-cells = <2>; 323d3bac980SSiddharth Vadapalli reg = <0x00 0xc000000 0x00 0x200000>; 324d3bac980SSiddharth Vadapalli reg-names = "cpsw_nuss"; 325d3bac980SSiddharth Vadapalli ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 326d3bac980SSiddharth Vadapalli clocks = <&k3_clks 19 33>; 327d3bac980SSiddharth Vadapalli clock-names = "fck"; 328d3bac980SSiddharth Vadapalli power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 329d3bac980SSiddharth Vadapalli 330d3bac980SSiddharth Vadapalli dmas = <&main_udmap 0xca00>, 331d3bac980SSiddharth Vadapalli <&main_udmap 0xca01>, 332d3bac980SSiddharth Vadapalli <&main_udmap 0xca02>, 333d3bac980SSiddharth Vadapalli <&main_udmap 0xca03>, 334d3bac980SSiddharth Vadapalli <&main_udmap 0xca04>, 335d3bac980SSiddharth Vadapalli <&main_udmap 0xca05>, 336d3bac980SSiddharth Vadapalli <&main_udmap 0xca06>, 337d3bac980SSiddharth Vadapalli <&main_udmap 0xca07>, 338d3bac980SSiddharth Vadapalli <&main_udmap 0x4a00>; 339d3bac980SSiddharth Vadapalli dma-names = "tx0", "tx1", "tx2", "tx3", 340d3bac980SSiddharth Vadapalli "tx4", "tx5", "tx6", "tx7", 341d3bac980SSiddharth Vadapalli "rx"; 342d3bac980SSiddharth Vadapalli 343d3bac980SSiddharth Vadapalli status = "disabled"; 344d3bac980SSiddharth Vadapalli 345d3bac980SSiddharth Vadapalli ethernet-ports { 346d3bac980SSiddharth Vadapalli #address-cells = <1>; 347d3bac980SSiddharth Vadapalli #size-cells = <0>; 348d3bac980SSiddharth Vadapalli cpsw0_port1: port@1 { 349d3bac980SSiddharth Vadapalli reg = <1>; 350d3bac980SSiddharth Vadapalli ti,mac-only; 351d3bac980SSiddharth Vadapalli label = "port1"; 352d3bac980SSiddharth Vadapalli status = "disabled"; 353d3bac980SSiddharth Vadapalli }; 354d3bac980SSiddharth Vadapalli 355d3bac980SSiddharth Vadapalli cpsw0_port2: port@2 { 356d3bac980SSiddharth Vadapalli reg = <2>; 357d3bac980SSiddharth Vadapalli ti,mac-only; 358d3bac980SSiddharth Vadapalli label = "port2"; 359d3bac980SSiddharth Vadapalli status = "disabled"; 360d3bac980SSiddharth Vadapalli }; 361d3bac980SSiddharth Vadapalli 362d3bac980SSiddharth Vadapalli cpsw0_port3: port@3 { 363d3bac980SSiddharth Vadapalli reg = <3>; 364d3bac980SSiddharth Vadapalli ti,mac-only; 365d3bac980SSiddharth Vadapalli label = "port3"; 366d3bac980SSiddharth Vadapalli status = "disabled"; 367d3bac980SSiddharth Vadapalli }; 368d3bac980SSiddharth Vadapalli 369d3bac980SSiddharth Vadapalli cpsw0_port4: port@4 { 370d3bac980SSiddharth Vadapalli reg = <4>; 371d3bac980SSiddharth Vadapalli ti,mac-only; 372d3bac980SSiddharth Vadapalli label = "port4"; 373d3bac980SSiddharth Vadapalli status = "disabled"; 374d3bac980SSiddharth Vadapalli }; 375d3bac980SSiddharth Vadapalli }; 376d3bac980SSiddharth Vadapalli 377d3bac980SSiddharth Vadapalli cpsw5g_mdio: mdio@f00 { 378d3bac980SSiddharth Vadapalli compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 379d3bac980SSiddharth Vadapalli reg = <0x00 0xf00 0x00 0x100>; 380d3bac980SSiddharth Vadapalli #address-cells = <1>; 381d3bac980SSiddharth Vadapalli #size-cells = <0>; 382d3bac980SSiddharth Vadapalli clocks = <&k3_clks 19 33>; 383d3bac980SSiddharth Vadapalli clock-names = "fck"; 384d3bac980SSiddharth Vadapalli bus_freq = <1000000>; 385d3bac980SSiddharth Vadapalli status = "disabled"; 386d3bac980SSiddharth Vadapalli }; 387d3bac980SSiddharth Vadapalli 388d3bac980SSiddharth Vadapalli cpts@3d000 { 389d3bac980SSiddharth Vadapalli compatible = "ti,j721e-cpts"; 390d3bac980SSiddharth Vadapalli reg = <0x00 0x3d000 0x00 0x400>; 391d3bac980SSiddharth Vadapalli clocks = <&k3_clks 19 16>; 392d3bac980SSiddharth Vadapalli clock-names = "cpts"; 393d3bac980SSiddharth Vadapalli interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 394d3bac980SSiddharth Vadapalli interrupt-names = "cpts"; 395d3bac980SSiddharth Vadapalli ti,cpts-ext-ts-inputs = <4>; 396d3bac980SSiddharth Vadapalli ti,cpts-periodic-outputs = <2>; 397d3bac980SSiddharth Vadapalli }; 398d3bac980SSiddharth Vadapalli }; 399d3bac980SSiddharth Vadapalli 40003612d38SUdit Kumar /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 40103612d38SUdit Kumar main_timerio_input: pinctrl@104200 { 4024eb42afeSThomas Richard compatible = "ti,j7200-padconf", "pinctrl-single"; 40303612d38SUdit Kumar reg = <0x0 0x104200 0x0 0x50>; 40403612d38SUdit Kumar #pinctrl-cells = <1>; 40503612d38SUdit Kumar pinctrl-single,register-width = <32>; 40603612d38SUdit Kumar pinctrl-single,function-mask = <0x000001ff>; 40703612d38SUdit Kumar }; 40803612d38SUdit Kumar 40903612d38SUdit Kumar /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 41003612d38SUdit Kumar main_timerio_output: pinctrl@104280 { 4114eb42afeSThomas Richard compatible = "ti,j7200-padconf", "pinctrl-single"; 41203612d38SUdit Kumar reg = <0x0 0x104280 0x0 0x20>; 41303612d38SUdit Kumar #pinctrl-cells = <1>; 41403612d38SUdit Kumar pinctrl-single,register-width = <32>; 41503612d38SUdit Kumar pinctrl-single,function-mask = <0x0000001f>; 41603612d38SUdit Kumar }; 41703612d38SUdit Kumar 418d361ed88SLokesh Vutla main_pmx0: pinctrl@11c000 { 4194eb42afeSThomas Richard compatible = "ti,j7200-padconf", "pinctrl-single"; 420d361ed88SLokesh Vutla /* Proxy 0 addressing */ 4210d0a0b44SMatt Ranostay reg = <0x00 0x11c000 0x00 0x10c>; 4220d0a0b44SMatt Ranostay #pinctrl-cells = <1>; 4230d0a0b44SMatt Ranostay pinctrl-single,register-width = <32>; 4240d0a0b44SMatt Ranostay pinctrl-single,function-mask = <0xffffffff>; 4250d0a0b44SMatt Ranostay }; 4260d0a0b44SMatt Ranostay 4270d0a0b44SMatt Ranostay main_pmx1: pinctrl@11c11c { 4284eb42afeSThomas Richard compatible = "ti,j7200-padconf", "pinctrl-single"; 4290d0a0b44SMatt Ranostay /* Proxy 0 addressing */ 4300d0a0b44SMatt Ranostay reg = <0x00 0x11c11c 0x00 0xc>; 431d361ed88SLokesh Vutla #pinctrl-cells = <1>; 432d361ed88SLokesh Vutla pinctrl-single,register-width = <32>; 433d361ed88SLokesh Vutla pinctrl-single,function-mask = <0xffffffff>; 434d361ed88SLokesh Vutla }; 435d361ed88SLokesh Vutla 436d361ed88SLokesh Vutla main_uart0: serial@2800000 { 437d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 438d361ed88SLokesh Vutla reg = <0x00 0x02800000 0x00 0x100>; 439d361ed88SLokesh Vutla interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 440d361ed88SLokesh Vutla clock-frequency = <48000000>; 441d361ed88SLokesh Vutla current-speed = <115200>; 442d361ed88SLokesh Vutla power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 443d361ed88SLokesh Vutla clocks = <&k3_clks 146 2>; 444d361ed88SLokesh Vutla clock-names = "fclk"; 445dae322f8SAndrew Davis status = "disabled"; 446d361ed88SLokesh Vutla }; 447d361ed88SLokesh Vutla 448d361ed88SLokesh Vutla main_uart1: serial@2810000 { 449d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 450d361ed88SLokesh Vutla reg = <0x00 0x02810000 0x00 0x100>; 451d361ed88SLokesh Vutla interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 452d361ed88SLokesh Vutla clock-frequency = <48000000>; 453d361ed88SLokesh Vutla current-speed = <115200>; 454d361ed88SLokesh Vutla power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 455d361ed88SLokesh Vutla clocks = <&k3_clks 278 2>; 456d361ed88SLokesh Vutla clock-names = "fclk"; 457dae322f8SAndrew Davis status = "disabled"; 458d361ed88SLokesh Vutla }; 459d361ed88SLokesh Vutla 460d361ed88SLokesh Vutla main_uart2: serial@2820000 { 461d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 462d361ed88SLokesh Vutla reg = <0x00 0x02820000 0x00 0x100>; 463d361ed88SLokesh Vutla interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 464d361ed88SLokesh Vutla clock-frequency = <48000000>; 465d361ed88SLokesh Vutla current-speed = <115200>; 466d361ed88SLokesh Vutla power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 467d361ed88SLokesh Vutla clocks = <&k3_clks 279 2>; 468d361ed88SLokesh Vutla clock-names = "fclk"; 469dae322f8SAndrew Davis status = "disabled"; 470d361ed88SLokesh Vutla }; 471d361ed88SLokesh Vutla 472d361ed88SLokesh Vutla main_uart3: serial@2830000 { 473d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 474d361ed88SLokesh Vutla reg = <0x00 0x02830000 0x00 0x100>; 475d361ed88SLokesh Vutla interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 476d361ed88SLokesh Vutla clock-frequency = <48000000>; 477d361ed88SLokesh Vutla current-speed = <115200>; 478d361ed88SLokesh Vutla power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 479d361ed88SLokesh Vutla clocks = <&k3_clks 280 2>; 480d361ed88SLokesh Vutla clock-names = "fclk"; 481dae322f8SAndrew Davis status = "disabled"; 482d361ed88SLokesh Vutla }; 483d361ed88SLokesh Vutla 484d361ed88SLokesh Vutla main_uart4: serial@2840000 { 485d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 486d361ed88SLokesh Vutla reg = <0x00 0x02840000 0x00 0x100>; 487d361ed88SLokesh Vutla interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 488d361ed88SLokesh Vutla clock-frequency = <48000000>; 489d361ed88SLokesh Vutla current-speed = <115200>; 490d361ed88SLokesh Vutla power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 491d361ed88SLokesh Vutla clocks = <&k3_clks 281 2>; 492d361ed88SLokesh Vutla clock-names = "fclk"; 493dae322f8SAndrew Davis status = "disabled"; 494d361ed88SLokesh Vutla }; 495d361ed88SLokesh Vutla 496d361ed88SLokesh Vutla main_uart5: serial@2850000 { 497d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 498d361ed88SLokesh Vutla reg = <0x00 0x02850000 0x00 0x100>; 499d361ed88SLokesh Vutla interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 500d361ed88SLokesh Vutla clock-frequency = <48000000>; 501d361ed88SLokesh Vutla current-speed = <115200>; 502d361ed88SLokesh Vutla power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 503d361ed88SLokesh Vutla clocks = <&k3_clks 282 2>; 504d361ed88SLokesh Vutla clock-names = "fclk"; 505dae322f8SAndrew Davis status = "disabled"; 506d361ed88SLokesh Vutla }; 507d361ed88SLokesh Vutla 508d361ed88SLokesh Vutla main_uart6: serial@2860000 { 509d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 510d361ed88SLokesh Vutla reg = <0x00 0x02860000 0x00 0x100>; 511d361ed88SLokesh Vutla interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 512d361ed88SLokesh Vutla clock-frequency = <48000000>; 513d361ed88SLokesh Vutla current-speed = <115200>; 514d361ed88SLokesh Vutla power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 515d361ed88SLokesh Vutla clocks = <&k3_clks 283 2>; 516d361ed88SLokesh Vutla clock-names = "fclk"; 517dae322f8SAndrew Davis status = "disabled"; 518d361ed88SLokesh Vutla }; 519d361ed88SLokesh Vutla 520d361ed88SLokesh Vutla main_uart7: serial@2870000 { 521d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 522d361ed88SLokesh Vutla reg = <0x00 0x02870000 0x00 0x100>; 523d361ed88SLokesh Vutla interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 524d361ed88SLokesh Vutla clock-frequency = <48000000>; 525d361ed88SLokesh Vutla current-speed = <115200>; 526d361ed88SLokesh Vutla power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 527d361ed88SLokesh Vutla clocks = <&k3_clks 284 2>; 528d361ed88SLokesh Vutla clock-names = "fclk"; 529dae322f8SAndrew Davis status = "disabled"; 530d361ed88SLokesh Vutla }; 531d361ed88SLokesh Vutla 532d361ed88SLokesh Vutla main_uart8: serial@2880000 { 533d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 534d361ed88SLokesh Vutla reg = <0x00 0x02880000 0x00 0x100>; 535d361ed88SLokesh Vutla interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 536d361ed88SLokesh Vutla clock-frequency = <48000000>; 537d361ed88SLokesh Vutla current-speed = <115200>; 538d361ed88SLokesh Vutla power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 539d361ed88SLokesh Vutla clocks = <&k3_clks 285 2>; 540d361ed88SLokesh Vutla clock-names = "fclk"; 541dae322f8SAndrew Davis status = "disabled"; 542d361ed88SLokesh Vutla }; 543d361ed88SLokesh Vutla 544d361ed88SLokesh Vutla main_uart9: serial@2890000 { 545d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 546d361ed88SLokesh Vutla reg = <0x00 0x02890000 0x00 0x100>; 547d361ed88SLokesh Vutla interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 548d361ed88SLokesh Vutla clock-frequency = <48000000>; 549d361ed88SLokesh Vutla current-speed = <115200>; 550d361ed88SLokesh Vutla power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 551d361ed88SLokesh Vutla clocks = <&k3_clks 286 2>; 552d361ed88SLokesh Vutla clock-names = "fclk"; 553dae322f8SAndrew Davis status = "disabled"; 554d361ed88SLokesh Vutla }; 55503bfeb52SVignesh Raghavendra 55603bfeb52SVignesh Raghavendra main_i2c0: i2c@2000000 { 55703bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 55803bfeb52SVignesh Raghavendra reg = <0x00 0x2000000 0x00 0x100>; 55903bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 56003bfeb52SVignesh Raghavendra #address-cells = <1>; 56103bfeb52SVignesh Raghavendra #size-cells = <0>; 56203bfeb52SVignesh Raghavendra clock-names = "fck"; 56303bfeb52SVignesh Raghavendra clocks = <&k3_clks 187 1>; 56403bfeb52SVignesh Raghavendra power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 565a9ed915cSAndrew Davis status = "disabled"; 56603bfeb52SVignesh Raghavendra }; 56703bfeb52SVignesh Raghavendra 56803bfeb52SVignesh Raghavendra main_i2c1: i2c@2010000 { 56903bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 57003bfeb52SVignesh Raghavendra reg = <0x00 0x2010000 0x00 0x100>; 57103bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 57203bfeb52SVignesh Raghavendra #address-cells = <1>; 57303bfeb52SVignesh Raghavendra #size-cells = <0>; 57403bfeb52SVignesh Raghavendra clock-names = "fck"; 57503bfeb52SVignesh Raghavendra clocks = <&k3_clks 188 1>; 57603bfeb52SVignesh Raghavendra power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 577a9ed915cSAndrew Davis status = "disabled"; 57803bfeb52SVignesh Raghavendra }; 57903bfeb52SVignesh Raghavendra 58003bfeb52SVignesh Raghavendra main_i2c2: i2c@2020000 { 58103bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 58203bfeb52SVignesh Raghavendra reg = <0x00 0x2020000 0x00 0x100>; 58303bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 58403bfeb52SVignesh Raghavendra #address-cells = <1>; 58503bfeb52SVignesh Raghavendra #size-cells = <0>; 58603bfeb52SVignesh Raghavendra clock-names = "fck"; 58703bfeb52SVignesh Raghavendra clocks = <&k3_clks 189 1>; 58803bfeb52SVignesh Raghavendra power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 589a9ed915cSAndrew Davis status = "disabled"; 59003bfeb52SVignesh Raghavendra }; 59103bfeb52SVignesh Raghavendra 59203bfeb52SVignesh Raghavendra main_i2c3: i2c@2030000 { 59303bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 59403bfeb52SVignesh Raghavendra reg = <0x00 0x2030000 0x00 0x100>; 59503bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 59603bfeb52SVignesh Raghavendra #address-cells = <1>; 59703bfeb52SVignesh Raghavendra #size-cells = <0>; 59803bfeb52SVignesh Raghavendra clock-names = "fck"; 59903bfeb52SVignesh Raghavendra clocks = <&k3_clks 190 1>; 60003bfeb52SVignesh Raghavendra power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 601a9ed915cSAndrew Davis status = "disabled"; 60203bfeb52SVignesh Raghavendra }; 60303bfeb52SVignesh Raghavendra 60403bfeb52SVignesh Raghavendra main_i2c4: i2c@2040000 { 60503bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 60603bfeb52SVignesh Raghavendra reg = <0x00 0x2040000 0x00 0x100>; 60703bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 60803bfeb52SVignesh Raghavendra #address-cells = <1>; 60903bfeb52SVignesh Raghavendra #size-cells = <0>; 61003bfeb52SVignesh Raghavendra clock-names = "fck"; 61103bfeb52SVignesh Raghavendra clocks = <&k3_clks 191 1>; 61203bfeb52SVignesh Raghavendra power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 613a9ed915cSAndrew Davis status = "disabled"; 61403bfeb52SVignesh Raghavendra }; 61503bfeb52SVignesh Raghavendra 61603bfeb52SVignesh Raghavendra main_i2c5: i2c@2050000 { 61703bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 61803bfeb52SVignesh Raghavendra reg = <0x00 0x2050000 0x00 0x100>; 61903bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 62003bfeb52SVignesh Raghavendra #address-cells = <1>; 62103bfeb52SVignesh Raghavendra #size-cells = <0>; 62203bfeb52SVignesh Raghavendra clock-names = "fck"; 62303bfeb52SVignesh Raghavendra clocks = <&k3_clks 192 1>; 62403bfeb52SVignesh Raghavendra power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 625a9ed915cSAndrew Davis status = "disabled"; 62603bfeb52SVignesh Raghavendra }; 62703bfeb52SVignesh Raghavendra 62803bfeb52SVignesh Raghavendra main_i2c6: i2c@2060000 { 62903bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 63003bfeb52SVignesh Raghavendra reg = <0x00 0x2060000 0x00 0x100>; 63103bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 63203bfeb52SVignesh Raghavendra #address-cells = <1>; 63303bfeb52SVignesh Raghavendra #size-cells = <0>; 63403bfeb52SVignesh Raghavendra clock-names = "fck"; 63503bfeb52SVignesh Raghavendra clocks = <&k3_clks 193 1>; 63603bfeb52SVignesh Raghavendra power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 637a9ed915cSAndrew Davis status = "disabled"; 63803bfeb52SVignesh Raghavendra }; 6397cd03dc7SFaiz Abbas 6407cd03dc7SFaiz Abbas main_sdhci0: mmc@4f80000 { 6417cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 6427cd03dc7SFaiz Abbas reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 6437cd03dc7SFaiz Abbas interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 6447cd03dc7SFaiz Abbas power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 6450cf73209SGrygorii Strashko clock-names = "clk_ahb", "clk_xin"; 6460cf73209SGrygorii Strashko clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 6477cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 6487cd03dc7SFaiz Abbas ti,otap-del-sel-mmc-hs = <0x0>; 6497cd03dc7SFaiz Abbas ti,otap-del-sel-ddr52 = <0x6>; 6507cd03dc7SFaiz Abbas ti,otap-del-sel-hs200 = <0x8>; 65194374990SAswath Govindraju ti,otap-del-sel-hs400 = <0x5>; 65294374990SAswath Govindraju ti,itap-del-sel-legacy = <0x10>; 65394374990SAswath Govindraju ti,itap-del-sel-mmc-hs = <0xa>; 65490899956SBhavya Kapoor ti,itap-del-sel-ddr52 = <0x3>; 6557cd03dc7SFaiz Abbas ti,strobe-sel = <0x77>; 65694374990SAswath Govindraju ti,clkbuf-sel = <0x7>; 6577cd03dc7SFaiz Abbas ti,trm-icp = <0x8>; 6587cd03dc7SFaiz Abbas bus-width = <8>; 6597cd03dc7SFaiz Abbas mmc-ddr-1_8v; 66094374990SAswath Govindraju mmc-hs200-1_8v; 66194374990SAswath Govindraju mmc-hs400-1_8v; 6627cd03dc7SFaiz Abbas dma-coherent; 663013b7dd3SAndrew Davis status = "disabled"; 6647cd03dc7SFaiz Abbas }; 6657cd03dc7SFaiz Abbas 6667cd03dc7SFaiz Abbas main_sdhci1: mmc@4fb0000 { 6677cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 6687cd03dc7SFaiz Abbas reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 6697cd03dc7SFaiz Abbas interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 6707cd03dc7SFaiz Abbas power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 6710cf73209SGrygorii Strashko clock-names = "clk_ahb", "clk_xin"; 6720cf73209SGrygorii Strashko clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 6737cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 6747cd03dc7SFaiz Abbas ti,otap-del-sel-sd-hs = <0x0>; 6757cd03dc7SFaiz Abbas ti,otap-del-sel-sdr12 = <0xf>; 6767cd03dc7SFaiz Abbas ti,otap-del-sel-sdr25 = <0xf>; 6777cd03dc7SFaiz Abbas ti,otap-del-sel-sdr50 = <0xc>; 6787cd03dc7SFaiz Abbas ti,otap-del-sel-sdr104 = <0x5>; 6797cd03dc7SFaiz Abbas ti,otap-del-sel-ddr50 = <0xc>; 68094374990SAswath Govindraju ti,itap-del-sel-legacy = <0x0>; 68194374990SAswath Govindraju ti,itap-del-sel-sd-hs = <0x0>; 68294374990SAswath Govindraju ti,itap-del-sel-sdr12 = <0x0>; 68394374990SAswath Govindraju ti,itap-del-sel-sdr25 = <0x0>; 68494374990SAswath Govindraju ti,clkbuf-sel = <0x7>; 68594374990SAswath Govindraju ti,trm-icp = <0x8>; 6867cd03dc7SFaiz Abbas dma-coherent; 687013b7dd3SAndrew Davis status = "disabled"; 6887cd03dc7SFaiz Abbas }; 6896197d713SRoger Quadros 6904c1b22a9SKishon Vijay Abraham I serdes_wiz0: wiz@5060000 { 6914c1b22a9SKishon Vijay Abraham I compatible = "ti,j721e-wiz-10g"; 6924c1b22a9SKishon Vijay Abraham I #address-cells = <1>; 6934c1b22a9SKishon Vijay Abraham I #size-cells = <1>; 6944c1b22a9SKishon Vijay Abraham I power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 6954c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 6964c1b22a9SKishon Vijay Abraham I clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 6974c1b22a9SKishon Vijay Abraham I num-lanes = <4>; 6984c1b22a9SKishon Vijay Abraham I #reset-cells = <1>; 6994c1b22a9SKishon Vijay Abraham I ranges = <0x5060000 0x0 0x5060000 0x10000>; 7004c1b22a9SKishon Vijay Abraham I 7014c1b22a9SKishon Vijay Abraham I assigned-clocks = <&k3_clks 292 85>; 7024c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 89>; 7034c1b22a9SKishon Vijay Abraham I 7044c1b22a9SKishon Vijay Abraham I wiz0_pll0_refclk: pll0-refclk { 7054c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 7064c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_pll0_refclk"; 7074c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 7084c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_pll0_refclk>; 7094c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 7104c1b22a9SKishon Vijay Abraham I }; 7114c1b22a9SKishon Vijay Abraham I 7124c1b22a9SKishon Vijay Abraham I wiz0_pll1_refclk: pll1-refclk { 7134c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 7144c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_pll1_refclk"; 7154c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 7164c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_pll1_refclk>; 7174c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 7184c1b22a9SKishon Vijay Abraham I }; 7194c1b22a9SKishon Vijay Abraham I 7204c1b22a9SKishon Vijay Abraham I wiz0_refclk_dig: refclk-dig { 7214c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 7224c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_refclk_dig"; 7234c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 7244c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_refclk_dig>; 7254c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 7264c1b22a9SKishon Vijay Abraham I }; 7274c1b22a9SKishon Vijay Abraham I 7284c1b22a9SKishon Vijay Abraham I wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 7294c1b22a9SKishon Vijay Abraham I clocks = <&wiz0_refclk_dig>; 7304c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 7314c1b22a9SKishon Vijay Abraham I }; 7324c1b22a9SKishon Vijay Abraham I 7334c1b22a9SKishon Vijay Abraham I serdes0: serdes@5060000 { 7344c1b22a9SKishon Vijay Abraham I compatible = "ti,j721e-serdes-10g"; 7354c1b22a9SKishon Vijay Abraham I reg = <0x05060000 0x00010000>; 7364c1b22a9SKishon Vijay Abraham I reg-names = "torrent_phy"; 7374c1b22a9SKishon Vijay Abraham I resets = <&serdes_wiz0 0>; 7384c1b22a9SKishon Vijay Abraham I reset-names = "torrent_reset"; 7394c1b22a9SKishon Vijay Abraham I clocks = <&wiz0_pll0_refclk>; 7404c1b22a9SKishon Vijay Abraham I clock-names = "refclk"; 7414c1b22a9SKishon Vijay Abraham I #address-cells = <1>; 7424c1b22a9SKishon Vijay Abraham I #size-cells = <0>; 7434c1b22a9SKishon Vijay Abraham I }; 7444c1b22a9SKishon Vijay Abraham I }; 7454c1b22a9SKishon Vijay Abraham I 7463276d9f5SKishon Vijay Abraham I pcie1_rc: pcie@2910000 { 7473276d9f5SKishon Vijay Abraham I compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 7483276d9f5SKishon Vijay Abraham I reg = <0x00 0x02910000 0x00 0x1000>, 7493276d9f5SKishon Vijay Abraham I <0x00 0x02917000 0x00 0x400>, 7503276d9f5SKishon Vijay Abraham I <0x00 0x0d800000 0x00 0x00800000>, 7513276d9f5SKishon Vijay Abraham I <0x00 0x18000000 0x00 0x00001000>; 7523276d9f5SKishon Vijay Abraham I reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 7533276d9f5SKishon Vijay Abraham I interrupt-names = "link_state"; 7543276d9f5SKishon Vijay Abraham I interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 7553276d9f5SKishon Vijay Abraham I device_type = "pci"; 7563276d9f5SKishon Vijay Abraham I ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 7573276d9f5SKishon Vijay Abraham I max-link-speed = <3>; 7583276d9f5SKishon Vijay Abraham I num-lanes = <4>; 7593276d9f5SKishon Vijay Abraham I power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 7603276d9f5SKishon Vijay Abraham I clocks = <&k3_clks 240 6>; 7613276d9f5SKishon Vijay Abraham I clock-names = "fck"; 7623276d9f5SKishon Vijay Abraham I #address-cells = <3>; 7633276d9f5SKishon Vijay Abraham I #size-cells = <2>; 7648bb84292SKishon Vijay Abraham I bus-range = <0x0 0xff>; 7653276d9f5SKishon Vijay Abraham I cdns,no-bar-match-nbits = <64>; 7660d553792SKishon Vijay Abraham I vendor-id = <0x104c>; 7670d553792SKishon Vijay Abraham I device-id = <0xb00f>; 7683276d9f5SKishon Vijay Abraham I msi-map = <0x0 &gic_its 0x0 0x10000>; 7693276d9f5SKishon Vijay Abraham I dma-coherent; 7703276d9f5SKishon Vijay Abraham I ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 7713276d9f5SKishon Vijay Abraham I <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 7723276d9f5SKishon Vijay Abraham I dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 7731b63a1b4SAndrew Davis status = "disabled"; 7743276d9f5SKishon Vijay Abraham I }; 7753276d9f5SKishon Vijay Abraham I 7766197d713SRoger Quadros usbss0: cdns-usb@4104000 { 7776197d713SRoger Quadros compatible = "ti,j721e-usb"; 7786197d713SRoger Quadros reg = <0x00 0x4104000 0x00 0x100>; 7796197d713SRoger Quadros dma-coherent; 7806197d713SRoger Quadros power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 7816197d713SRoger Quadros clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 7826197d713SRoger Quadros clock-names = "ref", "lpm"; 7836197d713SRoger Quadros assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 7846197d713SRoger Quadros assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 7856197d713SRoger Quadros #address-cells = <2>; 7866197d713SRoger Quadros #size-cells = <2>; 7876197d713SRoger Quadros ranges; 7886197d713SRoger Quadros 7896197d713SRoger Quadros usb0: usb@6000000 { 7906197d713SRoger Quadros compatible = "cdns,usb3"; 7916197d713SRoger Quadros reg = <0x00 0x6000000 0x00 0x10000>, 7926197d713SRoger Quadros <0x00 0x6010000 0x00 0x10000>, 7936197d713SRoger Quadros <0x00 0x6020000 0x00 0x10000>; 7946197d713SRoger Quadros reg-names = "otg", "xhci", "dev"; 7956197d713SRoger Quadros interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 7966197d713SRoger Quadros <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 7976197d713SRoger Quadros <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 7986197d713SRoger Quadros interrupt-names = "host", 7996197d713SRoger Quadros "peripheral", 8006197d713SRoger Quadros "otg"; 8016197d713SRoger Quadros maximum-speed = "super-speed"; 8026197d713SRoger Quadros dr_mode = "otg"; 803a2894d85SRoger Quadros cdns,phyrst-a-enable; 8046197d713SRoger Quadros }; 8056197d713SRoger Quadros }; 806eb6f3655SSuman Anna 807e0b2e6afSFaiz Abbas main_gpio0: gpio@600000 { 808e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 809e0b2e6afSFaiz Abbas reg = <0x00 0x00600000 0x00 0x100>; 810e0b2e6afSFaiz Abbas gpio-controller; 811e0b2e6afSFaiz Abbas #gpio-cells = <2>; 812e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 813e0b2e6afSFaiz Abbas interrupts = <145>, <146>, <147>, <148>, 814e0b2e6afSFaiz Abbas <149>; 815e0b2e6afSFaiz Abbas interrupt-controller; 816e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 817e0b2e6afSFaiz Abbas ti,ngpio = <69>; 818e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 819e0b2e6afSFaiz Abbas power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 820e0b2e6afSFaiz Abbas clocks = <&k3_clks 105 0>; 821e0b2e6afSFaiz Abbas clock-names = "gpio"; 822d9fe476dSAndrew Davis status = "disabled"; 823e0b2e6afSFaiz Abbas }; 824e0b2e6afSFaiz Abbas 825e0b2e6afSFaiz Abbas main_gpio2: gpio@610000 { 826e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 827e0b2e6afSFaiz Abbas reg = <0x00 0x00610000 0x00 0x100>; 828e0b2e6afSFaiz Abbas gpio-controller; 829e0b2e6afSFaiz Abbas #gpio-cells = <2>; 830e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 831e0b2e6afSFaiz Abbas interrupts = <154>, <155>, <156>, <157>, 832e0b2e6afSFaiz Abbas <158>; 833e0b2e6afSFaiz Abbas interrupt-controller; 834e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 835e0b2e6afSFaiz Abbas ti,ngpio = <69>; 836e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 837e0b2e6afSFaiz Abbas power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 838e0b2e6afSFaiz Abbas clocks = <&k3_clks 107 0>; 839e0b2e6afSFaiz Abbas clock-names = "gpio"; 840d9fe476dSAndrew Davis status = "disabled"; 841e0b2e6afSFaiz Abbas }; 842e0b2e6afSFaiz Abbas 843e0b2e6afSFaiz Abbas main_gpio4: gpio@620000 { 844e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 845e0b2e6afSFaiz Abbas reg = <0x00 0x00620000 0x00 0x100>; 846e0b2e6afSFaiz Abbas gpio-controller; 847e0b2e6afSFaiz Abbas #gpio-cells = <2>; 848e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 849e0b2e6afSFaiz Abbas interrupts = <163>, <164>, <165>, <166>, 850e0b2e6afSFaiz Abbas <167>; 851e0b2e6afSFaiz Abbas interrupt-controller; 852e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 853e0b2e6afSFaiz Abbas ti,ngpio = <69>; 854e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 855e0b2e6afSFaiz Abbas power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 856e0b2e6afSFaiz Abbas clocks = <&k3_clks 109 0>; 857e0b2e6afSFaiz Abbas clock-names = "gpio"; 858d9fe476dSAndrew Davis status = "disabled"; 859e0b2e6afSFaiz Abbas }; 860e0b2e6afSFaiz Abbas 861e0b2e6afSFaiz Abbas main_gpio6: gpio@630000 { 862e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 863e0b2e6afSFaiz Abbas reg = <0x00 0x00630000 0x00 0x100>; 864e0b2e6afSFaiz Abbas gpio-controller; 865e0b2e6afSFaiz Abbas #gpio-cells = <2>; 866e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 867e0b2e6afSFaiz Abbas interrupts = <172>, <173>, <174>, <175>, 868e0b2e6afSFaiz Abbas <176>; 869e0b2e6afSFaiz Abbas interrupt-controller; 870e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 871e0b2e6afSFaiz Abbas ti,ngpio = <69>; 872e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 873e0b2e6afSFaiz Abbas power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 874e0b2e6afSFaiz Abbas clocks = <&k3_clks 111 0>; 875e0b2e6afSFaiz Abbas clock-names = "gpio"; 876d9fe476dSAndrew Davis status = "disabled"; 877e0b2e6afSFaiz Abbas }; 878e0b2e6afSFaiz Abbas 87903b94719SBhavya Kapoor main_mcan0: can@2701000 { 88003b94719SBhavya Kapoor compatible = "bosch,m_can"; 88103b94719SBhavya Kapoor reg = <0x00 0x02701000 0x00 0x200>, 88203b94719SBhavya Kapoor <0x00 0x02708000 0x00 0x8000>; 88303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 88403b94719SBhavya Kapoor power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 88503b94719SBhavya Kapoor clocks = <&k3_clks 156 0>, <&k3_clks 156 2>; 88603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 88703b94719SBhavya Kapoor interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 88803b94719SBhavya Kapoor <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 88903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 89003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 89103b94719SBhavya Kapoor status = "disabled"; 89203b94719SBhavya Kapoor }; 89303b94719SBhavya Kapoor 89403b94719SBhavya Kapoor main_mcan1: can@2711000 { 89503b94719SBhavya Kapoor compatible = "bosch,m_can"; 89603b94719SBhavya Kapoor reg = <0x00 0x02711000 0x00 0x200>, 89703b94719SBhavya Kapoor <0x00 0x02718000 0x00 0x8000>; 89803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 89903b94719SBhavya Kapoor power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 90003b94719SBhavya Kapoor clocks = <&k3_clks 158 0>, <&k3_clks 158 2>; 90103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 90203b94719SBhavya Kapoor interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 90303b94719SBhavya Kapoor <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 90403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 90503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 90603b94719SBhavya Kapoor status = "disabled"; 90703b94719SBhavya Kapoor }; 90803b94719SBhavya Kapoor 90903b94719SBhavya Kapoor main_mcan2: can@2721000 { 91003b94719SBhavya Kapoor compatible = "bosch,m_can"; 91103b94719SBhavya Kapoor reg = <0x00 0x02721000 0x00 0x200>, 91203b94719SBhavya Kapoor <0x00 0x02728000 0x00 0x8000>; 91303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 91403b94719SBhavya Kapoor power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 91503b94719SBhavya Kapoor clocks = <&k3_clks 160 0>, <&k3_clks 160 2>; 91603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 91703b94719SBhavya Kapoor interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 91803b94719SBhavya Kapoor <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 91903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 92003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 92103b94719SBhavya Kapoor status = "disabled"; 92203b94719SBhavya Kapoor }; 92303b94719SBhavya Kapoor 92403b94719SBhavya Kapoor main_mcan3: can@2731000 { 92503b94719SBhavya Kapoor compatible = "bosch,m_can"; 92603b94719SBhavya Kapoor reg = <0x00 0x02731000 0x00 0x200>, 92703b94719SBhavya Kapoor <0x00 0x02738000 0x00 0x8000>; 92803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 92903b94719SBhavya Kapoor power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 93003b94719SBhavya Kapoor clocks = <&k3_clks 161 0>, <&k3_clks 161 2>; 93103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 93203b94719SBhavya Kapoor interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 93303b94719SBhavya Kapoor <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 93403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 93503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 93603b94719SBhavya Kapoor status = "disabled"; 93703b94719SBhavya Kapoor }; 93803b94719SBhavya Kapoor 93903b94719SBhavya Kapoor main_mcan4: can@2741000 { 94003b94719SBhavya Kapoor compatible = "bosch,m_can"; 94103b94719SBhavya Kapoor reg = <0x00 0x02741000 0x00 0x200>, 94203b94719SBhavya Kapoor <0x00 0x02748000 0x00 0x8000>; 94303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 94403b94719SBhavya Kapoor power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 94503b94719SBhavya Kapoor clocks = <&k3_clks 162 0>, <&k3_clks 162 2>; 94603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 94703b94719SBhavya Kapoor interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 94803b94719SBhavya Kapoor <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 94903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 95003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 95103b94719SBhavya Kapoor status = "disabled"; 95203b94719SBhavya Kapoor }; 95303b94719SBhavya Kapoor 95403b94719SBhavya Kapoor main_mcan5: can@2751000 { 95503b94719SBhavya Kapoor compatible = "bosch,m_can"; 95603b94719SBhavya Kapoor reg = <0x00 0x02751000 0x00 0x200>, 95703b94719SBhavya Kapoor <0x00 0x02758000 0x00 0x8000>; 95803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 95903b94719SBhavya Kapoor power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 96003b94719SBhavya Kapoor clocks = <&k3_clks 163 0>, <&k3_clks 163 2>; 96103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 96203b94719SBhavya Kapoor interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 96303b94719SBhavya Kapoor <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 96403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 96503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 96603b94719SBhavya Kapoor status = "disabled"; 96703b94719SBhavya Kapoor }; 96803b94719SBhavya Kapoor 96903b94719SBhavya Kapoor main_mcan6: can@2761000 { 97003b94719SBhavya Kapoor compatible = "bosch,m_can"; 97103b94719SBhavya Kapoor reg = <0x00 0x02761000 0x00 0x200>, 97203b94719SBhavya Kapoor <0x00 0x02768000 0x00 0x8000>; 97303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 97403b94719SBhavya Kapoor power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 97503b94719SBhavya Kapoor clocks = <&k3_clks 164 0>, <&k3_clks 164 2>; 97603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 97703b94719SBhavya Kapoor interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 97803b94719SBhavya Kapoor <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 97903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 98003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 98103b94719SBhavya Kapoor status = "disabled"; 98203b94719SBhavya Kapoor }; 98303b94719SBhavya Kapoor 98403b94719SBhavya Kapoor main_mcan7: can@2771000 { 98503b94719SBhavya Kapoor compatible = "bosch,m_can"; 98603b94719SBhavya Kapoor reg = <0x00 0x02771000 0x00 0x200>, 98703b94719SBhavya Kapoor <0x00 0x02778000 0x00 0x8000>; 98803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 98903b94719SBhavya Kapoor power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 99003b94719SBhavya Kapoor clocks = <&k3_clks 165 0>, <&k3_clks 165 2>; 99103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 99203b94719SBhavya Kapoor interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 99303b94719SBhavya Kapoor <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 99403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 99503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 99603b94719SBhavya Kapoor status = "disabled"; 99703b94719SBhavya Kapoor }; 99803b94719SBhavya Kapoor 99903b94719SBhavya Kapoor main_mcan8: can@2781000 { 100003b94719SBhavya Kapoor compatible = "bosch,m_can"; 100103b94719SBhavya Kapoor reg = <0x00 0x02781000 0x00 0x200>, 100203b94719SBhavya Kapoor <0x00 0x02788000 0x00 0x8000>; 100303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 100403b94719SBhavya Kapoor power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 100503b94719SBhavya Kapoor clocks = <&k3_clks 166 0>, <&k3_clks 166 2>; 100603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 100703b94719SBhavya Kapoor interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 100803b94719SBhavya Kapoor <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 100903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 101003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 101103b94719SBhavya Kapoor status = "disabled"; 101203b94719SBhavya Kapoor }; 101303b94719SBhavya Kapoor 101403b94719SBhavya Kapoor main_mcan9: can@2791000 { 101503b94719SBhavya Kapoor compatible = "bosch,m_can"; 101603b94719SBhavya Kapoor reg = <0x00 0x02791000 0x00 0x200>, 101703b94719SBhavya Kapoor <0x00 0x02798000 0x00 0x8000>; 101803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 101903b94719SBhavya Kapoor power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 102003b94719SBhavya Kapoor clocks = <&k3_clks 167 0>, <&k3_clks 167 2>; 102103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 102203b94719SBhavya Kapoor interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 102303b94719SBhavya Kapoor <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 102403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 102503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 102603b94719SBhavya Kapoor status = "disabled"; 102703b94719SBhavya Kapoor }; 102803b94719SBhavya Kapoor 102903b94719SBhavya Kapoor main_mcan10: can@27a1000 { 103003b94719SBhavya Kapoor compatible = "bosch,m_can"; 103103b94719SBhavya Kapoor reg = <0x00 0x027a1000 0x00 0x200>, 103203b94719SBhavya Kapoor <0x00 0x027a8000 0x00 0x8000>; 103303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 103403b94719SBhavya Kapoor power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 103503b94719SBhavya Kapoor clocks = <&k3_clks 168 0>, <&k3_clks 168 2>; 103603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 103703b94719SBhavya Kapoor interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 103803b94719SBhavya Kapoor <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 103903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 104003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 104103b94719SBhavya Kapoor status = "disabled"; 104203b94719SBhavya Kapoor }; 104303b94719SBhavya Kapoor 104403b94719SBhavya Kapoor main_mcan11: can@27b1000 { 104503b94719SBhavya Kapoor compatible = "bosch,m_can"; 104603b94719SBhavya Kapoor reg = <0x00 0x027b1000 0x00 0x200>, 104703b94719SBhavya Kapoor <0x00 0x027b8000 0x00 0x8000>; 104803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 104903b94719SBhavya Kapoor power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 105003b94719SBhavya Kapoor clocks = <&k3_clks 169 0>, <&k3_clks 169 2>; 105103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 105203b94719SBhavya Kapoor interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 105303b94719SBhavya Kapoor <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 105403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 105503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 105603b94719SBhavya Kapoor status = "disabled"; 105703b94719SBhavya Kapoor }; 105803b94719SBhavya Kapoor 105903b94719SBhavya Kapoor main_mcan12: can@27c1000 { 106003b94719SBhavya Kapoor compatible = "bosch,m_can"; 106103b94719SBhavya Kapoor reg = <0x00 0x027c1000 0x00 0x200>, 106203b94719SBhavya Kapoor <0x00 0x027c8000 0x00 0x8000>; 106303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 106403b94719SBhavya Kapoor power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 106503b94719SBhavya Kapoor clocks = <&k3_clks 170 0>, <&k3_clks 170 2>; 106603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 106703b94719SBhavya Kapoor interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 106803b94719SBhavya Kapoor <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 106903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 107003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 107103b94719SBhavya Kapoor status = "disabled"; 107203b94719SBhavya Kapoor }; 107303b94719SBhavya Kapoor 107403b94719SBhavya Kapoor main_mcan13: can@27d1000 { 107503b94719SBhavya Kapoor compatible = "bosch,m_can"; 107603b94719SBhavya Kapoor reg = <0x00 0x027d1000 0x00 0x200>, 107703b94719SBhavya Kapoor <0x00 0x027d8000 0x00 0x8000>; 107803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 107903b94719SBhavya Kapoor power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 108003b94719SBhavya Kapoor clocks = <&k3_clks 171 0>, <&k3_clks 171 2>; 108103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 108203b94719SBhavya Kapoor interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 108303b94719SBhavya Kapoor <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 108403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 108503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 108603b94719SBhavya Kapoor status = "disabled"; 108703b94719SBhavya Kapoor }; 108803b94719SBhavya Kapoor 108903b94719SBhavya Kapoor main_mcan14: can@2681000 { 109003b94719SBhavya Kapoor compatible = "bosch,m_can"; 109103b94719SBhavya Kapoor reg = <0x00 0x02681000 0x00 0x200>, 109203b94719SBhavya Kapoor <0x00 0x02688000 0x00 0x8000>; 109303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 109403b94719SBhavya Kapoor power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; 109503b94719SBhavya Kapoor clocks = <&k3_clks 150 0>, <&k3_clks 150 2>; 109603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 109703b94719SBhavya Kapoor interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 109803b94719SBhavya Kapoor <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 109903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 110003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 110103b94719SBhavya Kapoor status = "disabled"; 110203b94719SBhavya Kapoor }; 110303b94719SBhavya Kapoor 110403b94719SBhavya Kapoor main_mcan15: can@2691000 { 110503b94719SBhavya Kapoor compatible = "bosch,m_can"; 110603b94719SBhavya Kapoor reg = <0x00 0x02691000 0x00 0x200>, 110703b94719SBhavya Kapoor <0x00 0x02698000 0x00 0x8000>; 110803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 110903b94719SBhavya Kapoor power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 111003b94719SBhavya Kapoor clocks = <&k3_clks 151 0>, <&k3_clks 151 2>; 111103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 111203b94719SBhavya Kapoor interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 111303b94719SBhavya Kapoor <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 111403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 111503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 111603b94719SBhavya Kapoor status = "disabled"; 111703b94719SBhavya Kapoor }; 111803b94719SBhavya Kapoor 111903b94719SBhavya Kapoor main_mcan16: can@26a1000 { 112003b94719SBhavya Kapoor compatible = "bosch,m_can"; 112103b94719SBhavya Kapoor reg = <0x00 0x026a1000 0x00 0x200>, 112203b94719SBhavya Kapoor <0x00 0x026a8000 0x00 0x8000>; 112303b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 112403b94719SBhavya Kapoor power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 112503b94719SBhavya Kapoor clocks = <&k3_clks 152 0>, <&k3_clks 152 2>; 112603b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 112703b94719SBhavya Kapoor interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 112803b94719SBhavya Kapoor <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 112903b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 113003b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 113103b94719SBhavya Kapoor status = "disabled"; 113203b94719SBhavya Kapoor }; 113303b94719SBhavya Kapoor 113403b94719SBhavya Kapoor main_mcan17: can@26b1000 { 113503b94719SBhavya Kapoor compatible = "bosch,m_can"; 113603b94719SBhavya Kapoor reg = <0x00 0x026b1000 0x00 0x200>, 113703b94719SBhavya Kapoor <0x00 0x026b8000 0x00 0x8000>; 113803b94719SBhavya Kapoor reg-names = "m_can", "message_ram"; 113903b94719SBhavya Kapoor power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 114003b94719SBhavya Kapoor clocks = <&k3_clks 153 0>, <&k3_clks 153 2>; 114103b94719SBhavya Kapoor clock-names = "hclk", "cclk"; 114203b94719SBhavya Kapoor interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 114303b94719SBhavya Kapoor <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 114403b94719SBhavya Kapoor interrupt-names = "int0", "int1"; 114503b94719SBhavya Kapoor bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 114603b94719SBhavya Kapoor status = "disabled"; 114703b94719SBhavya Kapoor }; 114803b94719SBhavya Kapoor 11498f6c475fSVaishnav Achath main_spi0: spi@2100000 { 11508f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 11518f6c475fSVaishnav Achath reg = <0x00 0x02100000 0x00 0x400>; 11528f6c475fSVaishnav Achath interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 11538f6c475fSVaishnav Achath #address-cells = <1>; 11548f6c475fSVaishnav Achath #size-cells = <0>; 11558f6c475fSVaishnav Achath power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 11568f6c475fSVaishnav Achath clocks = <&k3_clks 266 1>; 11578f6c475fSVaishnav Achath status = "disabled"; 11588f6c475fSVaishnav Achath }; 11598f6c475fSVaishnav Achath 11608f6c475fSVaishnav Achath main_spi1: spi@2110000 { 11618f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 11628f6c475fSVaishnav Achath reg = <0x00 0x02110000 0x00 0x400>; 11638f6c475fSVaishnav Achath interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 11648f6c475fSVaishnav Achath #address-cells = <1>; 11658f6c475fSVaishnav Achath #size-cells = <0>; 11668f6c475fSVaishnav Achath power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 11678f6c475fSVaishnav Achath clocks = <&k3_clks 267 1>; 11688f6c475fSVaishnav Achath status = "disabled"; 11698f6c475fSVaishnav Achath }; 11708f6c475fSVaishnav Achath 11718f6c475fSVaishnav Achath main_spi2: spi@2120000 { 11728f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 11738f6c475fSVaishnav Achath reg = <0x00 0x02120000 0x00 0x400>; 11748f6c475fSVaishnav Achath interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 11758f6c475fSVaishnav Achath #address-cells = <1>; 11768f6c475fSVaishnav Achath #size-cells = <0>; 11778f6c475fSVaishnav Achath power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 11788f6c475fSVaishnav Achath clocks = <&k3_clks 268 1>; 11798f6c475fSVaishnav Achath status = "disabled"; 11808f6c475fSVaishnav Achath }; 11818f6c475fSVaishnav Achath 11828f6c475fSVaishnav Achath main_spi3: spi@2130000 { 11838f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 11848f6c475fSVaishnav Achath reg = <0x00 0x02130000 0x00 0x400>; 11858f6c475fSVaishnav Achath interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 11868f6c475fSVaishnav Achath #address-cells = <1>; 11878f6c475fSVaishnav Achath #size-cells = <0>; 11888f6c475fSVaishnav Achath power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 11898f6c475fSVaishnav Achath clocks = <&k3_clks 269 1>; 11908f6c475fSVaishnav Achath status = "disabled"; 11918f6c475fSVaishnav Achath }; 11928f6c475fSVaishnav Achath 11938f6c475fSVaishnav Achath main_spi4: spi@2140000 { 11948f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 11958f6c475fSVaishnav Achath reg = <0x00 0x02140000 0x00 0x400>; 11968f6c475fSVaishnav Achath interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 11978f6c475fSVaishnav Achath #address-cells = <1>; 11988f6c475fSVaishnav Achath #size-cells = <0>; 11998f6c475fSVaishnav Achath power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 12008f6c475fSVaishnav Achath clocks = <&k3_clks 270 1>; 12018f6c475fSVaishnav Achath status = "disabled"; 12028f6c475fSVaishnav Achath }; 12038f6c475fSVaishnav Achath 12048f6c475fSVaishnav Achath main_spi5: spi@2150000 { 12058f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 12068f6c475fSVaishnav Achath reg = <0x00 0x02150000 0x00 0x400>; 12078f6c475fSVaishnav Achath interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 12088f6c475fSVaishnav Achath #address-cells = <1>; 12098f6c475fSVaishnav Achath #size-cells = <0>; 12108f6c475fSVaishnav Achath power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 12118f6c475fSVaishnav Achath clocks = <&k3_clks 271 1>; 12128f6c475fSVaishnav Achath status = "disabled"; 12138f6c475fSVaishnav Achath }; 12148f6c475fSVaishnav Achath 12158f6c475fSVaishnav Achath main_spi6: spi@2160000 { 12168f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 12178f6c475fSVaishnav Achath reg = <0x00 0x02160000 0x00 0x400>; 12188f6c475fSVaishnav Achath interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 12198f6c475fSVaishnav Achath #address-cells = <1>; 12208f6c475fSVaishnav Achath #size-cells = <0>; 12218f6c475fSVaishnav Achath power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 12228f6c475fSVaishnav Achath clocks = <&k3_clks 272 1>; 12238f6c475fSVaishnav Achath status = "disabled"; 12248f6c475fSVaishnav Achath }; 12258f6c475fSVaishnav Achath 12268f6c475fSVaishnav Achath main_spi7: spi@2170000 { 12278f6c475fSVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 12288f6c475fSVaishnav Achath reg = <0x00 0x02170000 0x00 0x400>; 12298f6c475fSVaishnav Achath interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 12308f6c475fSVaishnav Achath #address-cells = <1>; 12318f6c475fSVaishnav Achath #size-cells = <0>; 12328f6c475fSVaishnav Achath power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 12338f6c475fSVaishnav Achath clocks = <&k3_clks 273 1>; 12348f6c475fSVaishnav Achath status = "disabled"; 12358f6c475fSVaishnav Achath }; 12368f6c475fSVaishnav Achath 12376038f117SGowtham Tammana watchdog0: watchdog@2200000 { 12386038f117SGowtham Tammana compatible = "ti,j7-rti-wdt"; 12396038f117SGowtham Tammana reg = <0x0 0x2200000 0x0 0x100>; 12406038f117SGowtham Tammana clocks = <&k3_clks 252 1>; 12416038f117SGowtham Tammana power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 12426038f117SGowtham Tammana assigned-clocks = <&k3_clks 252 1>; 12436038f117SGowtham Tammana assigned-clock-parents = <&k3_clks 252 5>; 12446038f117SGowtham Tammana }; 12456038f117SGowtham Tammana 12466038f117SGowtham Tammana watchdog1: watchdog@2210000 { 12476038f117SGowtham Tammana compatible = "ti,j7-rti-wdt"; 12486038f117SGowtham Tammana reg = <0x0 0x2210000 0x0 0x100>; 12496038f117SGowtham Tammana clocks = <&k3_clks 253 1>; 12506038f117SGowtham Tammana power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 12516038f117SGowtham Tammana assigned-clocks = <&k3_clks 253 1>; 12526038f117SGowtham Tammana assigned-clock-parents = <&k3_clks 253 5>; 12536038f117SGowtham Tammana }; 12546038f117SGowtham Tammana 1255c8a28ed4SUdit Kumar main_timer0: timer@2400000 { 1256c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1257c8a28ed4SUdit Kumar reg = <0x00 0x2400000 0x00 0x400>; 1258c8a28ed4SUdit Kumar interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1259c8a28ed4SUdit Kumar clocks = <&k3_clks 49 1>; 1260c8a28ed4SUdit Kumar clock-names = "fck"; 1261c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 49 1>; 1262c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 49 2>; 1263c8a28ed4SUdit Kumar power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1264c8a28ed4SUdit Kumar ti,timer-pwm; 1265c8a28ed4SUdit Kumar }; 1266c8a28ed4SUdit Kumar 1267c8a28ed4SUdit Kumar main_timer1: timer@2410000 { 1268c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1269c8a28ed4SUdit Kumar reg = <0x00 0x2410000 0x00 0x400>; 1270c8a28ed4SUdit Kumar interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1271c8a28ed4SUdit Kumar clocks = <&k3_clks 50 1>; 1272c8a28ed4SUdit Kumar clock-names = "fck"; 1273c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; 1274c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; 1275c8a28ed4SUdit Kumar power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1276c8a28ed4SUdit Kumar ti,timer-pwm; 1277c8a28ed4SUdit Kumar }; 1278c8a28ed4SUdit Kumar 1279c8a28ed4SUdit Kumar main_timer2: timer@2420000 { 1280c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1281c8a28ed4SUdit Kumar reg = <0x00 0x2420000 0x00 0x400>; 1282c8a28ed4SUdit Kumar interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1283c8a28ed4SUdit Kumar clocks = <&k3_clks 51 1>; 1284c8a28ed4SUdit Kumar clock-names = "fck"; 1285c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 51 1>; 1286c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 51 2>; 1287c8a28ed4SUdit Kumar power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1288c8a28ed4SUdit Kumar ti,timer-pwm; 1289c8a28ed4SUdit Kumar }; 1290c8a28ed4SUdit Kumar 1291c8a28ed4SUdit Kumar main_timer3: timer@2430000 { 1292c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1293c8a28ed4SUdit Kumar reg = <0x00 0x2430000 0x00 0x400>; 1294c8a28ed4SUdit Kumar interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1295c8a28ed4SUdit Kumar clocks = <&k3_clks 52 1>; 1296c8a28ed4SUdit Kumar clock-names = "fck"; 1297c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; 1298c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; 1299c8a28ed4SUdit Kumar power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1300c8a28ed4SUdit Kumar ti,timer-pwm; 1301c8a28ed4SUdit Kumar }; 1302c8a28ed4SUdit Kumar 1303c8a28ed4SUdit Kumar main_timer4: timer@2440000 { 1304c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1305c8a28ed4SUdit Kumar reg = <0x00 0x2440000 0x00 0x400>; 1306c8a28ed4SUdit Kumar interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1307c8a28ed4SUdit Kumar clocks = <&k3_clks 53 1>; 1308c8a28ed4SUdit Kumar clock-names = "fck"; 1309c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 53 1>; 1310c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 53 2>; 1311c8a28ed4SUdit Kumar power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1312c8a28ed4SUdit Kumar ti,timer-pwm; 1313c8a28ed4SUdit Kumar }; 1314c8a28ed4SUdit Kumar 1315c8a28ed4SUdit Kumar main_timer5: timer@2450000 { 1316c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1317c8a28ed4SUdit Kumar reg = <0x00 0x2450000 0x00 0x400>; 1318c8a28ed4SUdit Kumar interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1319c8a28ed4SUdit Kumar clocks = <&k3_clks 54 1>; 1320c8a28ed4SUdit Kumar clock-names = "fck"; 1321c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; 1322c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; 1323c8a28ed4SUdit Kumar power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1324c8a28ed4SUdit Kumar ti,timer-pwm; 1325c8a28ed4SUdit Kumar }; 1326c8a28ed4SUdit Kumar 1327c8a28ed4SUdit Kumar main_timer6: timer@2460000 { 1328c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1329c8a28ed4SUdit Kumar reg = <0x00 0x2460000 0x00 0x400>; 1330c8a28ed4SUdit Kumar interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1331c8a28ed4SUdit Kumar clocks = <&k3_clks 55 1>; 1332c8a28ed4SUdit Kumar clock-names = "fck"; 1333c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 55 1>; 1334c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 55 2>; 1335c8a28ed4SUdit Kumar power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1336c8a28ed4SUdit Kumar ti,timer-pwm; 1337c8a28ed4SUdit Kumar }; 1338c8a28ed4SUdit Kumar 1339c8a28ed4SUdit Kumar main_timer7: timer@2470000 { 1340c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1341c8a28ed4SUdit Kumar reg = <0x00 0x2470000 0x00 0x400>; 1342c8a28ed4SUdit Kumar interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1343c8a28ed4SUdit Kumar clocks = <&k3_clks 57 1>; 1344c8a28ed4SUdit Kumar clock-names = "fck"; 1345c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; 1346c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; 1347c8a28ed4SUdit Kumar power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1348c8a28ed4SUdit Kumar ti,timer-pwm; 1349c8a28ed4SUdit Kumar }; 1350c8a28ed4SUdit Kumar 1351c8a28ed4SUdit Kumar main_timer8: timer@2480000 { 1352c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1353c8a28ed4SUdit Kumar reg = <0x00 0x2480000 0x00 0x400>; 1354c8a28ed4SUdit Kumar interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1355c8a28ed4SUdit Kumar clocks = <&k3_clks 58 1>; 1356c8a28ed4SUdit Kumar clock-names = "fck"; 1357c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 58 1>; 1358c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 58 2>; 1359c8a28ed4SUdit Kumar power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1360c8a28ed4SUdit Kumar ti,timer-pwm; 1361c8a28ed4SUdit Kumar }; 1362c8a28ed4SUdit Kumar 1363c8a28ed4SUdit Kumar main_timer9: timer@2490000 { 1364c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1365c8a28ed4SUdit Kumar reg = <0x00 0x2490000 0x00 0x400>; 1366c8a28ed4SUdit Kumar interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1367c8a28ed4SUdit Kumar clocks = <&k3_clks 59 1>; 1368c8a28ed4SUdit Kumar clock-names = "fck"; 1369c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; 1370c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; 1371c8a28ed4SUdit Kumar power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1372c8a28ed4SUdit Kumar ti,timer-pwm; 1373c8a28ed4SUdit Kumar }; 1374c8a28ed4SUdit Kumar 1375c8a28ed4SUdit Kumar main_timer10: timer@24a0000 { 1376c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1377c8a28ed4SUdit Kumar reg = <0x00 0x24a0000 0x00 0x400>; 1378c8a28ed4SUdit Kumar interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1379c8a28ed4SUdit Kumar clocks = <&k3_clks 60 1>; 1380c8a28ed4SUdit Kumar clock-names = "fck"; 1381c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 60 1>; 1382c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 60 2>; 1383c8a28ed4SUdit Kumar power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1384c8a28ed4SUdit Kumar ti,timer-pwm; 1385c8a28ed4SUdit Kumar }; 1386c8a28ed4SUdit Kumar 1387c8a28ed4SUdit Kumar main_timer11: timer@24b0000 { 1388c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1389c8a28ed4SUdit Kumar reg = <0x00 0x24b0000 0x00 0x400>; 1390c8a28ed4SUdit Kumar interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1391c8a28ed4SUdit Kumar clocks = <&k3_clks 62 1>; 1392c8a28ed4SUdit Kumar clock-names = "fck"; 1393c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; 1394c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; 1395c8a28ed4SUdit Kumar power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1396c8a28ed4SUdit Kumar ti,timer-pwm; 1397c8a28ed4SUdit Kumar }; 1398c8a28ed4SUdit Kumar 1399c8a28ed4SUdit Kumar main_timer12: timer@24c0000 { 1400c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1401c8a28ed4SUdit Kumar reg = <0x00 0x24c0000 0x00 0x400>; 1402c8a28ed4SUdit Kumar interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1403c8a28ed4SUdit Kumar clocks = <&k3_clks 63 1>; 1404c8a28ed4SUdit Kumar clock-names = "fck"; 1405c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 63 1>; 1406c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 63 2>; 1407c8a28ed4SUdit Kumar power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1408c8a28ed4SUdit Kumar ti,timer-pwm; 1409c8a28ed4SUdit Kumar }; 1410c8a28ed4SUdit Kumar 1411c8a28ed4SUdit Kumar main_timer13: timer@24d0000 { 1412c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1413c8a28ed4SUdit Kumar reg = <0x00 0x24d0000 0x00 0x400>; 1414c8a28ed4SUdit Kumar interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1415c8a28ed4SUdit Kumar clocks = <&k3_clks 64 1>; 1416c8a28ed4SUdit Kumar clock-names = "fck"; 1417c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; 1418c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; 1419c8a28ed4SUdit Kumar power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1420c8a28ed4SUdit Kumar ti,timer-pwm; 1421c8a28ed4SUdit Kumar }; 1422c8a28ed4SUdit Kumar 1423c8a28ed4SUdit Kumar main_timer14: timer@24e0000 { 1424c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1425c8a28ed4SUdit Kumar reg = <0x00 0x24e0000 0x00 0x400>; 1426c8a28ed4SUdit Kumar interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1427c8a28ed4SUdit Kumar clocks = <&k3_clks 65 1>; 1428c8a28ed4SUdit Kumar clock-names = "fck"; 1429c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 65 1>; 1430c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 65 2>; 1431c8a28ed4SUdit Kumar power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1432c8a28ed4SUdit Kumar ti,timer-pwm; 1433c8a28ed4SUdit Kumar }; 1434c8a28ed4SUdit Kumar 1435c8a28ed4SUdit Kumar main_timer15: timer@24f0000 { 1436c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1437c8a28ed4SUdit Kumar reg = <0x00 0x24f0000 0x00 0x400>; 1438c8a28ed4SUdit Kumar interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1439c8a28ed4SUdit Kumar clocks = <&k3_clks 66 1>; 1440c8a28ed4SUdit Kumar clock-names = "fck"; 1441c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; 1442c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; 1443c8a28ed4SUdit Kumar power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1444c8a28ed4SUdit Kumar ti,timer-pwm; 1445c8a28ed4SUdit Kumar }; 1446c8a28ed4SUdit Kumar 1447c8a28ed4SUdit Kumar main_timer16: timer@2500000 { 1448c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1449c8a28ed4SUdit Kumar reg = <0x00 0x2500000 0x00 0x400>; 1450c8a28ed4SUdit Kumar interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1451c8a28ed4SUdit Kumar clocks = <&k3_clks 67 1>; 1452c8a28ed4SUdit Kumar clock-names = "fck"; 1453c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 67 1>; 1454c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 67 2>; 1455c8a28ed4SUdit Kumar power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1456c8a28ed4SUdit Kumar ti,timer-pwm; 1457c8a28ed4SUdit Kumar }; 1458c8a28ed4SUdit Kumar 1459c8a28ed4SUdit Kumar main_timer17: timer@2510000 { 1460c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1461c8a28ed4SUdit Kumar reg = <0x00 0x2510000 0x00 0x400>; 1462c8a28ed4SUdit Kumar interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1463c8a28ed4SUdit Kumar clocks = <&k3_clks 68 1>; 1464c8a28ed4SUdit Kumar clock-names = "fck"; 1465c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; 1466c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; 1467c8a28ed4SUdit Kumar power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1468c8a28ed4SUdit Kumar ti,timer-pwm; 1469c8a28ed4SUdit Kumar }; 1470c8a28ed4SUdit Kumar 1471c8a28ed4SUdit Kumar main_timer18: timer@2520000 { 1472c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1473c8a28ed4SUdit Kumar reg = <0x00 0x2520000 0x00 0x400>; 1474c8a28ed4SUdit Kumar interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1475c8a28ed4SUdit Kumar clocks = <&k3_clks 69 1>; 1476c8a28ed4SUdit Kumar clock-names = "fck"; 1477c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 69 1>; 1478c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 69 2>; 1479c8a28ed4SUdit Kumar power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1480c8a28ed4SUdit Kumar ti,timer-pwm; 1481c8a28ed4SUdit Kumar }; 1482c8a28ed4SUdit Kumar 1483c8a28ed4SUdit Kumar main_timer19: timer@2530000 { 1484c8a28ed4SUdit Kumar compatible = "ti,am654-timer"; 1485c8a28ed4SUdit Kumar reg = <0x00 0x2530000 0x00 0x400>; 1486c8a28ed4SUdit Kumar interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1487c8a28ed4SUdit Kumar clocks = <&k3_clks 70 1>; 1488c8a28ed4SUdit Kumar clock-names = "fck"; 1489c8a28ed4SUdit Kumar assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; 1490c8a28ed4SUdit Kumar assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; 1491c8a28ed4SUdit Kumar power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1492c8a28ed4SUdit Kumar ti,timer-pwm; 1493c8a28ed4SUdit Kumar }; 1494c8a28ed4SUdit Kumar 1495eb6f3655SSuman Anna main_r5fss0: r5fss@5c00000 { 1496eb6f3655SSuman Anna compatible = "ti,j7200-r5fss"; 1497eb6f3655SSuman Anna ti,cluster-mode = <1>; 1498eb6f3655SSuman Anna #address-cells = <1>; 1499eb6f3655SSuman Anna #size-cells = <1>; 1500eb6f3655SSuman Anna ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1501eb6f3655SSuman Anna <0x5d00000 0x00 0x5d00000 0x20000>; 1502eb6f3655SSuman Anna power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1503eb6f3655SSuman Anna 1504eb6f3655SSuman Anna main_r5fss0_core0: r5f@5c00000 { 1505eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 1506eb6f3655SSuman Anna reg = <0x5c00000 0x00010000>, 1507eb6f3655SSuman Anna <0x5c10000 0x00010000>; 1508eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 1509eb6f3655SSuman Anna ti,sci = <&dmsc>; 1510eb6f3655SSuman Anna ti,sci-dev-id = <245>; 1511eb6f3655SSuman Anna ti,sci-proc-ids = <0x06 0xff>; 1512eb6f3655SSuman Anna resets = <&k3_reset 245 1>; 1513eb6f3655SSuman Anna firmware-name = "j7200-main-r5f0_0-fw"; 1514eb6f3655SSuman Anna ti,atcm-enable = <1>; 1515eb6f3655SSuman Anna ti,btcm-enable = <1>; 1516eb6f3655SSuman Anna ti,loczrama = <1>; 1517eb6f3655SSuman Anna }; 1518eb6f3655SSuman Anna 1519eb6f3655SSuman Anna main_r5fss0_core1: r5f@5d00000 { 1520eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 1521eb6f3655SSuman Anna reg = <0x5d00000 0x00008000>, 1522eb6f3655SSuman Anna <0x5d10000 0x00008000>; 1523eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 1524eb6f3655SSuman Anna ti,sci = <&dmsc>; 1525eb6f3655SSuman Anna ti,sci-dev-id = <246>; 1526eb6f3655SSuman Anna ti,sci-proc-ids = <0x07 0xff>; 1527eb6f3655SSuman Anna resets = <&k3_reset 246 1>; 1528eb6f3655SSuman Anna firmware-name = "j7200-main-r5f0_1-fw"; 1529eb6f3655SSuman Anna ti,atcm-enable = <1>; 1530eb6f3655SSuman Anna ti,btcm-enable = <1>; 1531eb6f3655SSuman Anna ti,loczrama = <1>; 1532eb6f3655SSuman Anna }; 1533eb6f3655SSuman Anna }; 1534e3d1f276SNeha Malcom Francis 1535e3d1f276SNeha Malcom Francis main_esm: esm@700000 { 1536e3d1f276SNeha Malcom Francis compatible = "ti,j721e-esm"; 1537e3d1f276SNeha Malcom Francis reg = <0x0 0x700000 0x0 0x1000>; 1538e3d1f276SNeha Malcom Francis ti,esm-pins = <656>, <657>; 1539e3d1f276SNeha Malcom Francis }; 1540d361ed88SLokesh Vutla}; 1541