1d361ed88SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 2d361ed88SLokesh Vutla/* 3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family Main Domain peripherals 4d361ed88SLokesh Vutla * 5d361ed88SLokesh Vutla * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6d361ed88SLokesh Vutla */ 7d361ed88SLokesh Vutla 8d361ed88SLokesh Vutla&cbass_main { 9d361ed88SLokesh Vutla msmc_ram: sram@70000000 { 10d361ed88SLokesh Vutla compatible = "mmio-sram"; 11d361ed88SLokesh Vutla reg = <0x00 0x70000000 0x00 0x100000>; 12d361ed88SLokesh Vutla #address-cells = <1>; 13d361ed88SLokesh Vutla #size-cells = <1>; 14d361ed88SLokesh Vutla ranges = <0x00 0x00 0x70000000 0x100000>; 15d361ed88SLokesh Vutla 16d361ed88SLokesh Vutla atf-sram@0 { 17d361ed88SLokesh Vutla reg = <0x00 0x20000>; 18d361ed88SLokesh Vutla }; 19d361ed88SLokesh Vutla }; 20d361ed88SLokesh Vutla 2115092952SRoger Quadros scm_conf: scm-conf@100000 { 2215092952SRoger Quadros compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 2315092952SRoger Quadros reg = <0x00 0x00100000 0x00 0x1c000>; 2415092952SRoger Quadros #address-cells = <1>; 2515092952SRoger Quadros #size-cells = <1>; 2615092952SRoger Quadros ranges = <0x00 0x00 0x00100000 0x1c000>; 2715092952SRoger Quadros 2815092952SRoger Quadros serdes_ln_ctrl: serdes-ln-ctrl@4080 { 2915092952SRoger Quadros compatible = "mmio-mux"; 3015092952SRoger Quadros #mux-control-cells = <1>; 3115092952SRoger Quadros mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 3215092952SRoger Quadros <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 3315092952SRoger Quadros }; 349a09e6e9SRoger Quadros 359a09e6e9SRoger Quadros usb_serdes_mux: mux-controller@4000 { 369a09e6e9SRoger Quadros compatible = "mmio-mux"; 379a09e6e9SRoger Quadros #mux-control-cells = <1>; 389a09e6e9SRoger Quadros mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 399a09e6e9SRoger Quadros }; 4015092952SRoger Quadros }; 4115092952SRoger Quadros 42d361ed88SLokesh Vutla gic500: interrupt-controller@1800000 { 43d361ed88SLokesh Vutla compatible = "arm,gic-v3"; 44d361ed88SLokesh Vutla #address-cells = <2>; 45d361ed88SLokesh Vutla #size-cells = <2>; 46d361ed88SLokesh Vutla ranges; 47d361ed88SLokesh Vutla #interrupt-cells = <3>; 48d361ed88SLokesh Vutla interrupt-controller; 49d361ed88SLokesh Vutla reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 50d361ed88SLokesh Vutla <0x00 0x01900000 0x00 0x100000>; /* GICR */ 51d361ed88SLokesh Vutla 52d361ed88SLokesh Vutla /* vcpumntirq: virtual CPU interface maintenance interrupt */ 53d361ed88SLokesh Vutla interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 54d361ed88SLokesh Vutla 55d361ed88SLokesh Vutla gic_its: msi-controller@1820000 { 56d361ed88SLokesh Vutla compatible = "arm,gic-v3-its"; 57d361ed88SLokesh Vutla reg = <0x00 0x01820000 0x00 0x10000>; 58d361ed88SLokesh Vutla socionext,synquacer-pre-its = <0x1000000 0x400000>; 59d361ed88SLokesh Vutla msi-controller; 60d361ed88SLokesh Vutla #msi-cells = <1>; 61d361ed88SLokesh Vutla }; 62d361ed88SLokesh Vutla }; 63d361ed88SLokesh Vutla 64d361ed88SLokesh Vutla main_gpio_intr: interrupt-controller0 { 65d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 66d361ed88SLokesh Vutla ti,intr-trigger-type = <1>; 67d361ed88SLokesh Vutla interrupt-controller; 68d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 69d361ed88SLokesh Vutla #interrupt-cells = <1>; 70d361ed88SLokesh Vutla ti,sci = <&dmsc>; 71d361ed88SLokesh Vutla ti,sci-dev-id = <131>; 72d361ed88SLokesh Vutla ti,interrupt-ranges = <8 392 56>; 73d361ed88SLokesh Vutla }; 74d361ed88SLokesh Vutla 75d361ed88SLokesh Vutla main_navss: bus@30000000 { 76d361ed88SLokesh Vutla compatible = "simple-mfd"; 77d361ed88SLokesh Vutla #address-cells = <2>; 78d361ed88SLokesh Vutla #size-cells = <2>; 79d361ed88SLokesh Vutla ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 80d361ed88SLokesh Vutla ti,sci-dev-id = <199>; 81d361ed88SLokesh Vutla 82d361ed88SLokesh Vutla main_navss_intr: interrupt-controller1 { 83d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 84d361ed88SLokesh Vutla ti,intr-trigger-type = <4>; 85d361ed88SLokesh Vutla interrupt-controller; 86d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 87d361ed88SLokesh Vutla #interrupt-cells = <1>; 88d361ed88SLokesh Vutla ti,sci = <&dmsc>; 89d361ed88SLokesh Vutla ti,sci-dev-id = <213>; 90d361ed88SLokesh Vutla ti,interrupt-ranges = <0 64 64>, 91d361ed88SLokesh Vutla <64 448 64>, 92d361ed88SLokesh Vutla <128 672 64>; 93d361ed88SLokesh Vutla }; 94d361ed88SLokesh Vutla 95d361ed88SLokesh Vutla main_udmass_inta: msi-controller@33d00000 { 96d361ed88SLokesh Vutla compatible = "ti,sci-inta"; 97d361ed88SLokesh Vutla reg = <0x00 0x33d00000 0x00 0x100000>; 98d361ed88SLokesh Vutla interrupt-controller; 99d361ed88SLokesh Vutla #interrupt-cells = <0>; 100d361ed88SLokesh Vutla interrupt-parent = <&main_navss_intr>; 101d361ed88SLokesh Vutla msi-controller; 102d361ed88SLokesh Vutla ti,sci = <&dmsc>; 103d361ed88SLokesh Vutla ti,sci-dev-id = <209>; 104d361ed88SLokesh Vutla ti,interrupt-ranges = <0 0 256>; 105d361ed88SLokesh Vutla }; 106d361ed88SLokesh Vutla 107d361ed88SLokesh Vutla secure_proxy_main: mailbox@32c00000 { 108d361ed88SLokesh Vutla compatible = "ti,am654-secure-proxy"; 109d361ed88SLokesh Vutla #mbox-cells = <1>; 110d361ed88SLokesh Vutla reg-names = "target_data", "rt", "scfg"; 111d361ed88SLokesh Vutla reg = <0x00 0x32c00000 0x00 0x100000>, 112d361ed88SLokesh Vutla <0x00 0x32400000 0x00 0x100000>, 113d361ed88SLokesh Vutla <0x00 0x32800000 0x00 0x100000>; 114d361ed88SLokesh Vutla interrupt-names = "rx_011"; 115d361ed88SLokesh Vutla interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 116d361ed88SLokesh Vutla }; 11746374264SPeter Ujfalusi 11846374264SPeter Ujfalusi main_ringacc: ringacc@3c000000 { 11946374264SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 12046374264SPeter Ujfalusi reg = <0x00 0x3c000000 0x00 0x400000>, 12146374264SPeter Ujfalusi <0x00 0x38000000 0x00 0x400000>, 12246374264SPeter Ujfalusi <0x00 0x31120000 0x00 0x100>, 12346374264SPeter Ujfalusi <0x00 0x33000000 0x00 0x40000>; 12446374264SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 12546374264SPeter Ujfalusi ti,num-rings = <1024>; 12646374264SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 12746374264SPeter Ujfalusi ti,sci = <&dmsc>; 12846374264SPeter Ujfalusi ti,sci-dev-id = <211>; 12946374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 13046374264SPeter Ujfalusi }; 13146374264SPeter Ujfalusi 13246374264SPeter Ujfalusi main_udmap: dma-controller@31150000 { 13346374264SPeter Ujfalusi compatible = "ti,j721e-navss-main-udmap"; 13446374264SPeter Ujfalusi reg = <0x00 0x31150000 0x00 0x100>, 13546374264SPeter Ujfalusi <0x00 0x34000000 0x00 0x100000>, 13646374264SPeter Ujfalusi <0x00 0x35000000 0x00 0x100000>; 13746374264SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 13846374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 13946374264SPeter Ujfalusi #dma-cells = <1>; 14046374264SPeter Ujfalusi 14146374264SPeter Ujfalusi ti,sci = <&dmsc>; 14246374264SPeter Ujfalusi ti,sci-dev-id = <212>; 14346374264SPeter Ujfalusi ti,ringacc = <&main_ringacc>; 14446374264SPeter Ujfalusi 14546374264SPeter Ujfalusi ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 14646374264SPeter Ujfalusi <0x0f>, /* TX_HCHAN */ 14746374264SPeter Ujfalusi <0x10>; /* TX_UHCHAN */ 14846374264SPeter Ujfalusi ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 14946374264SPeter Ujfalusi <0x0b>, /* RX_HCHAN */ 15046374264SPeter Ujfalusi <0x0c>; /* RX_UHCHAN */ 15146374264SPeter Ujfalusi ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 15246374264SPeter Ujfalusi }; 153c5d73d8dSGrygorii Strashko 154c5d73d8dSGrygorii Strashko cpts@310d0000 { 155c5d73d8dSGrygorii Strashko compatible = "ti,j721e-cpts"; 156c5d73d8dSGrygorii Strashko reg = <0x00 0x310d0000 0x00 0x400>; 157c5d73d8dSGrygorii Strashko reg-names = "cpts"; 158c5d73d8dSGrygorii Strashko clocks = <&k3_clks 201 1>; 159c5d73d8dSGrygorii Strashko clock-names = "cpts"; 160c5d73d8dSGrygorii Strashko interrupts-extended = <&main_navss_intr 391>; 161c5d73d8dSGrygorii Strashko interrupt-names = "cpts"; 162c5d73d8dSGrygorii Strashko ti,cpts-periodic-outputs = <6>; 163c5d73d8dSGrygorii Strashko ti,cpts-ext-ts-inputs = <8>; 164c5d73d8dSGrygorii Strashko }; 165d361ed88SLokesh Vutla }; 166d361ed88SLokesh Vutla 167d361ed88SLokesh Vutla main_pmx0: pinctrl@11c000 { 168d361ed88SLokesh Vutla compatible = "pinctrl-single"; 169d361ed88SLokesh Vutla /* Proxy 0 addressing */ 170d361ed88SLokesh Vutla reg = <0x00 0x11c000 0x00 0x2b4>; 171d361ed88SLokesh Vutla #pinctrl-cells = <1>; 172d361ed88SLokesh Vutla pinctrl-single,register-width = <32>; 173d361ed88SLokesh Vutla pinctrl-single,function-mask = <0xffffffff>; 174d361ed88SLokesh Vutla }; 175d361ed88SLokesh Vutla 176d361ed88SLokesh Vutla main_uart0: serial@2800000 { 177d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 178d361ed88SLokesh Vutla reg = <0x00 0x02800000 0x00 0x100>; 179d361ed88SLokesh Vutla reg-shift = <2>; 180d361ed88SLokesh Vutla reg-io-width = <4>; 181d361ed88SLokesh Vutla interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 182d361ed88SLokesh Vutla clock-frequency = <48000000>; 183d361ed88SLokesh Vutla current-speed = <115200>; 184d361ed88SLokesh Vutla power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 185d361ed88SLokesh Vutla clocks = <&k3_clks 146 2>; 186d361ed88SLokesh Vutla clock-names = "fclk"; 187d361ed88SLokesh Vutla }; 188d361ed88SLokesh Vutla 189d361ed88SLokesh Vutla main_uart1: serial@2810000 { 190d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 191d361ed88SLokesh Vutla reg = <0x00 0x02810000 0x00 0x100>; 192d361ed88SLokesh Vutla reg-shift = <2>; 193d361ed88SLokesh Vutla reg-io-width = <4>; 194d361ed88SLokesh Vutla interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 195d361ed88SLokesh Vutla clock-frequency = <48000000>; 196d361ed88SLokesh Vutla current-speed = <115200>; 197d361ed88SLokesh Vutla power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 198d361ed88SLokesh Vutla clocks = <&k3_clks 278 2>; 199d361ed88SLokesh Vutla clock-names = "fclk"; 200d361ed88SLokesh Vutla }; 201d361ed88SLokesh Vutla 202d361ed88SLokesh Vutla main_uart2: serial@2820000 { 203d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 204d361ed88SLokesh Vutla reg = <0x00 0x02820000 0x00 0x100>; 205d361ed88SLokesh Vutla reg-shift = <2>; 206d361ed88SLokesh Vutla reg-io-width = <4>; 207d361ed88SLokesh Vutla interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 208d361ed88SLokesh Vutla clock-frequency = <48000000>; 209d361ed88SLokesh Vutla current-speed = <115200>; 210d361ed88SLokesh Vutla power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 211d361ed88SLokesh Vutla clocks = <&k3_clks 279 2>; 212d361ed88SLokesh Vutla clock-names = "fclk"; 213d361ed88SLokesh Vutla }; 214d361ed88SLokesh Vutla 215d361ed88SLokesh Vutla main_uart3: serial@2830000 { 216d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 217d361ed88SLokesh Vutla reg = <0x00 0x02830000 0x00 0x100>; 218d361ed88SLokesh Vutla reg-shift = <2>; 219d361ed88SLokesh Vutla reg-io-width = <4>; 220d361ed88SLokesh Vutla interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 221d361ed88SLokesh Vutla clock-frequency = <48000000>; 222d361ed88SLokesh Vutla current-speed = <115200>; 223d361ed88SLokesh Vutla power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 224d361ed88SLokesh Vutla clocks = <&k3_clks 280 2>; 225d361ed88SLokesh Vutla clock-names = "fclk"; 226d361ed88SLokesh Vutla }; 227d361ed88SLokesh Vutla 228d361ed88SLokesh Vutla main_uart4: serial@2840000 { 229d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 230d361ed88SLokesh Vutla reg = <0x00 0x02840000 0x00 0x100>; 231d361ed88SLokesh Vutla reg-shift = <2>; 232d361ed88SLokesh Vutla reg-io-width = <4>; 233d361ed88SLokesh Vutla interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 234d361ed88SLokesh Vutla clock-frequency = <48000000>; 235d361ed88SLokesh Vutla current-speed = <115200>; 236d361ed88SLokesh Vutla power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 237d361ed88SLokesh Vutla clocks = <&k3_clks 281 2>; 238d361ed88SLokesh Vutla clock-names = "fclk"; 239d361ed88SLokesh Vutla }; 240d361ed88SLokesh Vutla 241d361ed88SLokesh Vutla main_uart5: serial@2850000 { 242d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 243d361ed88SLokesh Vutla reg = <0x00 0x02850000 0x00 0x100>; 244d361ed88SLokesh Vutla reg-shift = <2>; 245d361ed88SLokesh Vutla reg-io-width = <4>; 246d361ed88SLokesh Vutla interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 247d361ed88SLokesh Vutla clock-frequency = <48000000>; 248d361ed88SLokesh Vutla current-speed = <115200>; 249d361ed88SLokesh Vutla power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 250d361ed88SLokesh Vutla clocks = <&k3_clks 282 2>; 251d361ed88SLokesh Vutla clock-names = "fclk"; 252d361ed88SLokesh Vutla }; 253d361ed88SLokesh Vutla 254d361ed88SLokesh Vutla main_uart6: serial@2860000 { 255d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 256d361ed88SLokesh Vutla reg = <0x00 0x02860000 0x00 0x100>; 257d361ed88SLokesh Vutla reg-shift = <2>; 258d361ed88SLokesh Vutla reg-io-width = <4>; 259d361ed88SLokesh Vutla interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 260d361ed88SLokesh Vutla clock-frequency = <48000000>; 261d361ed88SLokesh Vutla current-speed = <115200>; 262d361ed88SLokesh Vutla power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 263d361ed88SLokesh Vutla clocks = <&k3_clks 283 2>; 264d361ed88SLokesh Vutla clock-names = "fclk"; 265d361ed88SLokesh Vutla }; 266d361ed88SLokesh Vutla 267d361ed88SLokesh Vutla main_uart7: serial@2870000 { 268d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 269d361ed88SLokesh Vutla reg = <0x00 0x02870000 0x00 0x100>; 270d361ed88SLokesh Vutla reg-shift = <2>; 271d361ed88SLokesh Vutla reg-io-width = <4>; 272d361ed88SLokesh Vutla interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 273d361ed88SLokesh Vutla clock-frequency = <48000000>; 274d361ed88SLokesh Vutla current-speed = <115200>; 275d361ed88SLokesh Vutla power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 276d361ed88SLokesh Vutla clocks = <&k3_clks 284 2>; 277d361ed88SLokesh Vutla clock-names = "fclk"; 278d361ed88SLokesh Vutla }; 279d361ed88SLokesh Vutla 280d361ed88SLokesh Vutla main_uart8: serial@2880000 { 281d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 282d361ed88SLokesh Vutla reg = <0x00 0x02880000 0x00 0x100>; 283d361ed88SLokesh Vutla reg-shift = <2>; 284d361ed88SLokesh Vutla reg-io-width = <4>; 285d361ed88SLokesh Vutla interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 286d361ed88SLokesh Vutla clock-frequency = <48000000>; 287d361ed88SLokesh Vutla current-speed = <115200>; 288d361ed88SLokesh Vutla power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 289d361ed88SLokesh Vutla clocks = <&k3_clks 285 2>; 290d361ed88SLokesh Vutla clock-names = "fclk"; 291d361ed88SLokesh Vutla }; 292d361ed88SLokesh Vutla 293d361ed88SLokesh Vutla main_uart9: serial@2890000 { 294d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 295d361ed88SLokesh Vutla reg = <0x00 0x02890000 0x00 0x100>; 296d361ed88SLokesh Vutla reg-shift = <2>; 297d361ed88SLokesh Vutla reg-io-width = <4>; 298d361ed88SLokesh Vutla interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 299d361ed88SLokesh Vutla clock-frequency = <48000000>; 300d361ed88SLokesh Vutla current-speed = <115200>; 301d361ed88SLokesh Vutla power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 302d361ed88SLokesh Vutla clocks = <&k3_clks 286 2>; 303d361ed88SLokesh Vutla clock-names = "fclk"; 304d361ed88SLokesh Vutla }; 30503bfeb52SVignesh Raghavendra 30603bfeb52SVignesh Raghavendra main_i2c0: i2c@2000000 { 30703bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 30803bfeb52SVignesh Raghavendra reg = <0x00 0x2000000 0x00 0x100>; 30903bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 31003bfeb52SVignesh Raghavendra #address-cells = <1>; 31103bfeb52SVignesh Raghavendra #size-cells = <0>; 31203bfeb52SVignesh Raghavendra clock-names = "fck"; 31303bfeb52SVignesh Raghavendra clocks = <&k3_clks 187 1>; 31403bfeb52SVignesh Raghavendra power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 31503bfeb52SVignesh Raghavendra }; 31603bfeb52SVignesh Raghavendra 31703bfeb52SVignesh Raghavendra main_i2c1: i2c@2010000 { 31803bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 31903bfeb52SVignesh Raghavendra reg = <0x00 0x2010000 0x00 0x100>; 32003bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 32103bfeb52SVignesh Raghavendra #address-cells = <1>; 32203bfeb52SVignesh Raghavendra #size-cells = <0>; 32303bfeb52SVignesh Raghavendra clock-names = "fck"; 32403bfeb52SVignesh Raghavendra clocks = <&k3_clks 188 1>; 32503bfeb52SVignesh Raghavendra power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 32603bfeb52SVignesh Raghavendra }; 32703bfeb52SVignesh Raghavendra 32803bfeb52SVignesh Raghavendra main_i2c2: i2c@2020000 { 32903bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 33003bfeb52SVignesh Raghavendra reg = <0x00 0x2020000 0x00 0x100>; 33103bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 33203bfeb52SVignesh Raghavendra #address-cells = <1>; 33303bfeb52SVignesh Raghavendra #size-cells = <0>; 33403bfeb52SVignesh Raghavendra clock-names = "fck"; 33503bfeb52SVignesh Raghavendra clocks = <&k3_clks 189 1>; 33603bfeb52SVignesh Raghavendra power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 33703bfeb52SVignesh Raghavendra }; 33803bfeb52SVignesh Raghavendra 33903bfeb52SVignesh Raghavendra main_i2c3: i2c@2030000 { 34003bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 34103bfeb52SVignesh Raghavendra reg = <0x00 0x2030000 0x00 0x100>; 34203bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 34303bfeb52SVignesh Raghavendra #address-cells = <1>; 34403bfeb52SVignesh Raghavendra #size-cells = <0>; 34503bfeb52SVignesh Raghavendra clock-names = "fck"; 34603bfeb52SVignesh Raghavendra clocks = <&k3_clks 190 1>; 34703bfeb52SVignesh Raghavendra power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 34803bfeb52SVignesh Raghavendra }; 34903bfeb52SVignesh Raghavendra 35003bfeb52SVignesh Raghavendra main_i2c4: i2c@2040000 { 35103bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 35203bfeb52SVignesh Raghavendra reg = <0x00 0x2040000 0x00 0x100>; 35303bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 35403bfeb52SVignesh Raghavendra #address-cells = <1>; 35503bfeb52SVignesh Raghavendra #size-cells = <0>; 35603bfeb52SVignesh Raghavendra clock-names = "fck"; 35703bfeb52SVignesh Raghavendra clocks = <&k3_clks 191 1>; 35803bfeb52SVignesh Raghavendra power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 35903bfeb52SVignesh Raghavendra }; 36003bfeb52SVignesh Raghavendra 36103bfeb52SVignesh Raghavendra main_i2c5: i2c@2050000 { 36203bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 36303bfeb52SVignesh Raghavendra reg = <0x00 0x2050000 0x00 0x100>; 36403bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 36503bfeb52SVignesh Raghavendra #address-cells = <1>; 36603bfeb52SVignesh Raghavendra #size-cells = <0>; 36703bfeb52SVignesh Raghavendra clock-names = "fck"; 36803bfeb52SVignesh Raghavendra clocks = <&k3_clks 192 1>; 36903bfeb52SVignesh Raghavendra power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 37003bfeb52SVignesh Raghavendra }; 37103bfeb52SVignesh Raghavendra 37203bfeb52SVignesh Raghavendra main_i2c6: i2c@2060000 { 37303bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 37403bfeb52SVignesh Raghavendra reg = <0x00 0x2060000 0x00 0x100>; 37503bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 37603bfeb52SVignesh Raghavendra #address-cells = <1>; 37703bfeb52SVignesh Raghavendra #size-cells = <0>; 37803bfeb52SVignesh Raghavendra clock-names = "fck"; 37903bfeb52SVignesh Raghavendra clocks = <&k3_clks 193 1>; 38003bfeb52SVignesh Raghavendra power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 38103bfeb52SVignesh Raghavendra }; 3827cd03dc7SFaiz Abbas 3837cd03dc7SFaiz Abbas main_sdhci0: mmc@4f80000 { 3847cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 3857cd03dc7SFaiz Abbas reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 3867cd03dc7SFaiz Abbas interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 3877cd03dc7SFaiz Abbas power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 3887cd03dc7SFaiz Abbas clock-names = "clk_xin", "clk_ahb"; 3897cd03dc7SFaiz Abbas clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 3907cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 3917cd03dc7SFaiz Abbas ti,otap-del-sel-mmc-hs = <0x0>; 3927cd03dc7SFaiz Abbas ti,otap-del-sel-ddr52 = <0x6>; 3937cd03dc7SFaiz Abbas ti,otap-del-sel-hs200 = <0x8>; 3947cd03dc7SFaiz Abbas ti,otap-del-sel-hs400 = <0x0>; 3957cd03dc7SFaiz Abbas ti,strobe-sel = <0x77>; 3967cd03dc7SFaiz Abbas ti,trm-icp = <0x8>; 3977cd03dc7SFaiz Abbas bus-width = <8>; 3987cd03dc7SFaiz Abbas mmc-ddr-1_8v; 3997cd03dc7SFaiz Abbas dma-coherent; 4007cd03dc7SFaiz Abbas }; 4017cd03dc7SFaiz Abbas 4027cd03dc7SFaiz Abbas main_sdhci1: mmc@4fb0000 { 4037cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 4047cd03dc7SFaiz Abbas reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 4057cd03dc7SFaiz Abbas interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 4067cd03dc7SFaiz Abbas power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 4077cd03dc7SFaiz Abbas clock-names = "clk_xin", "clk_ahb"; 4087cd03dc7SFaiz Abbas clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 4097cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 4107cd03dc7SFaiz Abbas ti,otap-del-sel-sd-hs = <0x0>; 4117cd03dc7SFaiz Abbas ti,otap-del-sel-sdr12 = <0xf>; 4127cd03dc7SFaiz Abbas ti,otap-del-sel-sdr25 = <0xf>; 4137cd03dc7SFaiz Abbas ti,otap-del-sel-sdr50 = <0xc>; 4147cd03dc7SFaiz Abbas ti,otap-del-sel-sdr104 = <0x5>; 4157cd03dc7SFaiz Abbas ti,otap-del-sel-ddr50 = <0xc>; 4167cd03dc7SFaiz Abbas no-1-8-v; 4177cd03dc7SFaiz Abbas dma-coherent; 4187cd03dc7SFaiz Abbas }; 419*6197d713SRoger Quadros 420*6197d713SRoger Quadros usbss0: cdns-usb@4104000 { 421*6197d713SRoger Quadros compatible = "ti,j721e-usb"; 422*6197d713SRoger Quadros reg = <0x00 0x4104000 0x00 0x100>; 423*6197d713SRoger Quadros dma-coherent; 424*6197d713SRoger Quadros power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 425*6197d713SRoger Quadros clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 426*6197d713SRoger Quadros clock-names = "ref", "lpm"; 427*6197d713SRoger Quadros assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 428*6197d713SRoger Quadros assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 429*6197d713SRoger Quadros #address-cells = <2>; 430*6197d713SRoger Quadros #size-cells = <2>; 431*6197d713SRoger Quadros ranges; 432*6197d713SRoger Quadros 433*6197d713SRoger Quadros usb0: usb@6000000 { 434*6197d713SRoger Quadros compatible = "cdns,usb3"; 435*6197d713SRoger Quadros reg = <0x00 0x6000000 0x00 0x10000>, 436*6197d713SRoger Quadros <0x00 0x6010000 0x00 0x10000>, 437*6197d713SRoger Quadros <0x00 0x6020000 0x00 0x10000>; 438*6197d713SRoger Quadros reg-names = "otg", "xhci", "dev"; 439*6197d713SRoger Quadros interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 440*6197d713SRoger Quadros <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 441*6197d713SRoger Quadros <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 442*6197d713SRoger Quadros interrupt-names = "host", 443*6197d713SRoger Quadros "peripheral", 444*6197d713SRoger Quadros "otg"; 445*6197d713SRoger Quadros maximum-speed = "super-speed"; 446*6197d713SRoger Quadros dr_mode = "otg"; 447*6197d713SRoger Quadros }; 448*6197d713SRoger Quadros }; 449d361ed88SLokesh Vutla}; 450