1d361ed88SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 2d361ed88SLokesh Vutla/* 3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family Main Domain peripherals 4d361ed88SLokesh Vutla * 5eb6f3655SSuman Anna * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6d361ed88SLokesh Vutla */ 7d361ed88SLokesh Vutla 84c1b22a9SKishon Vijay Abraham I/ { 94c1b22a9SKishon Vijay Abraham I serdes_refclk: serdes-refclk { 104c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 114c1b22a9SKishon Vijay Abraham I compatible = "fixed-clock"; 124c1b22a9SKishon Vijay Abraham I }; 134c1b22a9SKishon Vijay Abraham I}; 144c1b22a9SKishon Vijay Abraham I 15d361ed88SLokesh Vutla&cbass_main { 16d361ed88SLokesh Vutla msmc_ram: sram@70000000 { 17d361ed88SLokesh Vutla compatible = "mmio-sram"; 18d361ed88SLokesh Vutla reg = <0x00 0x70000000 0x00 0x100000>; 19d361ed88SLokesh Vutla #address-cells = <1>; 20d361ed88SLokesh Vutla #size-cells = <1>; 21d361ed88SLokesh Vutla ranges = <0x00 0x00 0x70000000 0x100000>; 22d361ed88SLokesh Vutla 23d361ed88SLokesh Vutla atf-sram@0 { 24d361ed88SLokesh Vutla reg = <0x00 0x20000>; 25d361ed88SLokesh Vutla }; 26d361ed88SLokesh Vutla }; 27d361ed88SLokesh Vutla 2815092952SRoger Quadros scm_conf: scm-conf@100000 { 2915092952SRoger Quadros compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 3015092952SRoger Quadros reg = <0x00 0x00100000 0x00 0x1c000>; 3115092952SRoger Quadros #address-cells = <1>; 3215092952SRoger Quadros #size-cells = <1>; 3315092952SRoger Quadros ranges = <0x00 0x00 0x00100000 0x1c000>; 3415092952SRoger Quadros 354d398490SKishon Vijay Abraham I serdes_ln_ctrl: mux-controller@4080 { 3615092952SRoger Quadros compatible = "mmio-mux"; 3715092952SRoger Quadros #mux-control-cells = <1>; 3815092952SRoger Quadros mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 3915092952SRoger Quadros <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 4015092952SRoger Quadros }; 419a09e6e9SRoger Quadros 429a09e6e9SRoger Quadros usb_serdes_mux: mux-controller@4000 { 439a09e6e9SRoger Quadros compatible = "mmio-mux"; 449a09e6e9SRoger Quadros #mux-control-cells = <1>; 459a09e6e9SRoger Quadros mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 469a09e6e9SRoger Quadros }; 4715092952SRoger Quadros }; 4815092952SRoger Quadros 49d361ed88SLokesh Vutla gic500: interrupt-controller@1800000 { 50d361ed88SLokesh Vutla compatible = "arm,gic-v3"; 51d361ed88SLokesh Vutla #address-cells = <2>; 52d361ed88SLokesh Vutla #size-cells = <2>; 53d361ed88SLokesh Vutla ranges; 54d361ed88SLokesh Vutla #interrupt-cells = <3>; 55d361ed88SLokesh Vutla interrupt-controller; 56d361ed88SLokesh Vutla reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 571a307cc2SNishanth Menon <0x00 0x01900000 0x00 0x100000>, /* GICR */ 581a307cc2SNishanth Menon <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 591a307cc2SNishanth Menon <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 601a307cc2SNishanth Menon <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 61d361ed88SLokesh Vutla 62d361ed88SLokesh Vutla /* vcpumntirq: virtual CPU interface maintenance interrupt */ 63d361ed88SLokesh Vutla interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 64d361ed88SLokesh Vutla 65d361ed88SLokesh Vutla gic_its: msi-controller@1820000 { 66d361ed88SLokesh Vutla compatible = "arm,gic-v3-its"; 67d361ed88SLokesh Vutla reg = <0x00 0x01820000 0x00 0x10000>; 68d361ed88SLokesh Vutla socionext,synquacer-pre-its = <0x1000000 0x400000>; 69d361ed88SLokesh Vutla msi-controller; 70d361ed88SLokesh Vutla #msi-cells = <1>; 71d361ed88SLokesh Vutla }; 72d361ed88SLokesh Vutla }; 73d361ed88SLokesh Vutla 74cab12badSNishanth Menon main_gpio_intr: interrupt-controller@a00000 { 75d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 76cab12badSNishanth Menon reg = <0x00 0x00a00000 0x00 0x800>; 77d361ed88SLokesh Vutla ti,intr-trigger-type = <1>; 78d361ed88SLokesh Vutla interrupt-controller; 79d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 80d361ed88SLokesh Vutla #interrupt-cells = <1>; 81d361ed88SLokesh Vutla ti,sci = <&dmsc>; 82d361ed88SLokesh Vutla ti,sci-dev-id = <131>; 83d361ed88SLokesh Vutla ti,interrupt-ranges = <8 392 56>; 84d361ed88SLokesh Vutla }; 85d361ed88SLokesh Vutla 86d361ed88SLokesh Vutla main_navss: bus@30000000 { 87d361ed88SLokesh Vutla compatible = "simple-mfd"; 88d361ed88SLokesh Vutla #address-cells = <2>; 89d361ed88SLokesh Vutla #size-cells = <2>; 90d361ed88SLokesh Vutla ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 91d361ed88SLokesh Vutla ti,sci-dev-id = <199>; 9252ae30f5SVignesh Raghavendra dma-coherent; 9352ae30f5SVignesh Raghavendra dma-ranges; 94d361ed88SLokesh Vutla 95cab12badSNishanth Menon main_navss_intr: interrupt-controller@310e0000 { 96d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 97cab12badSNishanth Menon reg = <0x00 0x310e0000 0x00 0x4000>; 98d361ed88SLokesh Vutla ti,intr-trigger-type = <4>; 99d361ed88SLokesh Vutla interrupt-controller; 100d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 101d361ed88SLokesh Vutla #interrupt-cells = <1>; 102d361ed88SLokesh Vutla ti,sci = <&dmsc>; 103d361ed88SLokesh Vutla ti,sci-dev-id = <213>; 104d361ed88SLokesh Vutla ti,interrupt-ranges = <0 64 64>, 105d361ed88SLokesh Vutla <64 448 64>, 106d361ed88SLokesh Vutla <128 672 64>; 107d361ed88SLokesh Vutla }; 108d361ed88SLokesh Vutla 109d361ed88SLokesh Vutla main_udmass_inta: msi-controller@33d00000 { 110d361ed88SLokesh Vutla compatible = "ti,sci-inta"; 111d361ed88SLokesh Vutla reg = <0x00 0x33d00000 0x00 0x100000>; 112d361ed88SLokesh Vutla interrupt-controller; 113d361ed88SLokesh Vutla #interrupt-cells = <0>; 114d361ed88SLokesh Vutla interrupt-parent = <&main_navss_intr>; 115d361ed88SLokesh Vutla msi-controller; 116d361ed88SLokesh Vutla ti,sci = <&dmsc>; 117d361ed88SLokesh Vutla ti,sci-dev-id = <209>; 118d361ed88SLokesh Vutla ti,interrupt-ranges = <0 0 256>; 119d361ed88SLokesh Vutla }; 120d361ed88SLokesh Vutla 121d361ed88SLokesh Vutla secure_proxy_main: mailbox@32c00000 { 122d361ed88SLokesh Vutla compatible = "ti,am654-secure-proxy"; 123d361ed88SLokesh Vutla #mbox-cells = <1>; 124d361ed88SLokesh Vutla reg-names = "target_data", "rt", "scfg"; 125d361ed88SLokesh Vutla reg = <0x00 0x32c00000 0x00 0x100000>, 126d361ed88SLokesh Vutla <0x00 0x32400000 0x00 0x100000>, 127d361ed88SLokesh Vutla <0x00 0x32800000 0x00 0x100000>; 128d361ed88SLokesh Vutla interrupt-names = "rx_011"; 129d361ed88SLokesh Vutla interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130d361ed88SLokesh Vutla }; 13146374264SPeter Ujfalusi 1321d7a01c4SSuman Anna hwspinlock: spinlock@30e00000 { 1331d7a01c4SSuman Anna compatible = "ti,am654-hwspinlock"; 1341d7a01c4SSuman Anna reg = <0x00 0x30e00000 0x00 0x1000>; 1351d7a01c4SSuman Anna #hwlock-cells = <1>; 1361d7a01c4SSuman Anna }; 1371d7a01c4SSuman Anna 138d15d1cfbSSuman Anna mailbox0_cluster0: mailbox@31f80000 { 139d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 140d15d1cfbSSuman Anna reg = <0x00 0x31f80000 0x00 0x200>; 141d15d1cfbSSuman Anna #mbox-cells = <1>; 142d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 143d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 144d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 145d15d1cfbSSuman Anna }; 146d15d1cfbSSuman Anna 147d15d1cfbSSuman Anna mailbox0_cluster1: mailbox@31f81000 { 148d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 149d15d1cfbSSuman Anna reg = <0x00 0x31f81000 0x00 0x200>; 150d15d1cfbSSuman Anna #mbox-cells = <1>; 151d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 152d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 153d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 154d15d1cfbSSuman Anna }; 155d15d1cfbSSuman Anna 156d15d1cfbSSuman Anna mailbox0_cluster2: mailbox@31f82000 { 157d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 158d15d1cfbSSuman Anna reg = <0x00 0x31f82000 0x00 0x200>; 159d15d1cfbSSuman Anna #mbox-cells = <1>; 160d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 161d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 162d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 163d15d1cfbSSuman Anna }; 164d15d1cfbSSuman Anna 165d15d1cfbSSuman Anna mailbox0_cluster3: mailbox@31f83000 { 166d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 167d15d1cfbSSuman Anna reg = <0x00 0x31f83000 0x00 0x200>; 168d15d1cfbSSuman Anna #mbox-cells = <1>; 169d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 170d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 171d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 172d15d1cfbSSuman Anna }; 173d15d1cfbSSuman Anna 174d15d1cfbSSuman Anna mailbox0_cluster4: mailbox@31f84000 { 175d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 176d15d1cfbSSuman Anna reg = <0x00 0x31f84000 0x00 0x200>; 177d15d1cfbSSuman Anna #mbox-cells = <1>; 178d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 179d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 180d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 181d15d1cfbSSuman Anna }; 182d15d1cfbSSuman Anna 183d15d1cfbSSuman Anna mailbox0_cluster5: mailbox@31f85000 { 184d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 185d15d1cfbSSuman Anna reg = <0x00 0x31f85000 0x00 0x200>; 186d15d1cfbSSuman Anna #mbox-cells = <1>; 187d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 188d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 189d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 190d15d1cfbSSuman Anna }; 191d15d1cfbSSuman Anna 192d15d1cfbSSuman Anna mailbox0_cluster6: mailbox@31f86000 { 193d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 194d15d1cfbSSuman Anna reg = <0x00 0x31f86000 0x00 0x200>; 195d15d1cfbSSuman Anna #mbox-cells = <1>; 196d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 197d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 198d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 199d15d1cfbSSuman Anna }; 200d15d1cfbSSuman Anna 201d15d1cfbSSuman Anna mailbox0_cluster7: mailbox@31f87000 { 202d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 203d15d1cfbSSuman Anna reg = <0x00 0x31f87000 0x00 0x200>; 204d15d1cfbSSuman Anna #mbox-cells = <1>; 205d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 206d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 207d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 208d15d1cfbSSuman Anna }; 209d15d1cfbSSuman Anna 210d15d1cfbSSuman Anna mailbox0_cluster8: mailbox@31f88000 { 211d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 212d15d1cfbSSuman Anna reg = <0x00 0x31f88000 0x00 0x200>; 213d15d1cfbSSuman Anna #mbox-cells = <1>; 214d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 215d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 216d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 217d15d1cfbSSuman Anna }; 218d15d1cfbSSuman Anna 219d15d1cfbSSuman Anna mailbox0_cluster9: mailbox@31f89000 { 220d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 221d15d1cfbSSuman Anna reg = <0x00 0x31f89000 0x00 0x200>; 222d15d1cfbSSuman Anna #mbox-cells = <1>; 223d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 224d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 225d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 226d15d1cfbSSuman Anna }; 227d15d1cfbSSuman Anna 228d15d1cfbSSuman Anna mailbox0_cluster10: mailbox@31f8a000 { 229d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 230d15d1cfbSSuman Anna reg = <0x00 0x31f8a000 0x00 0x200>; 231d15d1cfbSSuman Anna #mbox-cells = <1>; 232d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 233d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 234d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 235d15d1cfbSSuman Anna }; 236d15d1cfbSSuman Anna 237d15d1cfbSSuman Anna mailbox0_cluster11: mailbox@31f8b000 { 238d15d1cfbSSuman Anna compatible = "ti,am654-mailbox"; 239d15d1cfbSSuman Anna reg = <0x00 0x31f8b000 0x00 0x200>; 240d15d1cfbSSuman Anna #mbox-cells = <1>; 241d15d1cfbSSuman Anna ti,mbox-num-users = <4>; 242d15d1cfbSSuman Anna ti,mbox-num-fifos = <16>; 243d15d1cfbSSuman Anna interrupt-parent = <&main_navss_intr>; 244d15d1cfbSSuman Anna }; 245d15d1cfbSSuman Anna 24646374264SPeter Ujfalusi main_ringacc: ringacc@3c000000 { 24746374264SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 24846374264SPeter Ujfalusi reg = <0x00 0x3c000000 0x00 0x400000>, 24946374264SPeter Ujfalusi <0x00 0x38000000 0x00 0x400000>, 25046374264SPeter Ujfalusi <0x00 0x31120000 0x00 0x100>, 25146374264SPeter Ujfalusi <0x00 0x33000000 0x00 0x40000>; 25246374264SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 25346374264SPeter Ujfalusi ti,num-rings = <1024>; 25446374264SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 25546374264SPeter Ujfalusi ti,sci = <&dmsc>; 25646374264SPeter Ujfalusi ti,sci-dev-id = <211>; 25746374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 25846374264SPeter Ujfalusi }; 25946374264SPeter Ujfalusi 26046374264SPeter Ujfalusi main_udmap: dma-controller@31150000 { 26146374264SPeter Ujfalusi compatible = "ti,j721e-navss-main-udmap"; 26246374264SPeter Ujfalusi reg = <0x00 0x31150000 0x00 0x100>, 26346374264SPeter Ujfalusi <0x00 0x34000000 0x00 0x100000>, 26446374264SPeter Ujfalusi <0x00 0x35000000 0x00 0x100000>; 26546374264SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 26646374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 26746374264SPeter Ujfalusi #dma-cells = <1>; 26846374264SPeter Ujfalusi 26946374264SPeter Ujfalusi ti,sci = <&dmsc>; 27046374264SPeter Ujfalusi ti,sci-dev-id = <212>; 27146374264SPeter Ujfalusi ti,ringacc = <&main_ringacc>; 27246374264SPeter Ujfalusi 27346374264SPeter Ujfalusi ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 27446374264SPeter Ujfalusi <0x0f>, /* TX_HCHAN */ 27546374264SPeter Ujfalusi <0x10>; /* TX_UHCHAN */ 27646374264SPeter Ujfalusi ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 27746374264SPeter Ujfalusi <0x0b>, /* RX_HCHAN */ 27846374264SPeter Ujfalusi <0x0c>; /* RX_UHCHAN */ 27946374264SPeter Ujfalusi ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 28046374264SPeter Ujfalusi }; 281c5d73d8dSGrygorii Strashko 282c5d73d8dSGrygorii Strashko cpts@310d0000 { 283c5d73d8dSGrygorii Strashko compatible = "ti,j721e-cpts"; 284c5d73d8dSGrygorii Strashko reg = <0x00 0x310d0000 0x00 0x400>; 285c5d73d8dSGrygorii Strashko reg-names = "cpts"; 286c5d73d8dSGrygorii Strashko clocks = <&k3_clks 201 1>; 287c5d73d8dSGrygorii Strashko clock-names = "cpts"; 288c5d73d8dSGrygorii Strashko interrupts-extended = <&main_navss_intr 391>; 289c5d73d8dSGrygorii Strashko interrupt-names = "cpts"; 290c5d73d8dSGrygorii Strashko ti,cpts-periodic-outputs = <6>; 291c5d73d8dSGrygorii Strashko ti,cpts-ext-ts-inputs = <8>; 292c5d73d8dSGrygorii Strashko }; 293d361ed88SLokesh Vutla }; 294d361ed88SLokesh Vutla 295d361ed88SLokesh Vutla main_pmx0: pinctrl@11c000 { 296d361ed88SLokesh Vutla compatible = "pinctrl-single"; 297d361ed88SLokesh Vutla /* Proxy 0 addressing */ 298d361ed88SLokesh Vutla reg = <0x00 0x11c000 0x00 0x2b4>; 299d361ed88SLokesh Vutla #pinctrl-cells = <1>; 300d361ed88SLokesh Vutla pinctrl-single,register-width = <32>; 301d361ed88SLokesh Vutla pinctrl-single,function-mask = <0xffffffff>; 302d361ed88SLokesh Vutla }; 303d361ed88SLokesh Vutla 304d361ed88SLokesh Vutla main_uart0: serial@2800000 { 305d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 306d361ed88SLokesh Vutla reg = <0x00 0x02800000 0x00 0x100>; 307d361ed88SLokesh Vutla interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 308d361ed88SLokesh Vutla clock-frequency = <48000000>; 309d361ed88SLokesh Vutla current-speed = <115200>; 310d361ed88SLokesh Vutla power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 311d361ed88SLokesh Vutla clocks = <&k3_clks 146 2>; 312d361ed88SLokesh Vutla clock-names = "fclk"; 313d361ed88SLokesh Vutla }; 314d361ed88SLokesh Vutla 315d361ed88SLokesh Vutla main_uart1: serial@2810000 { 316d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 317d361ed88SLokesh Vutla reg = <0x00 0x02810000 0x00 0x100>; 318d361ed88SLokesh Vutla interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 319d361ed88SLokesh Vutla clock-frequency = <48000000>; 320d361ed88SLokesh Vutla current-speed = <115200>; 321d361ed88SLokesh Vutla power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 322d361ed88SLokesh Vutla clocks = <&k3_clks 278 2>; 323d361ed88SLokesh Vutla clock-names = "fclk"; 324d361ed88SLokesh Vutla }; 325d361ed88SLokesh Vutla 326d361ed88SLokesh Vutla main_uart2: serial@2820000 { 327d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 328d361ed88SLokesh Vutla reg = <0x00 0x02820000 0x00 0x100>; 329d361ed88SLokesh Vutla interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 330d361ed88SLokesh Vutla clock-frequency = <48000000>; 331d361ed88SLokesh Vutla current-speed = <115200>; 332d361ed88SLokesh Vutla power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 333d361ed88SLokesh Vutla clocks = <&k3_clks 279 2>; 334d361ed88SLokesh Vutla clock-names = "fclk"; 335d361ed88SLokesh Vutla }; 336d361ed88SLokesh Vutla 337d361ed88SLokesh Vutla main_uart3: serial@2830000 { 338d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 339d361ed88SLokesh Vutla reg = <0x00 0x02830000 0x00 0x100>; 340d361ed88SLokesh Vutla interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 341d361ed88SLokesh Vutla clock-frequency = <48000000>; 342d361ed88SLokesh Vutla current-speed = <115200>; 343d361ed88SLokesh Vutla power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 344d361ed88SLokesh Vutla clocks = <&k3_clks 280 2>; 345d361ed88SLokesh Vutla clock-names = "fclk"; 346d361ed88SLokesh Vutla }; 347d361ed88SLokesh Vutla 348d361ed88SLokesh Vutla main_uart4: serial@2840000 { 349d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 350d361ed88SLokesh Vutla reg = <0x00 0x02840000 0x00 0x100>; 351d361ed88SLokesh Vutla interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 352d361ed88SLokesh Vutla clock-frequency = <48000000>; 353d361ed88SLokesh Vutla current-speed = <115200>; 354d361ed88SLokesh Vutla power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 355d361ed88SLokesh Vutla clocks = <&k3_clks 281 2>; 356d361ed88SLokesh Vutla clock-names = "fclk"; 357d361ed88SLokesh Vutla }; 358d361ed88SLokesh Vutla 359d361ed88SLokesh Vutla main_uart5: serial@2850000 { 360d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 361d361ed88SLokesh Vutla reg = <0x00 0x02850000 0x00 0x100>; 362d361ed88SLokesh Vutla interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 363d361ed88SLokesh Vutla clock-frequency = <48000000>; 364d361ed88SLokesh Vutla current-speed = <115200>; 365d361ed88SLokesh Vutla power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 366d361ed88SLokesh Vutla clocks = <&k3_clks 282 2>; 367d361ed88SLokesh Vutla clock-names = "fclk"; 368d361ed88SLokesh Vutla }; 369d361ed88SLokesh Vutla 370d361ed88SLokesh Vutla main_uart6: serial@2860000 { 371d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 372d361ed88SLokesh Vutla reg = <0x00 0x02860000 0x00 0x100>; 373d361ed88SLokesh Vutla interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 374d361ed88SLokesh Vutla clock-frequency = <48000000>; 375d361ed88SLokesh Vutla current-speed = <115200>; 376d361ed88SLokesh Vutla power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 377d361ed88SLokesh Vutla clocks = <&k3_clks 283 2>; 378d361ed88SLokesh Vutla clock-names = "fclk"; 379d361ed88SLokesh Vutla }; 380d361ed88SLokesh Vutla 381d361ed88SLokesh Vutla main_uart7: serial@2870000 { 382d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 383d361ed88SLokesh Vutla reg = <0x00 0x02870000 0x00 0x100>; 384d361ed88SLokesh Vutla interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 385d361ed88SLokesh Vutla clock-frequency = <48000000>; 386d361ed88SLokesh Vutla current-speed = <115200>; 387d361ed88SLokesh Vutla power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 388d361ed88SLokesh Vutla clocks = <&k3_clks 284 2>; 389d361ed88SLokesh Vutla clock-names = "fclk"; 390d361ed88SLokesh Vutla }; 391d361ed88SLokesh Vutla 392d361ed88SLokesh Vutla main_uart8: serial@2880000 { 393d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 394d361ed88SLokesh Vutla reg = <0x00 0x02880000 0x00 0x100>; 395d361ed88SLokesh Vutla interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 396d361ed88SLokesh Vutla clock-frequency = <48000000>; 397d361ed88SLokesh Vutla current-speed = <115200>; 398d361ed88SLokesh Vutla power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 399d361ed88SLokesh Vutla clocks = <&k3_clks 285 2>; 400d361ed88SLokesh Vutla clock-names = "fclk"; 401d361ed88SLokesh Vutla }; 402d361ed88SLokesh Vutla 403d361ed88SLokesh Vutla main_uart9: serial@2890000 { 404d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 405d361ed88SLokesh Vutla reg = <0x00 0x02890000 0x00 0x100>; 406d361ed88SLokesh Vutla interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 407d361ed88SLokesh Vutla clock-frequency = <48000000>; 408d361ed88SLokesh Vutla current-speed = <115200>; 409d361ed88SLokesh Vutla power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 410d361ed88SLokesh Vutla clocks = <&k3_clks 286 2>; 411d361ed88SLokesh Vutla clock-names = "fclk"; 412d361ed88SLokesh Vutla }; 41303bfeb52SVignesh Raghavendra 41403bfeb52SVignesh Raghavendra main_i2c0: i2c@2000000 { 41503bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 41603bfeb52SVignesh Raghavendra reg = <0x00 0x2000000 0x00 0x100>; 41703bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 41803bfeb52SVignesh Raghavendra #address-cells = <1>; 41903bfeb52SVignesh Raghavendra #size-cells = <0>; 42003bfeb52SVignesh Raghavendra clock-names = "fck"; 42103bfeb52SVignesh Raghavendra clocks = <&k3_clks 187 1>; 42203bfeb52SVignesh Raghavendra power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 42303bfeb52SVignesh Raghavendra }; 42403bfeb52SVignesh Raghavendra 42503bfeb52SVignesh Raghavendra main_i2c1: i2c@2010000 { 42603bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 42703bfeb52SVignesh Raghavendra reg = <0x00 0x2010000 0x00 0x100>; 42803bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 42903bfeb52SVignesh Raghavendra #address-cells = <1>; 43003bfeb52SVignesh Raghavendra #size-cells = <0>; 43103bfeb52SVignesh Raghavendra clock-names = "fck"; 43203bfeb52SVignesh Raghavendra clocks = <&k3_clks 188 1>; 43303bfeb52SVignesh Raghavendra power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 43403bfeb52SVignesh Raghavendra }; 43503bfeb52SVignesh Raghavendra 43603bfeb52SVignesh Raghavendra main_i2c2: i2c@2020000 { 43703bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 43803bfeb52SVignesh Raghavendra reg = <0x00 0x2020000 0x00 0x100>; 43903bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 44003bfeb52SVignesh Raghavendra #address-cells = <1>; 44103bfeb52SVignesh Raghavendra #size-cells = <0>; 44203bfeb52SVignesh Raghavendra clock-names = "fck"; 44303bfeb52SVignesh Raghavendra clocks = <&k3_clks 189 1>; 44403bfeb52SVignesh Raghavendra power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 44503bfeb52SVignesh Raghavendra }; 44603bfeb52SVignesh Raghavendra 44703bfeb52SVignesh Raghavendra main_i2c3: i2c@2030000 { 44803bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 44903bfeb52SVignesh Raghavendra reg = <0x00 0x2030000 0x00 0x100>; 45003bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 45103bfeb52SVignesh Raghavendra #address-cells = <1>; 45203bfeb52SVignesh Raghavendra #size-cells = <0>; 45303bfeb52SVignesh Raghavendra clock-names = "fck"; 45403bfeb52SVignesh Raghavendra clocks = <&k3_clks 190 1>; 45503bfeb52SVignesh Raghavendra power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 45603bfeb52SVignesh Raghavendra }; 45703bfeb52SVignesh Raghavendra 45803bfeb52SVignesh Raghavendra main_i2c4: i2c@2040000 { 45903bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 46003bfeb52SVignesh Raghavendra reg = <0x00 0x2040000 0x00 0x100>; 46103bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 46203bfeb52SVignesh Raghavendra #address-cells = <1>; 46303bfeb52SVignesh Raghavendra #size-cells = <0>; 46403bfeb52SVignesh Raghavendra clock-names = "fck"; 46503bfeb52SVignesh Raghavendra clocks = <&k3_clks 191 1>; 46603bfeb52SVignesh Raghavendra power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 46703bfeb52SVignesh Raghavendra }; 46803bfeb52SVignesh Raghavendra 46903bfeb52SVignesh Raghavendra main_i2c5: i2c@2050000 { 47003bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 47103bfeb52SVignesh Raghavendra reg = <0x00 0x2050000 0x00 0x100>; 47203bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 47303bfeb52SVignesh Raghavendra #address-cells = <1>; 47403bfeb52SVignesh Raghavendra #size-cells = <0>; 47503bfeb52SVignesh Raghavendra clock-names = "fck"; 47603bfeb52SVignesh Raghavendra clocks = <&k3_clks 192 1>; 47703bfeb52SVignesh Raghavendra power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 47803bfeb52SVignesh Raghavendra }; 47903bfeb52SVignesh Raghavendra 48003bfeb52SVignesh Raghavendra main_i2c6: i2c@2060000 { 48103bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 48203bfeb52SVignesh Raghavendra reg = <0x00 0x2060000 0x00 0x100>; 48303bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 48403bfeb52SVignesh Raghavendra #address-cells = <1>; 48503bfeb52SVignesh Raghavendra #size-cells = <0>; 48603bfeb52SVignesh Raghavendra clock-names = "fck"; 48703bfeb52SVignesh Raghavendra clocks = <&k3_clks 193 1>; 48803bfeb52SVignesh Raghavendra power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 48903bfeb52SVignesh Raghavendra }; 4907cd03dc7SFaiz Abbas 4917cd03dc7SFaiz Abbas main_sdhci0: mmc@4f80000 { 4927cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 4937cd03dc7SFaiz Abbas reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 4947cd03dc7SFaiz Abbas interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 4957cd03dc7SFaiz Abbas power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 4960cf73209SGrygorii Strashko clock-names = "clk_ahb", "clk_xin"; 4970cf73209SGrygorii Strashko clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 4987cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 4997cd03dc7SFaiz Abbas ti,otap-del-sel-mmc-hs = <0x0>; 5007cd03dc7SFaiz Abbas ti,otap-del-sel-ddr52 = <0x6>; 5017cd03dc7SFaiz Abbas ti,otap-del-sel-hs200 = <0x8>; 50294374990SAswath Govindraju ti,otap-del-sel-hs400 = <0x5>; 50394374990SAswath Govindraju ti,itap-del-sel-legacy = <0x10>; 50494374990SAswath Govindraju ti,itap-del-sel-mmc-hs = <0xa>; 5057cd03dc7SFaiz Abbas ti,strobe-sel = <0x77>; 50694374990SAswath Govindraju ti,clkbuf-sel = <0x7>; 5077cd03dc7SFaiz Abbas ti,trm-icp = <0x8>; 5087cd03dc7SFaiz Abbas bus-width = <8>; 5097cd03dc7SFaiz Abbas mmc-ddr-1_8v; 51094374990SAswath Govindraju mmc-hs200-1_8v; 51194374990SAswath Govindraju mmc-hs400-1_8v; 5127cd03dc7SFaiz Abbas dma-coherent; 5137cd03dc7SFaiz Abbas }; 5147cd03dc7SFaiz Abbas 5157cd03dc7SFaiz Abbas main_sdhci1: mmc@4fb0000 { 5167cd03dc7SFaiz Abbas compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 5177cd03dc7SFaiz Abbas reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 5187cd03dc7SFaiz Abbas interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 5197cd03dc7SFaiz Abbas power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 5200cf73209SGrygorii Strashko clock-names = "clk_ahb", "clk_xin"; 5210cf73209SGrygorii Strashko clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 5227cd03dc7SFaiz Abbas ti,otap-del-sel-legacy = <0x0>; 5237cd03dc7SFaiz Abbas ti,otap-del-sel-sd-hs = <0x0>; 5247cd03dc7SFaiz Abbas ti,otap-del-sel-sdr12 = <0xf>; 5257cd03dc7SFaiz Abbas ti,otap-del-sel-sdr25 = <0xf>; 5267cd03dc7SFaiz Abbas ti,otap-del-sel-sdr50 = <0xc>; 5277cd03dc7SFaiz Abbas ti,otap-del-sel-sdr104 = <0x5>; 5287cd03dc7SFaiz Abbas ti,otap-del-sel-ddr50 = <0xc>; 52994374990SAswath Govindraju ti,itap-del-sel-legacy = <0x0>; 53094374990SAswath Govindraju ti,itap-del-sel-sd-hs = <0x0>; 53194374990SAswath Govindraju ti,itap-del-sel-sdr12 = <0x0>; 53294374990SAswath Govindraju ti,itap-del-sel-sdr25 = <0x0>; 53394374990SAswath Govindraju ti,clkbuf-sel = <0x7>; 53494374990SAswath Govindraju ti,trm-icp = <0x8>; 5357cd03dc7SFaiz Abbas dma-coherent; 5367cd03dc7SFaiz Abbas }; 5376197d713SRoger Quadros 5384c1b22a9SKishon Vijay Abraham I serdes_wiz0: wiz@5060000 { 5394c1b22a9SKishon Vijay Abraham I compatible = "ti,j721e-wiz-10g"; 5404c1b22a9SKishon Vijay Abraham I #address-cells = <1>; 5414c1b22a9SKishon Vijay Abraham I #size-cells = <1>; 5424c1b22a9SKishon Vijay Abraham I power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 5434c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 5444c1b22a9SKishon Vijay Abraham I clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 5454c1b22a9SKishon Vijay Abraham I num-lanes = <4>; 5464c1b22a9SKishon Vijay Abraham I #reset-cells = <1>; 5474c1b22a9SKishon Vijay Abraham I ranges = <0x5060000 0x0 0x5060000 0x10000>; 5484c1b22a9SKishon Vijay Abraham I 5494c1b22a9SKishon Vijay Abraham I assigned-clocks = <&k3_clks 292 85>; 5504c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 89>; 5514c1b22a9SKishon Vijay Abraham I 5524c1b22a9SKishon Vijay Abraham I wiz0_pll0_refclk: pll0-refclk { 5534c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 5544c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_pll0_refclk"; 5554c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 5564c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_pll0_refclk>; 5574c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 5584c1b22a9SKishon Vijay Abraham I }; 5594c1b22a9SKishon Vijay Abraham I 5604c1b22a9SKishon Vijay Abraham I wiz0_pll1_refclk: pll1-refclk { 5614c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 5624c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_pll1_refclk"; 5634c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 5644c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_pll1_refclk>; 5654c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 5664c1b22a9SKishon Vijay Abraham I }; 5674c1b22a9SKishon Vijay Abraham I 5684c1b22a9SKishon Vijay Abraham I wiz0_refclk_dig: refclk-dig { 5694c1b22a9SKishon Vijay Abraham I clocks = <&k3_clks 292 85>, <&serdes_refclk>; 5704c1b22a9SKishon Vijay Abraham I clock-output-names = "wiz0_refclk_dig"; 5714c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 5724c1b22a9SKishon Vijay Abraham I assigned-clocks = <&wiz0_refclk_dig>; 5734c1b22a9SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 85>; 5744c1b22a9SKishon Vijay Abraham I }; 5754c1b22a9SKishon Vijay Abraham I 5764c1b22a9SKishon Vijay Abraham I wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 5774c1b22a9SKishon Vijay Abraham I clocks = <&wiz0_refclk_dig>; 5784c1b22a9SKishon Vijay Abraham I #clock-cells = <0>; 5794c1b22a9SKishon Vijay Abraham I }; 5804c1b22a9SKishon Vijay Abraham I 5814c1b22a9SKishon Vijay Abraham I serdes0: serdes@5060000 { 5824c1b22a9SKishon Vijay Abraham I compatible = "ti,j721e-serdes-10g"; 5834c1b22a9SKishon Vijay Abraham I reg = <0x05060000 0x00010000>; 5844c1b22a9SKishon Vijay Abraham I reg-names = "torrent_phy"; 5854c1b22a9SKishon Vijay Abraham I resets = <&serdes_wiz0 0>; 5864c1b22a9SKishon Vijay Abraham I reset-names = "torrent_reset"; 5874c1b22a9SKishon Vijay Abraham I clocks = <&wiz0_pll0_refclk>; 5884c1b22a9SKishon Vijay Abraham I clock-names = "refclk"; 5894c1b22a9SKishon Vijay Abraham I #address-cells = <1>; 5904c1b22a9SKishon Vijay Abraham I #size-cells = <0>; 5914c1b22a9SKishon Vijay Abraham I }; 5924c1b22a9SKishon Vijay Abraham I }; 5934c1b22a9SKishon Vijay Abraham I 5943276d9f5SKishon Vijay Abraham I pcie1_rc: pcie@2910000 { 5953276d9f5SKishon Vijay Abraham I compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 5963276d9f5SKishon Vijay Abraham I reg = <0x00 0x02910000 0x00 0x1000>, 5973276d9f5SKishon Vijay Abraham I <0x00 0x02917000 0x00 0x400>, 5983276d9f5SKishon Vijay Abraham I <0x00 0x0d800000 0x00 0x00800000>, 5993276d9f5SKishon Vijay Abraham I <0x00 0x18000000 0x00 0x00001000>; 6003276d9f5SKishon Vijay Abraham I reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 6013276d9f5SKishon Vijay Abraham I interrupt-names = "link_state"; 6023276d9f5SKishon Vijay Abraham I interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 6033276d9f5SKishon Vijay Abraham I device_type = "pci"; 6043276d9f5SKishon Vijay Abraham I ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 6053276d9f5SKishon Vijay Abraham I max-link-speed = <3>; 6063276d9f5SKishon Vijay Abraham I num-lanes = <4>; 6073276d9f5SKishon Vijay Abraham I power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 6083276d9f5SKishon Vijay Abraham I clocks = <&k3_clks 240 6>; 6093276d9f5SKishon Vijay Abraham I clock-names = "fck"; 6103276d9f5SKishon Vijay Abraham I #address-cells = <3>; 6113276d9f5SKishon Vijay Abraham I #size-cells = <2>; 6128bb84292SKishon Vijay Abraham I bus-range = <0x0 0xff>; 6133276d9f5SKishon Vijay Abraham I cdns,no-bar-match-nbits = <64>; 6140d553792SKishon Vijay Abraham I vendor-id = <0x104c>; 6150d553792SKishon Vijay Abraham I device-id = <0xb00f>; 6163276d9f5SKishon Vijay Abraham I msi-map = <0x0 &gic_its 0x0 0x10000>; 6173276d9f5SKishon Vijay Abraham I dma-coherent; 6183276d9f5SKishon Vijay Abraham I ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 6193276d9f5SKishon Vijay Abraham I <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 6203276d9f5SKishon Vijay Abraham I dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 6213276d9f5SKishon Vijay Abraham I }; 6223276d9f5SKishon Vijay Abraham I 6233276d9f5SKishon Vijay Abraham I pcie1_ep: pcie-ep@2910000 { 6243276d9f5SKishon Vijay Abraham I compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 6253276d9f5SKishon Vijay Abraham I reg = <0x00 0x02910000 0x00 0x1000>, 6263276d9f5SKishon Vijay Abraham I <0x00 0x02917000 0x00 0x400>, 6273276d9f5SKishon Vijay Abraham I <0x00 0x0d800000 0x00 0x00800000>, 6283276d9f5SKishon Vijay Abraham I <0x00 0x18000000 0x00 0x08000000>; 6293276d9f5SKishon Vijay Abraham I reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 6303276d9f5SKishon Vijay Abraham I interrupt-names = "link_state"; 6313276d9f5SKishon Vijay Abraham I interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 6323276d9f5SKishon Vijay Abraham I ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 6333276d9f5SKishon Vijay Abraham I max-link-speed = <3>; 6343276d9f5SKishon Vijay Abraham I num-lanes = <4>; 6353276d9f5SKishon Vijay Abraham I power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 6363276d9f5SKishon Vijay Abraham I clocks = <&k3_clks 240 6>; 6373276d9f5SKishon Vijay Abraham I clock-names = "fck"; 6383276d9f5SKishon Vijay Abraham I max-functions = /bits/ 8 <6>; 639b6021ba0SKishon Vijay Abraham I max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 6403276d9f5SKishon Vijay Abraham I dma-coherent; 6413276d9f5SKishon Vijay Abraham I }; 6423276d9f5SKishon Vijay Abraham I 6436197d713SRoger Quadros usbss0: cdns-usb@4104000 { 6446197d713SRoger Quadros compatible = "ti,j721e-usb"; 6456197d713SRoger Quadros reg = <0x00 0x4104000 0x00 0x100>; 6466197d713SRoger Quadros dma-coherent; 6476197d713SRoger Quadros power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 6486197d713SRoger Quadros clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 6496197d713SRoger Quadros clock-names = "ref", "lpm"; 6506197d713SRoger Quadros assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 6516197d713SRoger Quadros assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 6526197d713SRoger Quadros #address-cells = <2>; 6536197d713SRoger Quadros #size-cells = <2>; 6546197d713SRoger Quadros ranges; 6556197d713SRoger Quadros 6566197d713SRoger Quadros usb0: usb@6000000 { 6576197d713SRoger Quadros compatible = "cdns,usb3"; 6586197d713SRoger Quadros reg = <0x00 0x6000000 0x00 0x10000>, 6596197d713SRoger Quadros <0x00 0x6010000 0x00 0x10000>, 6606197d713SRoger Quadros <0x00 0x6020000 0x00 0x10000>; 6616197d713SRoger Quadros reg-names = "otg", "xhci", "dev"; 6626197d713SRoger Quadros interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 6636197d713SRoger Quadros <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 6646197d713SRoger Quadros <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 6656197d713SRoger Quadros interrupt-names = "host", 6666197d713SRoger Quadros "peripheral", 6676197d713SRoger Quadros "otg"; 6686197d713SRoger Quadros maximum-speed = "super-speed"; 6696197d713SRoger Quadros dr_mode = "otg"; 670a2894d85SRoger Quadros cdns,phyrst-a-enable; 6716197d713SRoger Quadros }; 6726197d713SRoger Quadros }; 673eb6f3655SSuman Anna 674e0b2e6afSFaiz Abbas main_gpio0: gpio@600000 { 675e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 676e0b2e6afSFaiz Abbas reg = <0x00 0x00600000 0x00 0x100>; 677e0b2e6afSFaiz Abbas gpio-controller; 678e0b2e6afSFaiz Abbas #gpio-cells = <2>; 679e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 680e0b2e6afSFaiz Abbas interrupts = <145>, <146>, <147>, <148>, 681e0b2e6afSFaiz Abbas <149>; 682e0b2e6afSFaiz Abbas interrupt-controller; 683e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 684e0b2e6afSFaiz Abbas ti,ngpio = <69>; 685e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 686e0b2e6afSFaiz Abbas power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 687e0b2e6afSFaiz Abbas clocks = <&k3_clks 105 0>; 688e0b2e6afSFaiz Abbas clock-names = "gpio"; 689e0b2e6afSFaiz Abbas }; 690e0b2e6afSFaiz Abbas 691e0b2e6afSFaiz Abbas main_gpio2: gpio@610000 { 692e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 693e0b2e6afSFaiz Abbas reg = <0x00 0x00610000 0x00 0x100>; 694e0b2e6afSFaiz Abbas gpio-controller; 695e0b2e6afSFaiz Abbas #gpio-cells = <2>; 696e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 697e0b2e6afSFaiz Abbas interrupts = <154>, <155>, <156>, <157>, 698e0b2e6afSFaiz Abbas <158>; 699e0b2e6afSFaiz Abbas interrupt-controller; 700e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 701e0b2e6afSFaiz Abbas ti,ngpio = <69>; 702e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 703e0b2e6afSFaiz Abbas power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 704e0b2e6afSFaiz Abbas clocks = <&k3_clks 107 0>; 705e0b2e6afSFaiz Abbas clock-names = "gpio"; 706e0b2e6afSFaiz Abbas }; 707e0b2e6afSFaiz Abbas 708e0b2e6afSFaiz Abbas main_gpio4: gpio@620000 { 709e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 710e0b2e6afSFaiz Abbas reg = <0x00 0x00620000 0x00 0x100>; 711e0b2e6afSFaiz Abbas gpio-controller; 712e0b2e6afSFaiz Abbas #gpio-cells = <2>; 713e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 714e0b2e6afSFaiz Abbas interrupts = <163>, <164>, <165>, <166>, 715e0b2e6afSFaiz Abbas <167>; 716e0b2e6afSFaiz Abbas interrupt-controller; 717e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 718e0b2e6afSFaiz Abbas ti,ngpio = <69>; 719e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 720e0b2e6afSFaiz Abbas power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 721e0b2e6afSFaiz Abbas clocks = <&k3_clks 109 0>; 722e0b2e6afSFaiz Abbas clock-names = "gpio"; 723e0b2e6afSFaiz Abbas }; 724e0b2e6afSFaiz Abbas 725e0b2e6afSFaiz Abbas main_gpio6: gpio@630000 { 726e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 727e0b2e6afSFaiz Abbas reg = <0x00 0x00630000 0x00 0x100>; 728e0b2e6afSFaiz Abbas gpio-controller; 729e0b2e6afSFaiz Abbas #gpio-cells = <2>; 730e0b2e6afSFaiz Abbas interrupt-parent = <&main_gpio_intr>; 731e0b2e6afSFaiz Abbas interrupts = <172>, <173>, <174>, <175>, 732e0b2e6afSFaiz Abbas <176>; 733e0b2e6afSFaiz Abbas interrupt-controller; 734e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 735e0b2e6afSFaiz Abbas ti,ngpio = <69>; 736e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 737e0b2e6afSFaiz Abbas power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 738e0b2e6afSFaiz Abbas clocks = <&k3_clks 111 0>; 739e0b2e6afSFaiz Abbas clock-names = "gpio"; 740e0b2e6afSFaiz Abbas }; 741e0b2e6afSFaiz Abbas 742*6038f117SGowtham Tammana watchdog0: watchdog@2200000 { 743*6038f117SGowtham Tammana compatible = "ti,j7-rti-wdt"; 744*6038f117SGowtham Tammana reg = <0x0 0x2200000 0x0 0x100>; 745*6038f117SGowtham Tammana clocks = <&k3_clks 252 1>; 746*6038f117SGowtham Tammana power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 747*6038f117SGowtham Tammana assigned-clocks = <&k3_clks 252 1>; 748*6038f117SGowtham Tammana assigned-clock-parents = <&k3_clks 252 5>; 749*6038f117SGowtham Tammana }; 750*6038f117SGowtham Tammana 751*6038f117SGowtham Tammana watchdog1: watchdog@2210000 { 752*6038f117SGowtham Tammana compatible = "ti,j7-rti-wdt"; 753*6038f117SGowtham Tammana reg = <0x0 0x2210000 0x0 0x100>; 754*6038f117SGowtham Tammana clocks = <&k3_clks 253 1>; 755*6038f117SGowtham Tammana power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 756*6038f117SGowtham Tammana assigned-clocks = <&k3_clks 253 1>; 757*6038f117SGowtham Tammana assigned-clock-parents = <&k3_clks 253 5>; 758*6038f117SGowtham Tammana }; 759*6038f117SGowtham Tammana 760eb6f3655SSuman Anna main_r5fss0: r5fss@5c00000 { 761eb6f3655SSuman Anna compatible = "ti,j7200-r5fss"; 762eb6f3655SSuman Anna ti,cluster-mode = <1>; 763eb6f3655SSuman Anna #address-cells = <1>; 764eb6f3655SSuman Anna #size-cells = <1>; 765eb6f3655SSuman Anna ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 766eb6f3655SSuman Anna <0x5d00000 0x00 0x5d00000 0x20000>; 767eb6f3655SSuman Anna power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 768eb6f3655SSuman Anna 769eb6f3655SSuman Anna main_r5fss0_core0: r5f@5c00000 { 770eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 771eb6f3655SSuman Anna reg = <0x5c00000 0x00010000>, 772eb6f3655SSuman Anna <0x5c10000 0x00010000>; 773eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 774eb6f3655SSuman Anna ti,sci = <&dmsc>; 775eb6f3655SSuman Anna ti,sci-dev-id = <245>; 776eb6f3655SSuman Anna ti,sci-proc-ids = <0x06 0xff>; 777eb6f3655SSuman Anna resets = <&k3_reset 245 1>; 778eb6f3655SSuman Anna firmware-name = "j7200-main-r5f0_0-fw"; 779eb6f3655SSuman Anna ti,atcm-enable = <1>; 780eb6f3655SSuman Anna ti,btcm-enable = <1>; 781eb6f3655SSuman Anna ti,loczrama = <1>; 782eb6f3655SSuman Anna }; 783eb6f3655SSuman Anna 784eb6f3655SSuman Anna main_r5fss0_core1: r5f@5d00000 { 785eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 786eb6f3655SSuman Anna reg = <0x5d00000 0x00008000>, 787eb6f3655SSuman Anna <0x5d10000 0x00008000>; 788eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 789eb6f3655SSuman Anna ti,sci = <&dmsc>; 790eb6f3655SSuman Anna ti,sci-dev-id = <246>; 791eb6f3655SSuman Anna ti,sci-proc-ids = <0x07 0xff>; 792eb6f3655SSuman Anna resets = <&k3_reset 246 1>; 793eb6f3655SSuman Anna firmware-name = "j7200-main-r5f0_1-fw"; 794eb6f3655SSuman Anna ti,atcm-enable = <1>; 795eb6f3655SSuman Anna ti,btcm-enable = <1>; 796eb6f3655SSuman Anna ti,loczrama = <1>; 797eb6f3655SSuman Anna }; 798eb6f3655SSuman Anna }; 799d361ed88SLokesh Vutla}; 800