1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g057-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g057-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 96>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g057-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g057-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 xspi: spi@11030000 { 284 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 285 reg = <0 0x11030000 0 0x10000>, 286 <0 0x20000000 0 0x10000000>; 287 reg-names = "regs", "dirmap"; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 290 interrupt-names = "pulse", "err_pulse"; 291 clocks = <&cpg CPG_MOD 0x9f>, 292 <&cpg CPG_MOD 0xa0>, 293 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 294 <&cpg CPG_MOD 0xa1>; 295 clock-names = "ahb", "axi", "spi", "spix2"; 296 resets = <&cpg 0xa3>, <&cpg 0xa4>; 297 reset-names = "hresetn", "aresetn"; 298 power-domains = <&cpg>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 dmac0: dma-controller@11400000 { 305 compatible = "renesas,r9a09g057-dmac"; 306 reg = <0 0x11400000 0 0x10000>; 307 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 324 interrupt-names = "error", 325 "ch0", "ch1", "ch2", "ch3", 326 "ch4", "ch5", "ch6", "ch7", 327 "ch8", "ch9", "ch10", "ch11", 328 "ch12", "ch13", "ch14", "ch15"; 329 clocks = <&cpg CPG_MOD 0x0>; 330 power-domains = <&cpg>; 331 resets = <&cpg 0x31>; 332 #dma-cells = <1>; 333 dma-channels = <16>; 334 renesas,icu = <&icu 4>; 335 }; 336 337 dmac1: dma-controller@14830000 { 338 compatible = "renesas,r9a09g057-dmac"; 339 reg = <0 0x14830000 0 0x10000>; 340 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 341 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 342 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 357 interrupt-names = "error", 358 "ch0", "ch1", "ch2", "ch3", 359 "ch4", "ch5", "ch6", "ch7", 360 "ch8", "ch9", "ch10", "ch11", 361 "ch12", "ch13", "ch14", "ch15"; 362 clocks = <&cpg CPG_MOD 0x1>; 363 power-domains = <&cpg>; 364 resets = <&cpg 0x32>; 365 #dma-cells = <1>; 366 dma-channels = <16>; 367 renesas,icu = <&icu 0>; 368 }; 369 370 dmac2: dma-controller@14840000 { 371 compatible = "renesas,r9a09g057-dmac"; 372 reg = <0 0x14840000 0 0x10000>; 373 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 374 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 375 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 390 interrupt-names = "error", 391 "ch0", "ch1", "ch2", "ch3", 392 "ch4", "ch5", "ch6", "ch7", 393 "ch8", "ch9", "ch10", "ch11", 394 "ch12", "ch13", "ch14", "ch15"; 395 clocks = <&cpg CPG_MOD 0x2>; 396 power-domains = <&cpg>; 397 resets = <&cpg 0x33>; 398 #dma-cells = <1>; 399 dma-channels = <16>; 400 renesas,icu = <&icu 1>; 401 }; 402 403 dmac3: dma-controller@12000000 { 404 compatible = "renesas,r9a09g057-dmac"; 405 reg = <0 0x12000000 0 0x10000>; 406 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 407 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 408 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 423 interrupt-names = "error", 424 "ch0", "ch1", "ch2", "ch3", 425 "ch4", "ch5", "ch6", "ch7", 426 "ch8", "ch9", "ch10", "ch11", 427 "ch12", "ch13", "ch14", "ch15"; 428 clocks = <&cpg CPG_MOD 0x3>; 429 power-domains = <&cpg>; 430 resets = <&cpg 0x34>; 431 #dma-cells = <1>; 432 dma-channels = <16>; 433 renesas,icu = <&icu 2>; 434 }; 435 436 dmac4: dma-controller@12010000 { 437 compatible = "renesas,r9a09g057-dmac"; 438 reg = <0 0x12010000 0 0x10000>; 439 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 440 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 456 interrupt-names = "error", 457 "ch0", "ch1", "ch2", "ch3", 458 "ch4", "ch5", "ch6", "ch7", 459 "ch8", "ch9", "ch10", "ch11", 460 "ch12", "ch13", "ch14", "ch15"; 461 clocks = <&cpg CPG_MOD 0x4>; 462 power-domains = <&cpg>; 463 resets = <&cpg 0x35>; 464 #dma-cells = <1>; 465 dma-channels = <16>; 466 renesas,icu = <&icu 3>; 467 }; 468 469 ostm0: timer@11800000 { 470 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 471 reg = <0x0 0x11800000 0x0 0x1000>; 472 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 473 clocks = <&cpg CPG_MOD 0x43>; 474 resets = <&cpg 0x6d>; 475 power-domains = <&cpg>; 476 status = "disabled"; 477 }; 478 479 ostm1: timer@11801000 { 480 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 481 reg = <0x0 0x11801000 0x0 0x1000>; 482 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 483 clocks = <&cpg CPG_MOD 0x44>; 484 resets = <&cpg 0x6e>; 485 power-domains = <&cpg>; 486 status = "disabled"; 487 }; 488 489 ostm2: timer@14000000 { 490 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 491 reg = <0x0 0x14000000 0x0 0x1000>; 492 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 493 clocks = <&cpg CPG_MOD 0x45>; 494 resets = <&cpg 0x6f>; 495 power-domains = <&cpg>; 496 status = "disabled"; 497 }; 498 499 ostm3: timer@14001000 { 500 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 501 reg = <0x0 0x14001000 0x0 0x1000>; 502 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 503 clocks = <&cpg CPG_MOD 0x46>; 504 resets = <&cpg 0x70>; 505 power-domains = <&cpg>; 506 status = "disabled"; 507 }; 508 509 ostm4: timer@12c00000 { 510 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 511 reg = <0x0 0x12c00000 0x0 0x1000>; 512 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 513 clocks = <&cpg CPG_MOD 0x47>; 514 resets = <&cpg 0x71>; 515 power-domains = <&cpg>; 516 status = "disabled"; 517 }; 518 519 ostm5: timer@12c01000 { 520 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 521 reg = <0x0 0x12c01000 0x0 0x1000>; 522 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 523 clocks = <&cpg CPG_MOD 0x48>; 524 resets = <&cpg 0x72>; 525 power-domains = <&cpg>; 526 status = "disabled"; 527 }; 528 529 ostm6: timer@12c02000 { 530 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 531 reg = <0x0 0x12c02000 0x0 0x1000>; 532 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 533 clocks = <&cpg CPG_MOD 0x49>; 534 resets = <&cpg 0x73>; 535 power-domains = <&cpg>; 536 status = "disabled"; 537 }; 538 539 ostm7: timer@12c03000 { 540 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 541 reg = <0x0 0x12c03000 0x0 0x1000>; 542 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 543 clocks = <&cpg CPG_MOD 0x4a>; 544 resets = <&cpg 0x74>; 545 power-domains = <&cpg>; 546 status = "disabled"; 547 }; 548 549 wdt0: watchdog@11c00400 { 550 compatible = "renesas,r9a09g057-wdt"; 551 reg = <0 0x11c00400 0 0x400>; 552 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 553 clock-names = "pclk", "oscclk"; 554 resets = <&cpg 0x75>; 555 power-domains = <&cpg>; 556 status = "disabled"; 557 }; 558 559 wdt1: watchdog@14400000 { 560 compatible = "renesas,r9a09g057-wdt"; 561 reg = <0 0x14400000 0 0x400>; 562 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 563 clock-names = "pclk", "oscclk"; 564 resets = <&cpg 0x76>; 565 power-domains = <&cpg>; 566 status = "disabled"; 567 }; 568 569 wdt2: watchdog@13000000 { 570 compatible = "renesas,r9a09g057-wdt"; 571 reg = <0 0x13000000 0 0x400>; 572 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 573 clock-names = "pclk", "oscclk"; 574 resets = <&cpg 0x77>; 575 power-domains = <&cpg>; 576 status = "disabled"; 577 }; 578 579 wdt3: watchdog@13000400 { 580 compatible = "renesas,r9a09g057-wdt"; 581 reg = <0 0x13000400 0 0x400>; 582 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 583 clock-names = "pclk", "oscclk"; 584 resets = <&cpg 0x78>; 585 power-domains = <&cpg>; 586 status = "disabled"; 587 }; 588 589 scif: serial@11c01400 { 590 compatible = "renesas,scif-r9a09g057"; 591 reg = <0 0x11c01400 0 0x400>; 592 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 600 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 601 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 602 "tei", "tei-dri", "rxi-edge", "txi-edge"; 603 clocks = <&cpg CPG_MOD 0x8f>; 604 clock-names = "fck"; 605 power-domains = <&cpg>; 606 resets = <&cpg 0x95>; 607 status = "disabled"; 608 }; 609 610 i3c: i3c@12400000 { 611 compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; 612 reg = <0 0x12400000 0 0x10000>; 613 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 614 clock-names = "pclk", "tclk", "pclkrw"; 615 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 619 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 621 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 622 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 623 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 624 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "ierr", "terr", "abort", "resp", 632 "cmd", "ibi", "rx", "tx", "rcv", 633 "st", "sp", "tend", "nack", 634 "al", "tmo", "wu"; 635 resets = <&cpg 0x96>, <&cpg 0x97>; 636 reset-names = "presetn", "tresetn"; 637 power-domains = <&cpg>; 638 #address-cells = <3>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 rspi0: spi@12800000 { 644 compatible = "renesas,r9a09g057-rspi"; 645 reg = <0x0 0x12800000 0x0 0x400>; 646 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 649 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 650 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 651 interrupt-names = "idle", "error", "end", "rx", "tx"; 652 clocks = <&cpg CPG_MOD 0x54>, 653 <&cpg CPG_MOD 0x55>, 654 <&cpg CPG_MOD 0x56>; 655 clock-names = "pclk", "pclk_sfr", "tclk"; 656 resets = <&cpg 0x7b>, <&cpg 0x7c>; 657 reset-names = "presetn", "tresetn"; 658 power-domains = <&cpg>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 status = "disabled"; 662 }; 663 664 rspi1: spi@12800400 { 665 compatible = "renesas,r9a09g057-rspi"; 666 reg = <0x0 0x12800400 0x0 0x400>; 667 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 670 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 671 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 672 interrupt-names = "idle", "error", "end", "rx", "tx"; 673 clocks = <&cpg CPG_MOD 0x57>, 674 <&cpg CPG_MOD 0x58>, 675 <&cpg CPG_MOD 0x59>; 676 clock-names = "pclk", "pclk_sfr", "tclk"; 677 resets = <&cpg 0x7d>, <&cpg 0x7e>; 678 reset-names = "presetn", "tresetn"; 679 power-domains = <&cpg>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disabled"; 683 }; 684 685 rspi2: spi@12800800 { 686 compatible = "renesas,r9a09g057-rspi"; 687 reg = <0x0 0x12800800 0x0 0x400>; 688 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 691 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 692 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 693 interrupt-names = "idle", "error", "end", "rx", "tx"; 694 clocks = <&cpg CPG_MOD 0x5a>, 695 <&cpg CPG_MOD 0x5b>, 696 <&cpg CPG_MOD 0x5c>; 697 clock-names = "pclk", "pclk_sfr", "tclk"; 698 resets = <&cpg 0x7f>, <&cpg 0x80>; 699 reset-names = "presetn", "tresetn"; 700 power-domains = <&cpg>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 status = "disabled"; 704 }; 705 706 i2c0: i2c@14400400 { 707 compatible = "renesas,riic-r9a09g057"; 708 reg = <0 0x14400400 0 0x400>; 709 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 711 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 712 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-names = "tei", "ri", "ti", "spi", "sti", 718 "naki", "ali", "tmoi"; 719 clocks = <&cpg CPG_MOD 0x94>; 720 resets = <&cpg 0x98>; 721 power-domains = <&cpg>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 status = "disabled"; 725 }; 726 727 i2c1: i2c@14400800 { 728 compatible = "renesas,riic-r9a09g057"; 729 reg = <0 0x14400800 0 0x400>; 730 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 732 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 733 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "tei", "ri", "ti", "spi", "sti", 739 "naki", "ali", "tmoi"; 740 clocks = <&cpg CPG_MOD 0x95>; 741 resets = <&cpg 0x99>; 742 power-domains = <&cpg>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 748 i2c2: i2c@14400c00 { 749 compatible = "renesas,riic-r9a09g057"; 750 reg = <0 0x14400c00 0 0x400>; 751 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 753 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 754 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 759 interrupt-names = "tei", "ri", "ti", "spi", "sti", 760 "naki", "ali", "tmoi"; 761 clocks = <&cpg CPG_MOD 0x96>; 762 resets = <&cpg 0x9a>; 763 power-domains = <&cpg>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 i2c3: i2c@14401000 { 770 compatible = "renesas,riic-r9a09g057"; 771 reg = <0 0x14401000 0 0x400>; 772 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 774 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 775 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-names = "tei", "ri", "ti", "spi", "sti", 781 "naki", "ali", "tmoi"; 782 clocks = <&cpg CPG_MOD 0x97>; 783 resets = <&cpg 0x9b>; 784 power-domains = <&cpg>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 i2c4: i2c@14401400 { 791 compatible = "renesas,riic-r9a09g057"; 792 reg = <0 0x14401400 0 0x400>; 793 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 795 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 796 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "tei", "ri", "ti", "spi", "sti", 802 "naki", "ali", "tmoi"; 803 clocks = <&cpg CPG_MOD 0x98>; 804 resets = <&cpg 0x9c>; 805 power-domains = <&cpg>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 i2c5: i2c@14401800 { 812 compatible = "renesas,riic-r9a09g057"; 813 reg = <0 0x14401800 0 0x400>; 814 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 816 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 817 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 822 interrupt-names = "tei", "ri", "ti", "spi", "sti", 823 "naki", "ali", "tmoi"; 824 clocks = <&cpg CPG_MOD 0x99>; 825 resets = <&cpg 0x9d>; 826 power-domains = <&cpg>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 i2c6: i2c@14401c00 { 833 compatible = "renesas,riic-r9a09g057"; 834 reg = <0 0x14401c00 0 0x400>; 835 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 837 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 838 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "tei", "ri", "ti", "spi", "sti", 844 "naki", "ali", "tmoi"; 845 clocks = <&cpg CPG_MOD 0x9a>; 846 resets = <&cpg 0x9e>; 847 power-domains = <&cpg>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 status = "disabled"; 851 }; 852 853 i2c7: i2c@14402000 { 854 compatible = "renesas,riic-r9a09g057"; 855 reg = <0 0x14402000 0 0x400>; 856 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 858 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 859 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "tei", "ri", "ti", "spi", "sti", 865 "naki", "ali", "tmoi"; 866 clocks = <&cpg CPG_MOD 0x9b>; 867 resets = <&cpg 0x9f>; 868 power-domains = <&cpg>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 status = "disabled"; 872 }; 873 874 i2c8: i2c@11c01000 { 875 compatible = "renesas,riic-r9a09g057"; 876 reg = <0 0x11c01000 0 0x400>; 877 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 879 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 880 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "tei", "ri", "ti", "spi", "sti", 886 "naki", "ali", "tmoi"; 887 clocks = <&cpg CPG_MOD 0x93>; 888 resets = <&cpg 0xa0>; 889 power-domains = <&cpg>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 gpu: gpu@14850000 { 896 compatible = "renesas,r9a09g057-mali", 897 "arm,mali-bifrost"; 898 reg = <0x0 0x14850000 0x0 0x10000>; 899 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "job", "mmu", "gpu", "event"; 904 clocks = <&cpg CPG_MOD 0xf0>, 905 <&cpg CPG_MOD 0xf1>, 906 <&cpg CPG_MOD 0xf2>; 907 clock-names = "gpu", "bus", "bus_ace"; 908 power-domains = <&cpg>; 909 resets = <&cpg 0xdd>, 910 <&cpg 0xde>, 911 <&cpg 0xdf>; 912 reset-names = "rst", "axi_rst", "ace_rst"; 913 operating-points-v2 = <&gpu_opp_table>; 914 status = "disabled"; 915 }; 916 917 gic: interrupt-controller@14900000 { 918 compatible = "arm,gic-v3"; 919 reg = <0x0 0x14900000 0 0x20000>, 920 <0x0 0x14940000 0 0x80000>; 921 #interrupt-cells = <3>; 922 #address-cells = <0>; 923 interrupt-controller; 924 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 925 }; 926 927 ohci0: usb@15800000 { 928 compatible = "generic-ohci"; 929 reg = <0 0x15800000 0 0x100>; 930 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 932 resets = <&usb20phyrst>, <&cpg 0xac>; 933 phys = <&usb2_phy0 1>; 934 phy-names = "usb"; 935 power-domains = <&cpg>; 936 status = "disabled"; 937 }; 938 939 ohci1: usb@15810000 { 940 compatible = "generic-ohci"; 941 reg = <0 0x15810000 0 0x100>; 942 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 944 resets = <&usb21phyrst>, <&cpg 0xad>; 945 phys = <&usb2_phy1 1>; 946 phy-names = "usb"; 947 power-domains = <&cpg>; 948 status = "disabled"; 949 }; 950 951 ehci0: usb@15800100 { 952 compatible = "generic-ehci"; 953 reg = <0 0x15800100 0 0x100>; 954 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 956 resets = <&usb20phyrst>, <&cpg 0xac>; 957 phys = <&usb2_phy0 2>; 958 phy-names = "usb"; 959 companion = <&ohci0>; 960 power-domains = <&cpg>; 961 status = "disabled"; 962 }; 963 964 ehci1: usb@15810100 { 965 compatible = "generic-ehci"; 966 reg = <0 0x15810100 0 0x100>; 967 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 969 resets = <&usb21phyrst>, <&cpg 0xad>; 970 phys = <&usb2_phy1 2>; 971 phy-names = "usb"; 972 companion = <&ohci1>; 973 power-domains = <&cpg>; 974 status = "disabled"; 975 }; 976 977 usb2_phy0: usb-phy@15800200 { 978 compatible = "renesas,usb2-phy-r9a09g057"; 979 reg = <0 0x15800200 0 0x700>; 980 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cpg CPG_MOD 0xb3>, 982 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 983 clock-names = "fck", "usb_x1"; 984 resets = <&usb20phyrst>; 985 #phy-cells = <1>; 986 power-domains = <&cpg>; 987 status = "disabled"; 988 }; 989 990 usb2_phy1: usb-phy@15810200 { 991 compatible = "renesas,usb2-phy-r9a09g057"; 992 reg = <0 0x15810200 0 0x700>; 993 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&cpg CPG_MOD 0xb4>, 995 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 996 clock-names = "fck", "usb_x1"; 997 resets = <&usb21phyrst>; 998 #phy-cells = <1>; 999 power-domains = <&cpg>; 1000 status = "disabled"; 1001 }; 1002 1003 hsusb: usb@15820000 { 1004 compatible = "renesas,usbhs-r9a09g057", 1005 "renesas,rzg2l-usbhs"; 1006 reg = <0 0x15820000 0 0x10000>; 1007 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 1008 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 1012 resets = <&usb20phyrst>, 1013 <&cpg 0xae>; 1014 phys = <&usb2_phy0 3>; 1015 phy-names = "usb"; 1016 power-domains = <&cpg>; 1017 status = "disabled"; 1018 }; 1019 1020 usb20phyrst: usb20phy-reset@15830000 { 1021 compatible = "renesas,r9a09g057-usb2phy-reset"; 1022 reg = <0 0x15830000 0 0x10000>; 1023 clocks = <&cpg CPG_MOD 0xb6>; 1024 resets = <&cpg 0xaf>; 1025 power-domains = <&cpg>; 1026 #reset-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 usb21phyrst: usb21phy-reset@15840000 { 1031 compatible = "renesas,r9a09g057-usb2phy-reset"; 1032 reg = <0 0x15840000 0 0x10000>; 1033 clocks = <&cpg CPG_MOD 0xb7>; 1034 resets = <&cpg 0xaf>; 1035 power-domains = <&cpg>; 1036 #reset-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 sdhi0: mmc@15c00000 { 1041 compatible = "renesas,sdhi-r9a09g057"; 1042 reg = <0x0 0x15c00000 0 0x10000>; 1043 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1046 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1047 clock-names = "core", "clkh", "cd", "aclk"; 1048 resets = <&cpg 0xa7>; 1049 power-domains = <&cpg>; 1050 status = "disabled"; 1051 1052 sdhi0_vqmmc: vqmmc-regulator { 1053 regulator-name = "SDHI0-VQMMC"; 1054 regulator-min-microvolt = <1800000>; 1055 regulator-max-microvolt = <3300000>; 1056 status = "disabled"; 1057 }; 1058 }; 1059 1060 sdhi1: mmc@15c10000 { 1061 compatible = "renesas,sdhi-r9a09g057"; 1062 reg = <0x0 0x15c10000 0 0x10000>; 1063 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1066 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1067 clock-names = "core", "clkh", "cd", "aclk"; 1068 resets = <&cpg 0xa8>; 1069 power-domains = <&cpg>; 1070 status = "disabled"; 1071 1072 sdhi1_vqmmc: vqmmc-regulator { 1073 regulator-name = "SDHI1-VQMMC"; 1074 regulator-min-microvolt = <1800000>; 1075 regulator-max-microvolt = <3300000>; 1076 status = "disabled"; 1077 }; 1078 }; 1079 1080 sdhi2: mmc@15c20000 { 1081 compatible = "renesas,sdhi-r9a09g057"; 1082 reg = <0x0 0x15c20000 0 0x10000>; 1083 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1086 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1087 clock-names = "core", "clkh", "cd", "aclk"; 1088 resets = <&cpg 0xa9>; 1089 power-domains = <&cpg>; 1090 status = "disabled"; 1091 1092 sdhi2_vqmmc: vqmmc-regulator { 1093 regulator-name = "SDHI2-VQMMC"; 1094 regulator-min-microvolt = <1800000>; 1095 regulator-max-microvolt = <3300000>; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 eth0: ethernet@15c30000 { 1101 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1102 "snps,dwmac-5.20"; 1103 reg = <0 0x15c30000 0 0x10000>; 1104 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1115 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1116 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1117 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1118 "tx-queue-2", "tx-queue-3"; 1119 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1120 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1121 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1122 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1123 clock-names = "stmmaceth", "pclk", "ptp_ref", 1124 "tx", "rx", "tx-180", "rx-180"; 1125 resets = <&cpg 0xb0>; 1126 power-domains = <&cpg>; 1127 snps,multicast-filter-bins = <256>; 1128 snps,perfect-filter-entries = <128>; 1129 rx-fifo-depth = <8192>; 1130 tx-fifo-depth = <8192>; 1131 snps,fixed-burst; 1132 snps,no-pbl-x8; 1133 snps,force_thresh_dma_mode; 1134 snps,axi-config = <&stmmac_axi_setup>; 1135 snps,mtl-rx-config = <&mtl_rx_setup0>; 1136 snps,mtl-tx-config = <&mtl_tx_setup0>; 1137 snps,txpbl = <32>; 1138 snps,rxpbl = <32>; 1139 status = "disabled"; 1140 1141 mdio0: mdio { 1142 compatible = "snps,dwmac-mdio"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 }; 1146 1147 mtl_rx_setup0: rx-queues-config { 1148 snps,rx-queues-to-use = <4>; 1149 snps,rx-sched-sp; 1150 1151 queue0 { 1152 snps,dcb-algorithm; 1153 snps,priority = <0x1>; 1154 snps,map-to-dma-channel = <0>; 1155 }; 1156 1157 queue1 { 1158 snps,dcb-algorithm; 1159 snps,priority = <0x2>; 1160 snps,map-to-dma-channel = <1>; 1161 }; 1162 1163 queue2 { 1164 snps,dcb-algorithm; 1165 snps,priority = <0x4>; 1166 snps,map-to-dma-channel = <2>; 1167 }; 1168 1169 queue3 { 1170 snps,dcb-algorithm; 1171 snps,priority = <0x8>; 1172 snps,map-to-dma-channel = <3>; 1173 }; 1174 }; 1175 1176 mtl_tx_setup0: tx-queues-config { 1177 snps,tx-queues-to-use = <4>; 1178 1179 queue0 { 1180 snps,dcb-algorithm; 1181 snps,priority = <0x1>; 1182 }; 1183 1184 queue1 { 1185 snps,dcb-algorithm; 1186 snps,priority = <0x2>; 1187 }; 1188 1189 queue2 { 1190 snps,dcb-algorithm; 1191 snps,priority = <0x4>; 1192 }; 1193 1194 queue3 { 1195 snps,dcb-algorithm; 1196 snps,priority = <0x8>; 1197 }; 1198 }; 1199 }; 1200 1201 eth1: ethernet@15c40000 { 1202 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1203 "snps,dwmac-5.20"; 1204 reg = <0 0x15c40000 0 0x10000>; 1205 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1216 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1217 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1218 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1219 "tx-queue-2", "tx-queue-3"; 1220 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1221 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1222 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1223 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1224 clock-names = "stmmaceth", "pclk", "ptp_ref", 1225 "tx", "rx", "tx-180", "rx-180"; 1226 resets = <&cpg 0xb1>; 1227 power-domains = <&cpg>; 1228 snps,multicast-filter-bins = <256>; 1229 snps,perfect-filter-entries = <128>; 1230 rx-fifo-depth = <8192>; 1231 tx-fifo-depth = <8192>; 1232 snps,fixed-burst; 1233 snps,no-pbl-x8; 1234 snps,force_thresh_dma_mode; 1235 snps,axi-config = <&stmmac_axi_setup>; 1236 snps,mtl-rx-config = <&mtl_rx_setup1>; 1237 snps,mtl-tx-config = <&mtl_tx_setup1>; 1238 snps,txpbl = <32>; 1239 snps,rxpbl = <32>; 1240 status = "disabled"; 1241 1242 mdio1: mdio { 1243 compatible = "snps,dwmac-mdio"; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 }; 1247 1248 mtl_rx_setup1: rx-queues-config { 1249 snps,rx-queues-to-use = <4>; 1250 snps,rx-sched-sp; 1251 1252 queue0 { 1253 snps,dcb-algorithm; 1254 snps,priority = <0x1>; 1255 snps,map-to-dma-channel = <0>; 1256 }; 1257 1258 queue1 { 1259 snps,dcb-algorithm; 1260 snps,priority = <0x2>; 1261 snps,map-to-dma-channel = <1>; 1262 }; 1263 1264 queue2 { 1265 snps,dcb-algorithm; 1266 snps,priority = <0x4>; 1267 snps,map-to-dma-channel = <2>; 1268 }; 1269 1270 queue3 { 1271 snps,dcb-algorithm; 1272 snps,priority = <0x8>; 1273 snps,map-to-dma-channel = <3>; 1274 }; 1275 }; 1276 1277 mtl_tx_setup1: tx-queues-config { 1278 snps,tx-queues-to-use = <4>; 1279 1280 queue0 { 1281 snps,dcb-algorithm; 1282 snps,priority = <0x1>; 1283 }; 1284 1285 queue1 { 1286 snps,dcb-algorithm; 1287 snps,priority = <0x2>; 1288 }; 1289 1290 queue2 { 1291 snps,dcb-algorithm; 1292 snps,priority = <0x4>; 1293 }; 1294 1295 queue3 { 1296 snps,dcb-algorithm; 1297 snps,priority = <0x8>; 1298 }; 1299 }; 1300 }; 1301 }; 1302 1303 stmmac_axi_setup: stmmac-axi-config { 1304 snps,lpi_en; 1305 snps,wr_osr_lmt = <0xf>; 1306 snps,rd_osr_lmt = <0xf>; 1307 snps,blen = <16 8 4 0 0 0 0>; 1308 }; 1309 1310 timer { 1311 compatible = "arm,armv8-timer"; 1312 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1313 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1314 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1315 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1316 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1317 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1318 }; 1319}; 1320