1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3L SoC 4 * 5 * Copyright (C) 2026 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a08g046-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a08g046"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci"; 27 }; 28 29 cpu1: cpu@100 { 30 compatible = "arm,cortex-a55"; 31 reg = <0x100>; 32 device_type = "cpu"; 33 next-level-cache = <&L3_CA55>; 34 enable-method = "psci"; 35 }; 36 37 cpu2: cpu@200 { 38 compatible = "arm,cortex-a55"; 39 reg = <0x200>; 40 device_type = "cpu"; 41 next-level-cache = <&L3_CA55>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 reg = <0x300>; 48 device_type = "cpu"; 49 next-level-cache = <&L3_CA55>; 50 enable-method = "psci"; 51 }; 52 53 L3_CA55: cache-controller-0 { 54 compatible = "cache"; 55 cache-unified; 56 cache-size = <0x80000>; 57 cache-level = <3>; 58 }; 59 }; 60 61 eth0_txc_tx_clk: eth0-txc-tx-clk { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 /* This value must be overridden by the board */ 65 clock-frequency = <0>; 66 }; 67 68 eth0_rxc_rx_clk: eth0-rxc-rx-clk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 /* This value must be overridden by the board */ 72 clock-frequency = <0>; 73 }; 74 75 eth1_txc_tx_clk: eth1-txc-tx-clk { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 /* This value must be overridden by the board */ 79 clock-frequency = <0>; 80 }; 81 82 eth1_rxc_rx_clk: eth1-rxc-rx-clk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 /* This value must be overridden by the board */ 86 clock-frequency = <0>; 87 }; 88 89 extal_clk: extal-clk { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 /* This value must be overridden by the board. */ 93 clock-frequency = <0>; 94 }; 95 96 psci { 97 compatible = "arm,psci-1.0", "arm,psci-0.2"; 98 method = "smc"; 99 }; 100 101 soc: soc { 102 compatible = "simple-bus"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 scif0: serial@100ac000 { 108 compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; 109 reg = <0 0x100ac000 0 0x400>; 110 interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "eri", "rxi", "txi", 117 "bri", "dri", "tei"; 118 clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>; 119 clock-names = "fck"; 120 power-domains = <&cpg>; 121 resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>; 122 status = "disabled"; 123 }; 124 125 i2c0: i2c@100ae000 { 126 reg = <0 0x100ae000 0 0x400>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 /* placeholder */ 130 }; 131 132 canfd: can@100c0000 { 133 reg = <0 0x100c0000 0 0x20000>; 134 /* placeholder */ 135 }; 136 137 cpg: clock-controller@11010000 { 138 compatible = "renesas,r9a08g046-cpg"; 139 reg = <0 0x11010000 0 0x10000>; 140 clocks = <&extal_clk>, 141 <ð0_txc_tx_clk>, <ð0_rxc_rx_clk>, 142 <ð1_txc_tx_clk>, <ð1_rxc_rx_clk>; 143 clock-names = "extal", 144 "eth0_txc_tx_clk", "eth0_rxc_rx_clk", 145 "eth1_txc_tx_clk", "eth1_rxc_rx_clk"; 146 #clock-cells = <2>; 147 #reset-cells = <1>; 148 #power-domain-cells = <0>; 149 }; 150 151 sysc: system-controller@11020000 { 152 compatible = "renesas,r9a08g046-sysc"; 153 reg = <0 0x11020000 0 0x10000>; 154 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "lpm_int", "ca55stbydone_int", 159 "cm33stbyr_int", "ca55_deny"; 160 }; 161 162 pinctrl: pinctrl@11030000 { 163 reg = <0 0x11030000 0 0x10000>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 /* placeholder */ 167 }; 168 169 sdhi1: mmc@11c10000 { 170 reg = <0x0 0x11c10000 0 0x10000>; 171 /* placeholder */ 172 }; 173 174 pcie: pcie@11e40000 { 175 reg = <0 0x11e40000 0 0x10000>; 176 ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; 177 device_type = "pci"; 178 #address-cells = <3>; 179 #size-cells = <2>; 180 /* placeholder */ 181 182 pcie_port0: pcie@0,0 { 183 reg = <0x0 0x0 0x0 0x0 0x0>; 184 ranges; 185 device_type = "pci"; 186 #address-cells = <3>; 187 #size-cells = <2>; 188 /* placeholder */ 189 }; 190 }; 191 192 gic: interrupt-controller@12400000 { 193 compatible = "arm,gic-v3"; 194 reg = <0x0 0x12400000 0 0x20000>, 195 <0x0 0x12440000 0 0x80000>; 196 #interrupt-cells = <3>; 197 #address-cells = <0>; 198 interrupt-controller; 199 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 200 }; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 206 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 207 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 208 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 209 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 210 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 211 }; 212}; 213