1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a55"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 power-domains = <&cpu_pd0>; 37 power-domain-names = "psci"; 38 capacity-dmips-mhz = <1024>; 39 dynamic-power-coefficient = <100>; 40 next-level-cache = <&l2_0>; 41 clocks = <&cpufreq_hw 0>; 42 qcom,freq-domain = <&cpufreq_hw 0>; 43 #cooling-cells = <2>; 44 operating-points-v2 = <&cpu0_opp_table>; 45 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 46 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 47 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 48 49 l2_0: l2-cache { 50 compatible = "cache"; 51 cache-level = <2>; 52 cache-unified; 53 next-level-cache = <&l3_0>; 54 }; 55 }; 56 57 cpu1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 power-domains = <&cpu_pd1>; 63 power-domain-names = "psci"; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 next-level-cache = <&l2_100>; 67 clocks = <&cpufreq_hw 0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 71 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 72 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 73 74 l2_100: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 next-level-cache = <&l3_0>; 79 }; 80 }; 81 82 cpu2: cpu@200 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x0 0x200>; 86 enable-method = "psci"; 87 power-domains = <&cpu_pd2>; 88 power-domain-names = "psci"; 89 capacity-dmips-mhz = <1024>; 90 dynamic-power-coefficient = <100>; 91 next-level-cache = <&l2_200>; 92 clocks = <&cpufreq_hw 0>; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 operating-points-v2 = <&cpu0_opp_table>; 95 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 96 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 97 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 98 99 l2_200: l2-cache { 100 compatible = "cache"; 101 cache-level = <2>; 102 cache-unified; 103 next-level-cache = <&l3_0>; 104 }; 105 }; 106 107 cpu3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 power-domains = <&cpu_pd3>; 113 power-domain-names = "psci"; 114 capacity-dmips-mhz = <1024>; 115 dynamic-power-coefficient = <100>; 116 next-level-cache = <&l2_300>; 117 clocks = <&cpufreq_hw 0>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 operating-points-v2 = <&cpu0_opp_table>; 120 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 122 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 123 124 l2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&l3_0>; 129 }; 130 }; 131 132 cpu4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a55"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 power-domains = <&cpu_pd4>; 138 power-domain-names = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <100>; 141 next-level-cache = <&l2_400>; 142 clocks = <&cpufreq_hw 0>; 143 qcom,freq-domain = <&cpufreq_hw 0>; 144 operating-points-v2 = <&cpu0_opp_table>; 145 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 146 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 147 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 148 149 l2_400: l2-cache { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_0>; 154 }; 155 }; 156 157 cpu5: cpu@500 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a55"; 160 reg = <0x0 0x500>; 161 enable-method = "psci"; 162 power-domains = <&cpu_pd5>; 163 power-domain-names = "psci"; 164 capacity-dmips-mhz = <1024>; 165 dynamic-power-coefficient = <100>; 166 next-level-cache = <&l2_500>; 167 clocks = <&cpufreq_hw 0>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 172 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 173 174 l2_500: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 }; 181 182 cpu6: cpu@600 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a76"; 185 reg = <0x0 0x600>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd6>; 188 power-domain-names = "psci"; 189 capacity-dmips-mhz = <1740>; 190 dynamic-power-coefficient = <404>; 191 next-level-cache = <&l2_600>; 192 clocks = <&cpufreq_hw 1>; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 #cooling-cells = <2>; 195 operating-points-v2 = <&cpu6_opp_table>; 196 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 198 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 199 200 l2_600: l2-cache { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&l3_0>; 205 }; 206 }; 207 208 cpu7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,cortex-a76"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 power-domains = <&cpu_pd7>; 214 power-domain-names = "psci"; 215 capacity-dmips-mhz = <1740>; 216 dynamic-power-coefficient = <404>; 217 next-level-cache = <&l2_700>; 218 clocks = <&cpufreq_hw 1>; 219 qcom,freq-domain = <&cpufreq_hw 1>; 220 operating-points-v2 = <&cpu6_opp_table>; 221 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 223 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 224 225 l2_700: l2-cache { 226 compatible = "cache"; 227 cache-level = <2>; 228 cache-unified; 229 next-level-cache = <&l3_0>; 230 }; 231 }; 232 233 cpu-map { 234 cluster0 { 235 core0 { 236 cpu = <&cpu0>; 237 }; 238 239 core1 { 240 cpu = <&cpu1>; 241 }; 242 243 core2 { 244 cpu = <&cpu2>; 245 }; 246 247 core3 { 248 cpu = <&cpu3>; 249 }; 250 251 core4 { 252 cpu = <&cpu4>; 253 }; 254 255 core5 { 256 cpu = <&cpu5>; 257 }; 258 259 core6 { 260 cpu = <&cpu6>; 261 }; 262 263 core7 { 264 cpu = <&cpu7>; 265 }; 266 }; 267 }; 268 269 l3_0: l3-cache { 270 compatible = "cache"; 271 cache-level = <3>; 272 cache-unified; 273 }; 274 }; 275 276 cpu0_opp_table: opp-table-cpu0 { 277 compatible = "operating-points-v2"; 278 opp-shared; 279 280 opp-300000000 { 281 opp-hz = /bits/ 64 <300000000>; 282 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 283 }; 284 285 opp-576000000 { 286 opp-hz = /bits/ 64 <576000000>; 287 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 288 }; 289 290 opp-748800000 { 291 opp-hz = /bits/ 64 <748800000>; 292 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 293 }; 294 295 opp-998400000 { 296 opp-hz = /bits/ 64 <998400000>; 297 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 298 }; 299 300 opp-1209600000 { 301 opp-hz = /bits/ 64 <1209600000>; 302 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 303 }; 304 305 opp-1363200000 { 306 opp-hz = /bits/ 64 <1363200000>; 307 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 308 }; 309 310 opp-1516800000 { 311 opp-hz = /bits/ 64 <1516800000>; 312 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 313 }; 314 315 opp-1593600000 { 316 opp-hz = /bits/ 64 <1593600000>; 317 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 318 }; 319 }; 320 321 cpu6_opp_table: opp-table-cpu6 { 322 compatible = "operating-points-v2"; 323 opp-shared; 324 325 opp-300000000 { 326 opp-hz = /bits/ 64 <300000000>; 327 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 328 }; 329 330 opp-652800000 { 331 opp-hz = /bits/ 64 <652800000>; 332 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 333 }; 334 335 opp-768000000 { 336 opp-hz = /bits/ 64 <768000000>; 337 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 338 }; 339 340 opp-979200000 { 341 opp-hz = /bits/ 64 <979200000>; 342 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 343 }; 344 345 opp-1017600000 { 346 opp-hz = /bits/ 64 <1017600000>; 347 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 348 }; 349 350 opp-1094400000 { 351 opp-hz = /bits/ 64 <109440000>; 352 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 353 }; 354 355 opp-1209600000 { 356 opp-hz = /bits/ 64 <1209600000>; 357 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 358 }; 359 360 opp-1363200000 { 361 opp-hz = /bits/ 64 <1363200000>; 362 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 363 }; 364 365 opp-1516800000 { 366 opp-hz = /bits/ 64 <1516800000>; 367 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 368 }; 369 370 opp-1708800000 { 371 opp-hz = /bits/ 64 <1708800000>; 372 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 373 }; 374 375 opp-1900800000 { 376 opp-hz = /bits/ 64 <1900800000>; 377 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 378 }; 379 }; 380 381 dummy_eud: dummy-sink { 382 compatible = "arm,coresight-dummy-sink"; 383 384 in-ports { 385 port { 386 eud_in: endpoint { 387 remote-endpoint = <&replicator_swao_out1>; 388 }; 389 }; 390 }; 391 }; 392 393 idle-states { 394 entry-method = "psci"; 395 396 little_cpu_sleep_0: cpu-sleep-0-0 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "silver-power-collapse"; 399 arm,psci-suspend-param = <0x40000003>; 400 entry-latency-us = <549>; 401 exit-latency-us = <901>; 402 min-residency-us = <1774>; 403 local-timer-stop; 404 }; 405 406 little_cpu_sleep_1: cpu-sleep-0-1 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "silver-rail-power-collapse"; 409 arm,psci-suspend-param = <0x40000004>; 410 entry-latency-us = <702>; 411 exit-latency-us = <915>; 412 min-residency-us = <4001>; 413 local-timer-stop; 414 }; 415 416 big_cpu_sleep_0: cpu-sleep-1-0 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "gold-power-collapse"; 419 arm,psci-suspend-param = <0x40000003>; 420 entry-latency-us = <523>; 421 exit-latency-us = <1244>; 422 min-residency-us = <2207>; 423 local-timer-stop; 424 }; 425 426 big_cpu_sleep_1: cpu-sleep-1-1 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "gold-rail-power-collapse"; 429 arm,psci-suspend-param = <0x40000004>; 430 entry-latency-us = <526>; 431 exit-latency-us = <1854>; 432 min-residency-us = <5555>; 433 local-timer-stop; 434 }; 435 }; 436 437 domain-idle-states { 438 cluster_sleep_0: cluster-sleep-0 { 439 compatible = "domain-idle-state"; 440 arm,psci-suspend-param = <0x41000044>; 441 entry-latency-us = <2752>; 442 exit-latency-us = <3048>; 443 min-residency-us = <6118>; 444 }; 445 446 cluster_sleep_1: cluster-sleep-1 { 447 compatible = "domain-idle-state"; 448 arm,psci-suspend-param = <0x41001344>; 449 entry-latency-us = <3263>; 450 exit-latency-us = <4562>; 451 min-residency-us = <8467>; 452 }; 453 454 cluster_sleep_2: cluster-sleep-2 { 455 compatible = "domain-idle-state"; 456 arm,psci-suspend-param = <0x4100b344>; 457 entry-latency-us = <3638>; 458 exit-latency-us = <6562>; 459 min-residency-us = <9826>; 460 }; 461 }; 462 463 memory@80000000 { 464 device_type = "memory"; 465 /* We expect the bootloader to fill in the size */ 466 reg = <0 0x80000000 0 0>; 467 }; 468 469 firmware { 470 scm { 471 compatible = "qcom,scm-qcs615", "qcom,scm"; 472 qcom,dload-mode = <&tcsr 0x13000>; 473 }; 474 }; 475 476 camnoc_virt: interconnect-0 { 477 compatible = "qcom,qcs615-camnoc-virt"; 478 #interconnect-cells = <2>; 479 qcom,bcm-voters = <&apps_bcm_voter>; 480 }; 481 482 ipa_virt: interconnect-1 { 483 compatible = "qcom,qcs615-ipa-virt"; 484 #interconnect-cells = <2>; 485 qcom,bcm-voters = <&apps_bcm_voter>; 486 }; 487 488 mc_virt: interconnect-2 { 489 compatible = "qcom,qcs615-mc-virt"; 490 #interconnect-cells = <2>; 491 qcom,bcm-voters = <&apps_bcm_voter>; 492 }; 493 494 smp2p-adsp { 495 compatible = "qcom,smp2p"; 496 qcom,smem = <443>, <429>; 497 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 498 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 499 mboxes = <&apss_shared 26>; 500 501 qcom,local-pid = <0>; 502 qcom,remote-pid = <2>; 503 504 adsp_smp2p_out: master-kernel { 505 qcom,entry-name = "master-kernel"; 506 #qcom,smem-state-cells = <1>; 507 }; 508 509 adsp_smp2p_in: slave-kernel { 510 qcom,entry-name = "slave-kernel"; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 }; 514 }; 515 516 smp2p-cdsp { 517 compatible = "qcom,smp2p"; 518 qcom,smem = <94>, <432>; 519 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 520 mboxes = <&apss_shared 6>; 521 522 qcom,local-pid = <0>; 523 qcom,remote-pid = <5>; 524 525 cdsp_smp2p_out: master-kernel { 526 qcom,entry-name = "master-kernel"; 527 #qcom,smem-state-cells = <1>; 528 }; 529 530 cdsp_smp2p_in: slave-kernel { 531 qcom,entry-name = "slave-kernel"; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 536 }; 537 538 qup_opp_table: opp-table-qup { 539 compatible = "operating-points-v2"; 540 opp-shared; 541 542 opp-75000000 { 543 opp-hz = /bits/ 64 <75000000>; 544 required-opps = <&rpmhpd_opp_low_svs>; 545 }; 546 547 opp-100000000 { 548 opp-hz = /bits/ 64 <100000000>; 549 required-opps = <&rpmhpd_opp_svs>; 550 }; 551 552 opp-128000000 { 553 opp-hz = /bits/ 64 <128000000>; 554 required-opps = <&rpmhpd_opp_nom>; 555 }; 556 }; 557 558 psci { 559 compatible = "arm,psci-1.0"; 560 method = "smc"; 561 562 cpu_pd0: power-domain-cpu0 { 563 #power-domain-cells = <0>; 564 power-domains = <&cluster_pd>; 565 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 566 }; 567 568 cpu_pd1: power-domain-cpu1 { 569 #power-domain-cells = <0>; 570 power-domains = <&cluster_pd>; 571 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 572 }; 573 574 cpu_pd2: power-domain-cpu2 { 575 #power-domain-cells = <0>; 576 power-domains = <&cluster_pd>; 577 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 578 }; 579 580 cpu_pd3: power-domain-cpu3 { 581 #power-domain-cells = <0>; 582 power-domains = <&cluster_pd>; 583 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 584 }; 585 586 cpu_pd4: power-domain-cpu4 { 587 #power-domain-cells = <0>; 588 power-domains = <&cluster_pd>; 589 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 590 }; 591 592 cpu_pd5: power-domain-cpu5 { 593 #power-domain-cells = <0>; 594 power-domains = <&cluster_pd>; 595 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 596 }; 597 598 cpu_pd6: power-domain-cpu6 { 599 #power-domain-cells = <0>; 600 power-domains = <&cluster_pd>; 601 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 602 }; 603 604 cpu_pd7: power-domain-cpu7 { 605 #power-domain-cells = <0>; 606 power-domains = <&cluster_pd>; 607 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 608 }; 609 610 cluster_pd: power-domain-cluster { 611 #power-domain-cells = <0>; 612 domain-idle-states = <&cluster_sleep_0 613 &cluster_sleep_1 614 &cluster_sleep_2>; 615 }; 616 }; 617 618 reserved-memory { 619 #address-cells = <2>; 620 #size-cells = <2>; 621 ranges; 622 623 aop_cmd_db_mem: aop-cmd-db@85f20000 { 624 compatible = "qcom,cmd-db"; 625 reg = <0x0 0x85f20000 0x0 0x20000>; 626 no-map; 627 }; 628 629 smem_region: smem@86000000 { 630 compatible = "qcom,smem"; 631 reg = <0x0 0x86000000 0x0 0x200000>; 632 no-map; 633 hwlocks = <&tcsr_mutex 3>; 634 }; 635 636 pil_video_mem: pil-video@93400000 { 637 reg = <0x0 0x93400000 0x0 0x500000>; 638 no-map; 639 }; 640 641 rproc_cdsp_mem: rproc-cdsp@93b00000 { 642 reg = <0x0 0x93b00000 0x0 0x1e00000>; 643 no-map; 644 }; 645 646 rproc_adsp_mem: rproc-adsp@95900000 { 647 reg = <0x0 0x95900000 0x0 0x1e00000>; 648 no-map; 649 }; 650 }; 651 652 soc: soc@0 { 653 compatible = "simple-bus"; 654 ranges = <0 0 0 0 0x10 0>; 655 dma-ranges = <0 0 0 0 0x10 0>; 656 #address-cells = <2>; 657 #size-cells = <2>; 658 659 gcc: clock-controller@100000 { 660 compatible = "qcom,qcs615-gcc"; 661 reg = <0 0x00100000 0 0x1f0000>; 662 clocks = <&rpmhcc RPMH_CXO_CLK>, 663 <&rpmhcc RPMH_CXO_CLK_A>, 664 <&sleep_clk>; 665 666 #clock-cells = <1>; 667 #reset-cells = <1>; 668 #power-domain-cells = <1>; 669 }; 670 671 qfprom: efuse@780000 { 672 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 673 reg = <0x0 0x00780000 0x0 0x7000>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 qusb2_hstx_trim: hstx-trim@1f8 { 678 reg = <0x1fb 0x1>; 679 bits = <1 4>; 680 }; 681 }; 682 683 rng@793000 { 684 compatible = "qcom,qcs615-trng", "qcom,trng"; 685 reg = <0x0 0x00793000 0x0 0x1000>; 686 }; 687 688 sdhc_1: mmc@7c4000 { 689 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 690 reg = <0x0 0x007c4000 0x0 0x1000>, 691 <0x0 0x007c5000 0x0 0x1000>, 692 <0x0 0x007c8000 0x0 0x8000>; 693 reg-names = "hc", 694 "cqhci", 695 "ice"; 696 697 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 699 interrupt-names = "hc_irq", 700 "pwr_irq"; 701 702 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 703 <&gcc GCC_SDCC1_APPS_CLK>, 704 <&rpmhcc RPMH_CXO_CLK>, 705 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 706 clock-names = "iface", 707 "core", 708 "xo", 709 "ice"; 710 711 resets = <&gcc GCC_SDCC1_BCR>; 712 713 power-domains = <&rpmhpd RPMHPD_CX>; 714 operating-points-v2 = <&sdhc1_opp_table>; 715 iommus = <&apps_smmu 0x02c0 0x0>; 716 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 718 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 719 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 720 interconnect-names = "sdhc-ddr", 721 "cpu-sdhc"; 722 723 qcom,dll-config = <0x000f642c>; 724 qcom,ddr-config = <0x80040868>; 725 supports-cqe; 726 dma-coherent; 727 728 status = "disabled"; 729 730 sdhc1_opp_table: opp-table { 731 compatible = "operating-points-v2"; 732 733 opp-50000000 { 734 opp-hz = /bits/ 64 <50000000>; 735 required-opps = <&rpmhpd_opp_low_svs>; 736 }; 737 738 opp-100000000 { 739 opp-hz = /bits/ 64 <100000000>; 740 required-opps = <&rpmhpd_opp_svs>; 741 }; 742 743 opp-200000000 { 744 opp-hz = /bits/ 64 <200000000>; 745 required-opps = <&rpmhpd_opp_svs_l1>; 746 }; 747 748 opp-384000000 { 749 opp-hz = /bits/ 64 <384000000>; 750 required-opps = <&rpmhpd_opp_nom>; 751 }; 752 }; 753 }; 754 755 gpi_dma0: dma-controller@800000 { 756 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 757 reg = <0x0 0x800000 0x0 0x60000>; 758 #dma-cells = <3>; 759 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 767 dma-channels = <8>; 768 dma-channel-mask = <0xf>; 769 iommus = <&apps_smmu 0xd6 0x0>; 770 status = "disabled"; 771 }; 772 773 qupv3_id_0: geniqup@8c0000 { 774 compatible = "qcom,geni-se-qup"; 775 reg = <0x0 0x008c0000 0x0 0x6000>; 776 ranges; 777 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 778 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 779 clock-names = "m-ahb", 780 "s-ahb"; 781 iommus = <&apps_smmu 0xc3 0x0>; 782 #address-cells = <2>; 783 #size-cells = <2>; 784 status = "disabled"; 785 786 uart0: serial@880000 { 787 compatible = "qcom,geni-debug-uart"; 788 reg = <0x0 0x00880000 0x0 0x4000>; 789 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 790 clock-names = "se"; 791 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 792 pinctrl-names = "default"; 793 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 794 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 795 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 796 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 797 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 798 interconnect-names = "qup-core", 799 "qup-config"; 800 power-domains = <&rpmhpd RPMHPD_CX>; 801 operating-points-v2 = <&qup_opp_table>; 802 status = "disabled"; 803 }; 804 805 i2c1: i2c@884000 { 806 compatible = "qcom,geni-i2c"; 807 reg = <0x0 0x884000 0x0 0x4000>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 812 clock-names = "se"; 813 pinctrl-0 = <&qup_i2c1_data_clk>; 814 pinctrl-names = "default"; 815 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 816 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 818 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 819 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 821 interconnect-names = "qup-core", 822 "qup-config", 823 "qup-memory"; 824 power-domains = <&rpmhpd RPMHPD_CX>; 825 required-opps = <&rpmhpd_opp_low_svs>; 826 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 827 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 828 dma-names = "tx", 829 "rx"; 830 status = "disabled"; 831 }; 832 833 i2c2: i2c@888000 { 834 compatible = "qcom,geni-i2c"; 835 reg = <0x0 0x888000 0x0 0x4000>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 840 clock-names = "se"; 841 pinctrl-0 = <&qup_i2c2_data_clk>; 842 pinctrl-names = "default"; 843 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 844 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 845 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 846 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 847 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 849 interconnect-names = "qup-core", 850 "qup-config", 851 "qup-memory"; 852 power-domains = <&rpmhpd RPMHPD_CX>; 853 required-opps = <&rpmhpd_opp_low_svs>; 854 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 855 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 856 dma-names = "tx", 857 "rx"; 858 status = "disabled"; 859 }; 860 861 spi2: spi@888000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0x0 0x00888000 0x0 0x4000>; 864 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 866 clock-names = "se"; 867 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 868 pinctrl-names = "default"; 869 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 870 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 871 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 872 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 873 interconnect-names = "qup-core", 874 "qup-config"; 875 power-domains = <&rpmhpd RPMHPD_CX>; 876 operating-points-v2 = <&qup_opp_table>; 877 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 878 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 879 dma-names = "tx", 880 "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 uart2: serial@888000 { 887 compatible = "qcom,geni-uart"; 888 reg = <0x0 0x00888000 0x0 0x4000>; 889 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 891 clock-names = "se"; 892 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 893 <&qup_uart2_tx>, <&qup_uart2_rx>; 894 pinctrl-names = "default"; 895 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 897 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 898 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 899 interconnect-names = "qup-core", 900 "qup-config"; 901 power-domains = <&rpmhpd RPMHPD_CX>; 902 operating-points-v2 = <&qup_opp_table>; 903 status = "disabled"; 904 }; 905 906 i2c3: i2c@88c000 { 907 compatible = "qcom,geni-i2c"; 908 reg = <0x0 0x88c000 0x0 0x4000>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 913 clock-names = "se"; 914 pinctrl-0 = <&qup_i2c3_data_clk>; 915 pinctrl-names = "default"; 916 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 919 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 920 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 922 interconnect-names = "qup-core", 923 "qup-config", 924 "qup-memory"; 925 power-domains = <&rpmhpd RPMHPD_CX>; 926 required-opps = <&rpmhpd_opp_low_svs>; 927 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 928 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 929 dma-names = "tx", 930 "rx"; 931 status = "disabled"; 932 }; 933 }; 934 935 gpi_dma1: dma-controller@a00000 { 936 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 937 reg = <0x0 0xa00000 0x0 0x60000>; 938 #dma-cells = <3>; 939 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 947 dma-channels = <8>; 948 dma-channel-mask = <0xf>; 949 iommus = <&apps_smmu 0x376 0x0>; 950 status = "disabled"; 951 }; 952 953 qupv3_id_1: geniqup@ac0000 { 954 compatible = "qcom,geni-se-qup"; 955 reg = <0x0 0xac0000 0x0 0x2000>; 956 ranges; 957 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 958 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 959 clock-names = "m-ahb", 960 "s-ahb"; 961 iommus = <&apps_smmu 0x363 0x0>; 962 #address-cells = <2>; 963 #size-cells = <2>; 964 status = "disabled"; 965 966 i2c4: i2c@a80000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0x0 0xa80000 0x0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-0 = <&qup_i2c4_data_clk>; 972 pinctrl-names = "default"; 973 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 978 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 979 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 980 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 981 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 982 interconnect-names = "qup-core", 983 "qup-config", 984 "qup-memory"; 985 power-domains = <&rpmhpd RPMHPD_CX>; 986 required-opps = <&rpmhpd_opp_low_svs>; 987 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 988 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 989 dma-names = "tx", 990 "rx"; 991 status = "disabled"; 992 }; 993 994 spi4: spi@a80000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0x0 0xa80000 0x0 0x4000>; 997 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 998 clock-names = "se"; 999 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1000 pinctrl-names = "default"; 1001 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1006 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1007 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1008 interconnect-names = "qup-core", 1009 "qup-config"; 1010 power-domains = <&rpmhpd RPMHPD_CX>; 1011 operating-points-v2 = <&qup_opp_table>; 1012 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1013 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1014 dma-names = "tx", 1015 "rx"; 1016 status = "disabled"; 1017 }; 1018 1019 uart4: serial@a80000 { 1020 compatible = "qcom,geni-uart"; 1021 reg = <0x0 0xa80000 0x0 0x4000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1023 clock-names = "se"; 1024 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1025 <&qup_uart4_tx>, <&qup_uart4_rx>; 1026 pinctrl-names = "default"; 1027 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1028 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1029 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 power-domains = <&rpmhpd RPMHPD_CX>; 1035 operating-points-v2 = <&qup_opp_table>; 1036 status = "disabled"; 1037 }; 1038 1039 i2c5: i2c@a84000 { 1040 compatible = "qcom,geni-i2c"; 1041 reg = <0x0 0xa84000 0x0 0x4000>; 1042 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1043 clock-names = "se"; 1044 pinctrl-0 = <&qup_i2c5_data_clk>; 1045 pinctrl-names = "default"; 1046 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1050 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1051 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1052 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1053 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1054 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1055 interconnect-names = "qup-core", 1056 "qup-config", 1057 "qup-memory"; 1058 power-domains = <&rpmhpd RPMHPD_CX>; 1059 required-opps = <&rpmhpd_opp_low_svs>; 1060 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1061 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1062 dma-names = "tx", 1063 "rx"; 1064 status = "disabled"; 1065 }; 1066 1067 i2c6: i2c@a88000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0x0 0xa88000 0x0 0x4000>; 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1071 clock-names = "se"; 1072 pinctrl-0 = <&qup_i2c6_data_clk>; 1073 pinctrl-names = "default"; 1074 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1080 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1081 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1083 interconnect-names = "qup-core", 1084 "qup-config", 1085 "qup-memory"; 1086 power-domains = <&rpmhpd RPMHPD_CX>; 1087 required-opps = <&rpmhpd_opp_low_svs>; 1088 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1089 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1090 dma-names = "tx", 1091 "rx"; 1092 status = "disabled"; 1093 }; 1094 1095 spi6: spi@a88000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0x0 0xa88000 0x0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1099 clock-names = "se"; 1100 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1101 pinctrl-names = "default"; 1102 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1106 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1108 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1109 interconnect-names = "qup-core", 1110 "qup-config"; 1111 power-domains = <&rpmhpd RPMHPD_CX>; 1112 operating-points-v2 = <&qup_opp_table>; 1113 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1114 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1115 dma-names = "tx", 1116 "rx"; 1117 status = "disabled"; 1118 }; 1119 1120 uart6: serial@a88000 { 1121 compatible = "qcom,geni-uart"; 1122 reg = <0x0 0xa88000 0x0 0x4000>; 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1124 clock-names = "se"; 1125 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1126 <&qup_uart6_tx>, <&qup_uart6_rx>; 1127 pinctrl-names = "default"; 1128 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1129 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1130 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1131 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1132 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config"; 1135 power-domains = <&rpmhpd RPMHPD_CX>; 1136 operating-points-v2 = <&qup_opp_table>; 1137 status = "disabled"; 1138 }; 1139 1140 i2c7: i2c@a8c000 { 1141 compatible = "qcom,geni-i2c"; 1142 reg = <0x0 0xa8c000 0x0 0x4000>; 1143 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1144 clock-names = "se"; 1145 pinctrl-0 = <&qup_i2c7_data_clk>; 1146 pinctrl-names = "default"; 1147 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1152 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1153 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1154 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1156 interconnect-names = "qup-core", 1157 "qup-config", 1158 "qup-memory"; 1159 power-domains = <&rpmhpd RPMHPD_CX>; 1160 required-opps = <&rpmhpd_opp_low_svs>; 1161 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1162 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1163 dma-names = "tx", 1164 "rx"; 1165 status = "disabled"; 1166 }; 1167 1168 spi7: spi@a8c000 { 1169 compatible = "qcom,geni-spi"; 1170 reg = <0x0 0xa8c000 0x0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1172 clock-names = "se"; 1173 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1174 pinctrl-names = "default"; 1175 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1179 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1181 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1182 interconnect-names = "qup-core", 1183 "qup-config"; 1184 power-domains = <&rpmhpd RPMHPD_CX>; 1185 operating-points-v2 = <&qup_opp_table>; 1186 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1187 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1188 dma-names = "tx", 1189 "rx"; 1190 status = "disabled"; 1191 }; 1192 1193 uart7: serial@a8c000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0x0 0xa8c000 0x0 0x4000>; 1196 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1197 clock-names = "se"; 1198 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1199 <&qup_uart7_tx>, <&qup_uart7_rx>; 1200 pinctrl-names = "default"; 1201 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1202 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1204 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1205 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1206 interconnect-names = "qup-core", 1207 "qup-config"; 1208 power-domains = <&rpmhpd RPMHPD_CX>; 1209 operating-points-v2 = <&qup_opp_table>; 1210 status = "disabled"; 1211 }; 1212 }; 1213 1214 config_noc: interconnect@1500000 { 1215 reg = <0x0 0x01500000 0x0 0x5080>; 1216 compatible = "qcom,qcs615-config-noc"; 1217 #interconnect-cells = <2>; 1218 qcom,bcm-voters = <&apps_bcm_voter>; 1219 }; 1220 1221 system_noc: interconnect@1620000 { 1222 reg = <0x0 0x01620000 0x0 0x1f300>; 1223 compatible = "qcom,qcs615-system-noc"; 1224 #interconnect-cells = <2>; 1225 qcom,bcm-voters = <&apps_bcm_voter>; 1226 }; 1227 1228 aggre1_noc: interconnect@1700000 { 1229 reg = <0x0 0x01700000 0x0 0x3f200>; 1230 compatible = "qcom,qcs615-aggre1-noc"; 1231 #interconnect-cells = <2>; 1232 qcom,bcm-voters = <&apps_bcm_voter>; 1233 }; 1234 1235 mmss_noc: interconnect@1740000 { 1236 reg = <0x0 0x01740000 0x0 0x1c100>; 1237 compatible = "qcom,qcs615-mmss-noc"; 1238 #interconnect-cells = <2>; 1239 qcom,bcm-voters = <&apps_bcm_voter>; 1240 }; 1241 1242 pcie: pcie@1c08000 { 1243 device_type = "pci"; 1244 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1245 reg = <0x0 0x01c08000 0x0 0x3000>, 1246 <0x0 0x40000000 0x0 0xf1d>, 1247 <0x0 0x40000f20 0x0 0xa8>, 1248 <0x0 0x40001000 0x0 0x1000>, 1249 <0x0 0x40100000 0x0 0x100000>, 1250 <0x0 0x01c0b000 0x0 0x1000>; 1251 reg-names = "parf", 1252 "dbi", 1253 "elbi", 1254 "atu", 1255 "config", 1256 "mhi"; 1257 #address-cells = <3>; 1258 #size-cells = <2>; 1259 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1260 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1261 bus-range = <0x00 0xff>; 1262 1263 dma-coherent; 1264 1265 linux,pci-domain = <0>; 1266 num-lanes = <1>; 1267 1268 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-names = "msi0", 1278 "msi1", 1279 "msi2", 1280 "msi3", 1281 "msi4", 1282 "msi5", 1283 "msi6", 1284 "msi7", 1285 "global"; 1286 1287 #interrupt-cells = <1>; 1288 interrupt-map-mask = <0 0 0 0x7>; 1289 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1290 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1291 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1292 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1293 1294 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1295 <&gcc GCC_PCIE_0_AUX_CLK>, 1296 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1297 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1298 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1299 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1300 clock-names = "pipe", 1301 "aux", 1302 "cfg", 1303 "bus_master", 1304 "bus_slave", 1305 "slave_q2a"; 1306 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1307 assigned-clock-rates = <19200000>; 1308 1309 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1312 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1313 interconnect-names = "pcie-mem", "cpu-pcie"; 1314 1315 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1316 <0x100 &apps_smmu 0x401 0x1>; 1317 1318 resets = <&gcc GCC_PCIE_0_BCR>; 1319 reset-names = "pci"; 1320 1321 power-domains = <&gcc PCIE_0_GDSC>; 1322 1323 phys = <&pcie_phy>; 1324 phy-names = "pciephy"; 1325 1326 max-link-speed = <2>; 1327 1328 operating-points-v2 = <&pcie_opp_table>; 1329 1330 status = "disabled"; 1331 1332 pcie_opp_table: opp-table { 1333 compatible = "operating-points-v2"; 1334 1335 /* GEN 1 x1 */ 1336 opp-2500000 { 1337 opp-hz = /bits/ 64 <2500000>; 1338 required-opps = <&rpmhpd_opp_low_svs>; 1339 opp-peak-kBps = <250000 1>; 1340 }; 1341 1342 /* GEN 2 x1 */ 1343 opp-5000000 { 1344 opp-hz = /bits/ 64 <5000000>; 1345 required-opps = <&rpmhpd_opp_low_svs>; 1346 opp-peak-kBps = <500000 1>; 1347 }; 1348 }; 1349 1350 pcie_port0: pcie@0 { 1351 device_type = "pci"; 1352 reg = <0x0 0x0 0x0 0x0 0x0>; 1353 #address-cells = <3>; 1354 #size-cells = <2>; 1355 ranges; 1356 bus-range = <0x01 0xff>; 1357 }; 1358 }; 1359 1360 pcie_phy: phy@1c0e000 { 1361 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1362 reg = <0x0 0x01c0e000 0x0 0x1000>; 1363 1364 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1365 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1366 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1367 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1368 <&gcc GCC_PCIE_0_PIPE_CLK>; 1369 clock-names = "aux", 1370 "cfg_ahb", 1371 "ref", 1372 "refgen", 1373 "pipe"; 1374 1375 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1376 reset-names = "phy"; 1377 1378 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1379 assigned-clock-rates = <100000000>; 1380 1381 #clock-cells = <0>; 1382 clock-output-names = "pcie_0_pipe_clk"; 1383 1384 #phy-cells = <0>; 1385 1386 status = "disabled"; 1387 }; 1388 1389 ufs_mem_hc: ufshc@1d84000 { 1390 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1391 reg = <0x0 0x01d84000 0x0 0x3000>, 1392 <0x0 0x01d90000 0x0 0x8000>; 1393 reg-names = "std", 1394 "ice"; 1395 1396 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1397 1398 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1399 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1400 <&gcc GCC_UFS_PHY_AHB_CLK>, 1401 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1402 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1403 <&rpmhcc RPMH_CXO_CLK>, 1404 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1405 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1406 clock-names = "core_clk", 1407 "bus_aggr_clk", 1408 "iface_clk", 1409 "core_clk_unipro", 1410 "ref_clk", 1411 "tx_lane0_sync_clk", 1412 "rx_lane0_sync_clk", 1413 "ice_core_clk"; 1414 1415 resets = <&gcc GCC_UFS_PHY_BCR>; 1416 reset-names = "rst"; 1417 1418 operating-points-v2 = <&ufs_opp_table>; 1419 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1422 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1423 interconnect-names = "ufs-ddr", 1424 "cpu-ufs"; 1425 1426 power-domains = <&gcc UFS_PHY_GDSC>; 1427 1428 iommus = <&apps_smmu 0x300 0x0>; 1429 dma-coherent; 1430 1431 lanes-per-direction = <1>; 1432 1433 phys = <&ufs_mem_phy>; 1434 phy-names = "ufsphy"; 1435 1436 #reset-cells = <1>; 1437 1438 status = "disabled"; 1439 1440 ufs_opp_table: opp-table { 1441 compatible = "operating-points-v2"; 1442 1443 opp-50000000 { 1444 opp-hz = /bits/ 64 <50000000>, 1445 /bits/ 64 <0>, 1446 /bits/ 64 <0>, 1447 /bits/ 64 <37500000>, 1448 /bits/ 64 <0>, 1449 /bits/ 64 <0>, 1450 /bits/ 64 <0>, 1451 /bits/ 64 <75000000>; 1452 required-opps = <&rpmhpd_opp_low_svs>; 1453 }; 1454 1455 opp-100000000 { 1456 opp-hz = /bits/ 64 <100000000>, 1457 /bits/ 64 <0>, 1458 /bits/ 64 <0>, 1459 /bits/ 64 <75000000>, 1460 /bits/ 64 <0>, 1461 /bits/ 64 <0>, 1462 /bits/ 64 <0>, 1463 /bits/ 64 <150000000>; 1464 required-opps = <&rpmhpd_opp_svs>; 1465 }; 1466 1467 opp-200000000 { 1468 opp-hz = /bits/ 64 <200000000>, 1469 /bits/ 64 <0>, 1470 /bits/ 64 <0>, 1471 /bits/ 64 <150000000>, 1472 /bits/ 64 <0>, 1473 /bits/ 64 <0>, 1474 /bits/ 64 <0>, 1475 /bits/ 64 <300000000>; 1476 required-opps = <&rpmhpd_opp_nom>; 1477 }; 1478 }; 1479 }; 1480 1481 ufs_mem_phy: phy@1d87000 { 1482 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1483 reg = <0x0 0x01d87000 0x0 0xe00>; 1484 clocks = <&rpmhcc RPMH_CXO_CLK>, 1485 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1486 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1487 clock-names = "ref", 1488 "ref_aux", 1489 "qref"; 1490 1491 power-domains = <&gcc UFS_PHY_GDSC>; 1492 1493 resets = <&ufs_mem_hc 0>; 1494 reset-names = "ufsphy"; 1495 1496 #clock-cells = <1>; 1497 #phy-cells = <0>; 1498 1499 status = "disabled"; 1500 }; 1501 1502 cryptobam: dma-controller@1dc4000 { 1503 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1504 reg = <0x0 0x01dc4000 0x0 0x24000>; 1505 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1506 #dma-cells = <1>; 1507 qcom,ee = <0>; 1508 qcom,controlled-remotely; 1509 num-channels = <16>; 1510 qcom,num-ees = <4>; 1511 iommus = <&apps_smmu 0x0104 0x0011>; 1512 }; 1513 1514 crypto: crypto@1dfa000 { 1515 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1516 reg = <0x0 0x01dfa000 0x0 0x6000>; 1517 dmas = <&cryptobam 4>, <&cryptobam 5>; 1518 dma-names = "rx", "tx"; 1519 iommus = <&apps_smmu 0x0104 0x0011>; 1520 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1521 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1522 interconnect-names = "memory"; 1523 }; 1524 1525 tcsr_mutex: hwlock@1f40000 { 1526 compatible = "qcom,tcsr-mutex"; 1527 reg = <0x0 0x01f40000 0x0 0x20000>; 1528 #hwlock-cells = <1>; 1529 }; 1530 1531 tcsr: syscon@1fc0000 { 1532 compatible = "qcom,qcs615-tcsr", "syscon"; 1533 reg = <0x0 0x01fc0000 0x0 0x30000>; 1534 }; 1535 1536 tlmm: pinctrl@3100000 { 1537 compatible = "qcom,qcs615-tlmm"; 1538 reg = <0x0 0x03100000 0x0 0x300000>, 1539 <0x0 0x03500000 0x0 0x300000>, 1540 <0x0 0x03d00000 0x0 0x300000>; 1541 reg-names = "east", 1542 "west", 1543 "south"; 1544 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1545 gpio-ranges = <&tlmm 0 0 124>; 1546 gpio-controller; 1547 #gpio-cells = <2>; 1548 interrupt-controller; 1549 #interrupt-cells = <2>; 1550 wakeup-parent = <&pdc>; 1551 1552 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1553 pins = "gpio4", "gpio5"; 1554 function = "qup0"; 1555 1556 }; 1557 1558 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1559 pins = "gpio0", "gpio1"; 1560 function = "qup0"; 1561 }; 1562 1563 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1564 pins = "gpio18", "gpio19"; 1565 function = "qup0"; 1566 }; 1567 1568 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1569 pins = "gpio20", "gpio21"; 1570 function = "qup1"; 1571 }; 1572 1573 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1574 pins = "gpio14", "gpio15"; 1575 function = "qup1"; 1576 }; 1577 1578 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1579 pins = "gpio6", "gpio7"; 1580 function = "qup1"; 1581 }; 1582 1583 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1584 pins = "gpio10", "gpio11"; 1585 function = "qup1"; 1586 }; 1587 1588 qup_spi2_data_clk: qup-spi2-data-clk-state { 1589 pins = "gpio0", "gpio1", "gpio2"; 1590 function = "qup0"; 1591 }; 1592 1593 qup_spi2_cs: qup-spi2-cs-state { 1594 pins = "gpio3"; 1595 function = "qup0"; 1596 }; 1597 1598 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1599 pins = "gpio3"; 1600 function = "gpio"; 1601 }; 1602 1603 qup_spi4_data_clk: qup-spi4-data-clk-state { 1604 pins = "gpio20", "gpio21", "gpio22"; 1605 function = "qup1"; 1606 }; 1607 1608 qup_spi4_cs: qup-spi4-cs-state { 1609 pins = "gpio23"; 1610 function = "qup1"; 1611 }; 1612 1613 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1614 pins = "gpio23"; 1615 function = "gpio"; 1616 }; 1617 1618 qup_spi6_data_clk: qup-spi6-data-clk-state { 1619 pins = "gpio6", "gpio7", "gpio8"; 1620 function = "qup1"; 1621 }; 1622 1623 qup_spi6_cs: qup-spi6-cs-state { 1624 pins = "gpio9"; 1625 function = "qup1"; 1626 }; 1627 1628 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1629 pins = "gpio9"; 1630 function = "gpio"; 1631 }; 1632 1633 qup_spi7_data_clk: qup-spi7-data-clk-state { 1634 pins = "gpio10", "gpio11", "gpio12"; 1635 function = "qup1"; 1636 }; 1637 1638 qup_spi7_cs: qup-spi7-cs-state { 1639 pins = "gpio13"; 1640 function = "qup1"; 1641 }; 1642 1643 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1644 pins = "gpio13"; 1645 function = "gpio"; 1646 }; 1647 1648 qup_uart0_tx: qup-uart0-tx-state { 1649 pins = "gpio16"; 1650 function = "qup0"; 1651 }; 1652 1653 qup_uart0_rx: qup-uart0-rx-state { 1654 pins = "gpio17"; 1655 function = "qup0"; 1656 }; 1657 1658 qup_uart2_cts: qup-uart2-cts-state { 1659 pins = "gpio0"; 1660 function = "qup0"; 1661 }; 1662 1663 qup_uart2_rts: qup-uart2-rts-state { 1664 pins = "gpio1"; 1665 function = "qup0"; 1666 }; 1667 1668 qup_uart2_tx: qup-uart2-tx-state { 1669 pins = "gpio2"; 1670 function = "qup0"; 1671 }; 1672 1673 qup_uart2_rx: qup-uart2-rx-state { 1674 pins = "gpio3"; 1675 function = "qup0"; 1676 }; 1677 1678 qup_uart4_cts: qup-uart4-cts-state { 1679 pins = "gpio20"; 1680 function = "qup1"; 1681 }; 1682 1683 qup_uart4_rts: qup-uart4-rts-state { 1684 pins = "gpio21"; 1685 function = "qup1"; 1686 }; 1687 1688 qup_uart4_tx: qup-uart4-tx-state { 1689 pins = "gpio22"; 1690 function = "qup1"; 1691 }; 1692 1693 qup_uart4_rx: qup-uart4-rx-state { 1694 pins = "gpio23"; 1695 function = "qup1"; 1696 }; 1697 1698 qup_uart6_cts: qup-uart6-cts-state { 1699 pins = "gpio6"; 1700 function = "qup1"; 1701 }; 1702 1703 qup_uart6_rts: qup-uart6-rts-state { 1704 pins = "gpio7"; 1705 function = "qup1"; 1706 }; 1707 1708 qup_uart6_tx: qup-uart6-tx-state { 1709 pins = "gpio8"; 1710 function = "qup1"; 1711 }; 1712 1713 qup_uart6_rx: qup-uart6-rx-state { 1714 pins = "gpio9"; 1715 function = "qup1"; 1716 }; 1717 1718 qup_uart7_cts: qup-uart7-cts-state { 1719 pins = "gpio10"; 1720 function = "qup1"; 1721 }; 1722 1723 qup_uart7_rts: qup-uart7-rts-state { 1724 pins = "gpio11"; 1725 function = "qup1"; 1726 }; 1727 1728 qup_uart7_tx: qup-uart7-tx-state { 1729 pins = "gpio12"; 1730 function = "qup1"; 1731 }; 1732 1733 qup_uart7_rx: qup-uart7-rx-state { 1734 pins = "gpio13"; 1735 function = "qup1"; 1736 }; 1737 1738 sdc1_state_on: sdc1-on-state { 1739 clk-pins { 1740 pins = "sdc1_clk"; 1741 bias-disable; 1742 drive-strength = <16>; 1743 }; 1744 1745 cmd-pins { 1746 pins = "sdc1_cmd"; 1747 bias-pull-up; 1748 drive-strength = <10>; 1749 }; 1750 1751 data-pins { 1752 pins = "sdc1_data"; 1753 bias-pull-up; 1754 drive-strength = <10>; 1755 }; 1756 1757 rclk-pins { 1758 pins = "sdc1_rclk"; 1759 bias-pull-down; 1760 }; 1761 }; 1762 1763 sdc1_state_off: sdc1-off-state { 1764 clk-pins { 1765 pins = "sdc1_clk"; 1766 bias-disable; 1767 drive-strength = <2>; 1768 }; 1769 1770 cmd-pins { 1771 pins = "sdc1_cmd"; 1772 bias-pull-up; 1773 drive-strength = <2>; 1774 }; 1775 1776 data-pins { 1777 pins = "sdc1_data"; 1778 bias-pull-up; 1779 drive-strength = <2>; 1780 }; 1781 1782 rclk-pins { 1783 pins = "sdc1_rclk"; 1784 bias-pull-down; 1785 }; 1786 }; 1787 1788 sdc2_state_on: sdc2-on-state { 1789 clk-pins { 1790 pins = "sdc2_clk"; 1791 bias-disable; 1792 drive-strength = <16>; 1793 }; 1794 1795 cmd-pins { 1796 pins = "sdc2_cmd"; 1797 bias-pull-up; 1798 drive-strength = <10>; 1799 }; 1800 1801 data-pins { 1802 pins = "sdc2_data"; 1803 bias-pull-up; 1804 drive-strength = <10>; 1805 }; 1806 }; 1807 1808 sdc2_state_off: sdc2-off-state { 1809 clk-pins { 1810 pins = "sdc2_clk"; 1811 bias-disable; 1812 drive-strength = <2>; 1813 }; 1814 1815 cmd-pins { 1816 pins = "sdc2_cmd"; 1817 bias-pull-up; 1818 drive-strength = <2>; 1819 }; 1820 1821 data-pins { 1822 pins = "sdc2_data"; 1823 bias-pull-up; 1824 drive-strength = <2>; 1825 }; 1826 }; 1827 }; 1828 1829 gpucc: clock-controller@5090000 { 1830 compatible = "qcom,qcs615-gpucc"; 1831 reg = <0 0x05090000 0 0x9000>; 1832 1833 clocks = <&rpmhcc RPMH_CXO_CLK>, 1834 <&gcc GPLL0>, 1835 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1836 1837 #clock-cells = <1>; 1838 #reset-cells = <1>; 1839 #power-domain-cells = <1>; 1840 }; 1841 1842 stm@6002000 { 1843 compatible = "arm,coresight-stm", "arm,primecell"; 1844 reg = <0x0 0x06002000 0x0 0x1000>, 1845 <0x0 0x16280000 0x0 0x180000>; 1846 reg-names = "stm-base", 1847 "stm-stimulus-base"; 1848 1849 clocks = <&aoss_qmp>; 1850 clock-names = "apb_pclk"; 1851 1852 out-ports { 1853 port { 1854 stm_out: endpoint { 1855 remote-endpoint = <&funnel_in0_in7>; 1856 }; 1857 }; 1858 }; 1859 }; 1860 1861 tpda@6004000 { 1862 compatible = "qcom,coresight-tpda", "arm,primecell"; 1863 reg = <0x0 0x06004000 0x0 0x1000>; 1864 1865 clocks = <&aoss_qmp>; 1866 clock-names = "apb_pclk"; 1867 1868 in-ports { 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 port@0 { 1873 reg = <0>; 1874 1875 tpda_qdss_in0: endpoint { 1876 remote-endpoint = <&tpdm_center_out>; 1877 }; 1878 }; 1879 1880 port@4 { 1881 reg = <4>; 1882 1883 tpda_qdss_in4: endpoint { 1884 remote-endpoint = <&funnel_monaq_out>; 1885 }; 1886 }; 1887 1888 port@5 { 1889 reg = <5>; 1890 1891 tpda_qdss_in5: endpoint { 1892 remote-endpoint = <&funnel_ddr_0_out>; 1893 }; 1894 }; 1895 1896 port@6 { 1897 reg = <6>; 1898 1899 tpda_qdss_in6: endpoint { 1900 remote-endpoint = <&funnel_turing_out>; 1901 }; 1902 }; 1903 1904 port@7 { 1905 reg = <7>; 1906 1907 tpda_qdss_in7: endpoint { 1908 remote-endpoint = <&tpdm_vsense_out>; 1909 }; 1910 }; 1911 1912 port@8 { 1913 reg = <8>; 1914 1915 tpda_qdss_in8: endpoint { 1916 remote-endpoint = <&tpdm_dcc_out>; 1917 }; 1918 }; 1919 1920 port@9 { 1921 reg = <9>; 1922 1923 tpda_qdss_in9: endpoint { 1924 remote-endpoint = <&tpdm_prng_out>; 1925 }; 1926 }; 1927 1928 port@b { 1929 reg = <11>; 1930 1931 tpda_qdss_in11: endpoint { 1932 remote-endpoint = <&tpdm_qm_out>; 1933 }; 1934 }; 1935 1936 port@c { 1937 reg = <12>; 1938 1939 tpda_qdss_in12: endpoint { 1940 remote-endpoint = <&tpdm_west_out>; 1941 }; 1942 }; 1943 1944 port@d { 1945 reg = <13>; 1946 1947 tpda_qdss_in13: endpoint { 1948 remote-endpoint = <&tpdm_pimem_out>; 1949 }; 1950 }; 1951 }; 1952 1953 out-ports { 1954 port { 1955 tpda_qdss_out: endpoint { 1956 remote-endpoint = <&funnel_qatb_in>; 1957 }; 1958 }; 1959 }; 1960 }; 1961 1962 funnel@6005000 { 1963 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1964 reg = <0x0 0x06005000 0x0 0x1000>; 1965 1966 clocks = <&aoss_qmp>; 1967 clock-names = "apb_pclk"; 1968 1969 in-ports { 1970 port { 1971 funnel_qatb_in: endpoint { 1972 remote-endpoint = <&tpda_qdss_out>; 1973 }; 1974 }; 1975 }; 1976 1977 out-ports { 1978 port { 1979 funnel_qatb_out: endpoint { 1980 remote-endpoint = <&funnel_in0_in6>; 1981 }; 1982 }; 1983 }; 1984 }; 1985 1986 cti@6010000 { 1987 compatible = "arm,coresight-cti", "arm,primecell"; 1988 reg = <0x0 0x06010000 0x0 0x1000>; 1989 1990 clocks = <&aoss_qmp>; 1991 clock-names = "apb_pclk"; 1992 }; 1993 1994 cti@6011000 { 1995 compatible = "arm,coresight-cti", "arm,primecell"; 1996 reg = <0x0 0x06011000 0x0 0x1000>; 1997 1998 clocks = <&aoss_qmp>; 1999 clock-names = "apb_pclk"; 2000 }; 2001 2002 cti@6012000 { 2003 compatible = "arm,coresight-cti", "arm,primecell"; 2004 reg = <0x0 0x06012000 0x0 0x1000>; 2005 2006 clocks = <&aoss_qmp>; 2007 clock-names = "apb_pclk"; 2008 }; 2009 2010 cti@6013000 { 2011 compatible = "arm,coresight-cti", "arm,primecell"; 2012 reg = <0x0 0x06013000 0x0 0x1000>; 2013 2014 clocks = <&aoss_qmp>; 2015 clock-names = "apb_pclk"; 2016 }; 2017 2018 cti@6014000 { 2019 compatible = "arm,coresight-cti", "arm,primecell"; 2020 reg = <0x0 0x06014000 0x0 0x1000>; 2021 2022 clocks = <&aoss_qmp>; 2023 clock-names = "apb_pclk"; 2024 }; 2025 2026 cti@6015000 { 2027 compatible = "arm,coresight-cti", "arm,primecell"; 2028 reg = <0x0 0x06015000 0x0 0x1000>; 2029 2030 clocks = <&aoss_qmp>; 2031 clock-names = "apb_pclk"; 2032 }; 2033 2034 cti@6016000 { 2035 compatible = "arm,coresight-cti", "arm,primecell"; 2036 reg = <0x0 0x06016000 0x0 0x1000>; 2037 2038 clocks = <&aoss_qmp>; 2039 clock-names = "apb_pclk"; 2040 }; 2041 2042 cti@6017000 { 2043 compatible = "arm,coresight-cti", "arm,primecell"; 2044 reg = <0x0 0x06017000 0x0 0x1000>; 2045 2046 clocks = <&aoss_qmp>; 2047 clock-names = "apb_pclk"; 2048 }; 2049 2050 cti@6018000 { 2051 compatible = "arm,coresight-cti", "arm,primecell"; 2052 reg = <0x0 0x06018000 0x0 0x1000>; 2053 2054 clocks = <&aoss_qmp>; 2055 clock-names = "apb_pclk"; 2056 }; 2057 2058 cti@6019000 { 2059 compatible = "arm,coresight-cti", "arm,primecell"; 2060 reg = <0x0 0x06019000 0x0 0x1000>; 2061 2062 clocks = <&aoss_qmp>; 2063 clock-names = "apb_pclk"; 2064 }; 2065 2066 cti@601a000 { 2067 compatible = "arm,coresight-cti", "arm,primecell"; 2068 reg = <0x0 0x0601a000 0x0 0x1000>; 2069 2070 clocks = <&aoss_qmp>; 2071 clock-names = "apb_pclk"; 2072 }; 2073 2074 cti@601b000 { 2075 compatible = "arm,coresight-cti", "arm,primecell"; 2076 reg = <0x0 0x0601b000 0x0 0x1000>; 2077 2078 clocks = <&aoss_qmp>; 2079 clock-names = "apb_pclk"; 2080 }; 2081 2082 cti@601c000 { 2083 compatible = "arm,coresight-cti", "arm,primecell"; 2084 reg = <0x0 0x0601c000 0x0 0x1000>; 2085 2086 clocks = <&aoss_qmp>; 2087 clock-names = "apb_pclk"; 2088 }; 2089 2090 cti@601d000 { 2091 compatible = "arm,coresight-cti", "arm,primecell"; 2092 reg = <0x0 0x0601d000 0x0 0x1000>; 2093 2094 clocks = <&aoss_qmp>; 2095 clock-names = "apb_pclk"; 2096 }; 2097 2098 cti@601e000 { 2099 compatible = "arm,coresight-cti", "arm,primecell"; 2100 reg = <0x0 0x0601e000 0x0 0x1000>; 2101 2102 clocks = <&aoss_qmp>; 2103 clock-names = "apb_pclk"; 2104 }; 2105 2106 cti@601f000 { 2107 compatible = "arm,coresight-cti", "arm,primecell"; 2108 reg = <0x0 0x0601f000 0x0 0x1000>; 2109 2110 clocks = <&aoss_qmp>; 2111 clock-names = "apb_pclk"; 2112 }; 2113 2114 funnel@6041000 { 2115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2116 reg = <0x0 0x06041000 0x0 0x1000>; 2117 2118 clocks = <&aoss_qmp>; 2119 clock-names = "apb_pclk"; 2120 2121 in-ports { 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 2125 port@6 { 2126 reg = <6>; 2127 2128 funnel_in0_in6: endpoint { 2129 remote-endpoint = <&funnel_qatb_out>; 2130 }; 2131 }; 2132 2133 port@7 { 2134 reg = <7>; 2135 2136 funnel_in0_in7: endpoint { 2137 remote-endpoint = <&stm_out>; 2138 }; 2139 }; 2140 }; 2141 2142 out-ports { 2143 port { 2144 funnel_in0_out: endpoint { 2145 remote-endpoint = <&funnel_merg_in0>; 2146 }; 2147 }; 2148 }; 2149 }; 2150 2151 funnel@6042000 { 2152 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2153 reg = <0x0 0x06042000 0x0 0x1000>; 2154 2155 clocks = <&aoss_qmp>; 2156 clock-names = "apb_pclk"; 2157 2158 in-ports { 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 2162 port@3 { 2163 reg = <3>; 2164 2165 funnel_in1_in3: endpoint { 2166 remote-endpoint = <&replicator_swao_out0>; 2167 }; 2168 }; 2169 2170 port@4 { 2171 reg = <4>; 2172 2173 funnel_in1_in4: endpoint { 2174 remote-endpoint = <&tpdm_wcss_out>; 2175 }; 2176 }; 2177 2178 port@7 { 2179 reg = <7>; 2180 2181 funnel_in1_in7: endpoint { 2182 remote-endpoint = <&funnel_apss_merg_out>; 2183 }; 2184 }; 2185 }; 2186 2187 out-ports { 2188 port { 2189 funnel_in1_out: endpoint { 2190 remote-endpoint = <&funnel_merg_in1>; 2191 }; 2192 }; 2193 }; 2194 }; 2195 2196 funnel@6045000 { 2197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2198 reg = <0x0 0x06045000 0x0 0x1000>; 2199 2200 clocks = <&aoss_qmp>; 2201 clock-names = "apb_pclk"; 2202 2203 in-ports { 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 2207 port@0 { 2208 reg = <0>; 2209 2210 funnel_merg_in0: endpoint { 2211 remote-endpoint = <&funnel_in0_out>; 2212 }; 2213 }; 2214 2215 port@1 { 2216 reg = <1>; 2217 2218 funnel_merg_in1: endpoint { 2219 remote-endpoint = <&funnel_in1_out>; 2220 }; 2221 }; 2222 }; 2223 2224 out-ports { 2225 port { 2226 funnel_merg_out: endpoint { 2227 remote-endpoint = <&tmc_etf_in>; 2228 }; 2229 }; 2230 }; 2231 }; 2232 2233 replicator@6046000 { 2234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2235 reg = <0x0 0x06046000 0x0 0x1000>; 2236 2237 clocks = <&aoss_qmp>; 2238 clock-names = "apb_pclk"; 2239 2240 in-ports { 2241 port { 2242 replicator0_in: endpoint { 2243 remote-endpoint = <&tmc_etf_out>; 2244 }; 2245 }; 2246 }; 2247 2248 out-ports { 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 2252 port@1 { 2253 reg = <1>; 2254 2255 replicator0_out1: endpoint { 2256 remote-endpoint = <&replicator1_in>; 2257 }; 2258 }; 2259 }; 2260 }; 2261 2262 tmc@6047000 { 2263 compatible = "arm,coresight-tmc", "arm,primecell"; 2264 reg = <0x0 0x06047000 0x0 0x1000>; 2265 2266 clocks = <&aoss_qmp>; 2267 clock-names = "apb_pclk"; 2268 2269 in-ports { 2270 port { 2271 tmc_etf_in: endpoint { 2272 remote-endpoint = <&funnel_merg_out>; 2273 }; 2274 }; 2275 }; 2276 2277 out-ports { 2278 port { 2279 tmc_etf_out: endpoint { 2280 remote-endpoint = <&replicator0_in>; 2281 }; 2282 }; 2283 }; 2284 }; 2285 2286 replicator@604a000 { 2287 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2288 reg = <0x0 0x0604a000 0x0 0x1000>; 2289 2290 clocks = <&aoss_qmp>; 2291 clock-names = "apb_pclk"; 2292 status = "disabled"; 2293 2294 in-ports { 2295 port { 2296 replicator1_in: endpoint { 2297 remote-endpoint = <&replicator0_out1>; 2298 }; 2299 }; 2300 }; 2301 2302 out-ports { 2303 port { 2304 replicator1_out: endpoint { 2305 remote-endpoint = <&funnel_swao_in6>; 2306 }; 2307 }; 2308 }; 2309 }; 2310 2311 cti@683b000 { 2312 compatible = "arm,coresight-cti", "arm,primecell"; 2313 reg = <0x0 0x0683b000 0x0 0x1000>; 2314 2315 clocks = <&aoss_qmp>; 2316 clock-names = "apb_pclk"; 2317 }; 2318 2319 tpdm@6840000 { 2320 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2321 reg = <0x0 0x06840000 0x0 0x1000>; 2322 2323 clocks = <&aoss_qmp>; 2324 clock-names = "apb_pclk"; 2325 2326 qcom,cmb-element-bits = <64>; 2327 qcom,cmb-msrs-num = <32>; 2328 status = "disabled"; 2329 2330 out-ports { 2331 port { 2332 tpdm_vsense_out: endpoint { 2333 remote-endpoint = <&tpda_qdss_in7>; 2334 }; 2335 }; 2336 }; 2337 }; 2338 2339 tpdm@684c000 { 2340 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2341 reg = <0x0 0x0684c000 0x0 0x1000>; 2342 2343 clocks = <&aoss_qmp>; 2344 clock-names = "apb_pclk"; 2345 2346 qcom,cmb-element-bits = <32>; 2347 qcom,cmb-msrs-num = <32>; 2348 2349 out-ports { 2350 port { 2351 tpdm_prng_out: endpoint { 2352 remote-endpoint = <&tpda_qdss_in9>; 2353 }; 2354 }; 2355 }; 2356 }; 2357 2358 tpdm@6850000 { 2359 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2360 reg = <0x0 0x06850000 0x0 0x1000>; 2361 2362 clocks = <&aoss_qmp>; 2363 clock-names = "apb_pclk"; 2364 2365 qcom,cmb-element-bits = <64>; 2366 qcom,cmb-msrs-num = <32>; 2367 qcom,dsb-element-bits = <32>; 2368 qcom,dsb-msrs-num = <32>; 2369 2370 out-ports { 2371 port { 2372 tpdm_pimem_out: endpoint { 2373 remote-endpoint = <&tpda_qdss_in13>; 2374 }; 2375 }; 2376 }; 2377 }; 2378 2379 tpdm@6860000 { 2380 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2381 reg = <0x0 0x06860000 0x0 0x1000>; 2382 2383 clocks = <&aoss_qmp>; 2384 clock-names = "apb_pclk"; 2385 2386 qcom,dsb-element-bits = <32>; 2387 qcom,dsb-msrs-num = <32>; 2388 2389 out-ports { 2390 port { 2391 tpdm_turing_out: endpoint { 2392 remote-endpoint = <&funnel_turing_in>; 2393 }; 2394 }; 2395 }; 2396 }; 2397 2398 funnel@6861000 { 2399 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2400 reg = <0x0 0x06861000 0x0 0x1000>; 2401 2402 clocks = <&aoss_qmp>; 2403 clock-names = "apb_pclk"; 2404 2405 in-ports { 2406 port { 2407 funnel_turing_in: endpoint { 2408 remote-endpoint = <&tpdm_turing_out>; 2409 }; 2410 }; 2411 }; 2412 2413 out-ports { 2414 port { 2415 funnel_turing_out: endpoint { 2416 remote-endpoint = <&tpda_qdss_in6>; 2417 }; 2418 }; 2419 }; 2420 }; 2421 2422 cti@6867000 { 2423 compatible = "arm,coresight-cti", "arm,primecell"; 2424 reg = <0x0 0x06867000 0x0 0x1000>; 2425 2426 clocks = <&aoss_qmp>; 2427 clock-names = "apb_pclk"; 2428 }; 2429 2430 tpdm@6870000 { 2431 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2432 reg = <0x0 0x06870000 0x0 0x1000>; 2433 2434 clocks = <&aoss_qmp>; 2435 clock-names = "apb_pclk"; 2436 2437 qcom,cmb-element-bits = <32>; 2438 qcom,cmb-msrs-num = <32>; 2439 status = "disabled"; 2440 2441 out-ports { 2442 port { 2443 tpdm_dcc_out: endpoint { 2444 remote-endpoint = <&tpda_qdss_in8>; 2445 }; 2446 }; 2447 }; 2448 }; 2449 2450 tpdm@699c000 { 2451 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2452 reg = <0x0 0x0699c000 0x0 0x1000>; 2453 2454 clocks = <&aoss_qmp>; 2455 clock-names = "apb_pclk"; 2456 2457 qcom,cmb-element-bits = <32>; 2458 qcom,cmb-msrs-num = <32>; 2459 qcom,dsb-element-bits = <32>; 2460 qcom,dsb-msrs-num = <32>; 2461 status = "disabled"; 2462 2463 out-ports { 2464 port { 2465 tpdm_wcss_out: endpoint { 2466 remote-endpoint = <&funnel_in1_in4>; 2467 }; 2468 }; 2469 }; 2470 }; 2471 2472 tpdm@69c0000 { 2473 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2474 reg = <0x0 0x069c0000 0x0 0x1000>; 2475 2476 clocks = <&aoss_qmp>; 2477 clock-names = "apb_pclk"; 2478 2479 qcom,dsb-element-bits = <32>; 2480 qcom,dsb-msrs-num = <32>; 2481 2482 out-ports { 2483 port { 2484 tpdm_monaq_out: endpoint { 2485 remote-endpoint = <&funnel_monaq_in>; 2486 }; 2487 }; 2488 }; 2489 }; 2490 2491 funnel@69c3000 { 2492 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2493 reg = <0x0 0x069c3000 0x0 0x1000>; 2494 2495 clocks = <&aoss_qmp>; 2496 clock-names = "apb_pclk"; 2497 2498 in-ports { 2499 port { 2500 funnel_monaq_in: endpoint { 2501 remote-endpoint = <&tpdm_monaq_out>; 2502 }; 2503 }; 2504 }; 2505 2506 out-ports { 2507 port { 2508 funnel_monaq_out: endpoint { 2509 remote-endpoint = <&tpda_qdss_in4>; 2510 }; 2511 }; 2512 }; 2513 }; 2514 2515 tpdm@69d0000 { 2516 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2517 reg = <0x0 0x069d0000 0x0 0x1000>; 2518 2519 clocks = <&aoss_qmp>; 2520 clock-names = "apb_pclk"; 2521 2522 qcom,dsb-element-bits = <32>; 2523 qcom,dsb-msrs-num = <32>; 2524 status = "disabled"; 2525 2526 out-ports { 2527 port { 2528 tpdm_qm_out: endpoint { 2529 remote-endpoint = <&tpda_qdss_in11>; 2530 }; 2531 }; 2532 }; 2533 }; 2534 2535 tpdm@6a00000 { 2536 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2537 reg = <0x0 0x06a00000 0x0 0x1000>; 2538 2539 clocks = <&aoss_qmp>; 2540 clock-names = "apb_pclk"; 2541 2542 qcom,dsb-element-bits = <32>; 2543 qcom,dsb-msrs-num = <32>; 2544 status = "disabled"; 2545 2546 out-ports { 2547 port { 2548 tpdm_ddr_out: endpoint { 2549 remote-endpoint = <&funnel_ddr_0_in>; 2550 }; 2551 }; 2552 }; 2553 }; 2554 2555 cti@6a02000 { 2556 compatible = "arm,coresight-cti", "arm,primecell"; 2557 reg = <0x0 0x06a02000 0x0 0x1000>; 2558 2559 clocks = <&aoss_qmp>; 2560 clock-names = "apb_pclk"; 2561 }; 2562 2563 cti@6a03000 { 2564 compatible = "arm,coresight-cti", "arm,primecell"; 2565 reg = <0x0 0x06a03000 0x0 0x1000>; 2566 2567 clocks = <&aoss_qmp>; 2568 clock-names = "apb_pclk"; 2569 }; 2570 2571 cti@6a10000 { 2572 compatible = "arm,coresight-cti", "arm,primecell"; 2573 reg = <0x0 0x06a10000 0x0 0x1000>; 2574 2575 clocks = <&aoss_qmp>; 2576 clock-names = "apb_pclk"; 2577 }; 2578 2579 cti@6a11000 { 2580 compatible = "arm,coresight-cti", "arm,primecell"; 2581 reg = <0x0 0x06a11000 0x0 0x1000>; 2582 2583 clocks = <&aoss_qmp>; 2584 clock-names = "apb_pclk"; 2585 }; 2586 2587 funnel@6a05000 { 2588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2589 reg = <0x0 0x06a05000 0x0 0x1000>; 2590 2591 clocks = <&aoss_qmp>; 2592 clock-names = "apb_pclk"; 2593 2594 in-ports { 2595 port { 2596 funnel_ddr_0_in: endpoint { 2597 remote-endpoint = <&tpdm_ddr_out>; 2598 }; 2599 }; 2600 }; 2601 2602 out-ports { 2603 port { 2604 funnel_ddr_0_out: endpoint { 2605 remote-endpoint = <&tpda_qdss_in5>; 2606 }; 2607 }; 2608 }; 2609 }; 2610 2611 tpda@6b01000 { 2612 compatible = "qcom,coresight-tpda", "arm,primecell"; 2613 reg = <0x0 0x06b01000 0x0 0x1000>; 2614 2615 clocks = <&aoss_qmp>; 2616 clock-names = "apb_pclk"; 2617 2618 in-ports { 2619 #address-cells = <1>; 2620 #size-cells = <0>; 2621 2622 port@0 { 2623 reg = <0>; 2624 2625 tpda_swao_in0: endpoint { 2626 remote-endpoint = <&tpdm_swao0_out>; 2627 }; 2628 }; 2629 2630 port@1 { 2631 reg = <1>; 2632 2633 tpda_swao_in1: endpoint { 2634 remote-endpoint = <&tpdm_swao1_out>; 2635 }; 2636 2637 }; 2638 }; 2639 2640 out-ports { 2641 port { 2642 tpda_swao_out: endpoint { 2643 remote-endpoint = <&funnel_swao_in7>; 2644 }; 2645 }; 2646 }; 2647 }; 2648 2649 tpdm@6b02000 { 2650 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2651 reg = <0x0 0x06b02000 0x0 0x1000>; 2652 2653 clocks = <&aoss_qmp>; 2654 clock-names = "apb_pclk"; 2655 2656 qcom,cmb-element-bits = <64>; 2657 qcom,cmb-msrs-num = <32>; 2658 status = "disabled"; 2659 2660 out-ports { 2661 port { 2662 tpdm_swao0_out: endpoint { 2663 remote-endpoint = <&tpda_swao_in0>; 2664 }; 2665 }; 2666 }; 2667 }; 2668 2669 tpdm@6b03000 { 2670 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2671 reg = <0x0 0x06b03000 0x0 0x1000>; 2672 2673 clocks = <&aoss_qmp>; 2674 clock-names = "apb_pclk"; 2675 2676 qcom,dsb-element-bits = <32>; 2677 qcom,dsb-msrs-num = <32>; 2678 status = "disabled"; 2679 2680 out-ports { 2681 port { 2682 tpdm_swao1_out: endpoint { 2683 remote-endpoint = <&tpda_swao_in1>; 2684 }; 2685 }; 2686 }; 2687 }; 2688 2689 cti@6b04000 { 2690 compatible = "arm,coresight-cti", "arm,primecell"; 2691 reg = <0x0 0x06b04000 0x0 0x1000>; 2692 2693 clocks = <&aoss_qmp>; 2694 clock-names = "apb_pclk"; 2695 }; 2696 2697 cti@6b05000 { 2698 compatible = "arm,coresight-cti", "arm,primecell"; 2699 reg = <0x0 0x06b05000 0x0 0x1000>; 2700 2701 clocks = <&aoss_qmp>; 2702 clock-names = "apb_pclk"; 2703 }; 2704 2705 cti@6b06000 { 2706 compatible = "arm,coresight-cti", "arm,primecell"; 2707 reg = <0x0 0x06b06000 0x0 0x1000>; 2708 2709 clocks = <&aoss_qmp>; 2710 clock-names = "apb_pclk"; 2711 }; 2712 2713 cti@6b07000 { 2714 compatible = "arm,coresight-cti", "arm,primecell"; 2715 reg = <0x0 0x06b07000 0x0 0x1000>; 2716 2717 clocks = <&aoss_qmp>; 2718 clock-names = "apb_pclk"; 2719 }; 2720 2721 funnel@6b08000 { 2722 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2723 reg = <0x0 0x06b08000 0x0 0x1000>; 2724 2725 clocks = <&aoss_qmp>; 2726 clock-names = "apb_pclk"; 2727 2728 in-ports { 2729 #address-cells = <1>; 2730 #size-cells = <0>; 2731 2732 port@6 { 2733 reg = <6>; 2734 2735 funnel_swao_in6: endpoint { 2736 remote-endpoint = <&replicator1_out>; 2737 }; 2738 }; 2739 2740 port@7 { 2741 reg = <7>; 2742 2743 funnel_swao_in7: endpoint { 2744 remote-endpoint = <&tpda_swao_out>; 2745 }; 2746 }; 2747 }; 2748 2749 out-ports { 2750 port { 2751 funnel_swao_out: endpoint { 2752 remote-endpoint = <&tmc_etf_swao_in>; 2753 }; 2754 }; 2755 }; 2756 }; 2757 2758 tmc@6b09000 { 2759 compatible = "arm,coresight-tmc", "arm,primecell"; 2760 reg = <0x0 0x06b09000 0x0 0x1000>; 2761 2762 clocks = <&aoss_qmp>; 2763 clock-names = "apb_pclk"; 2764 2765 in-ports { 2766 port { 2767 tmc_etf_swao_in: endpoint { 2768 remote-endpoint = <&funnel_swao_out>; 2769 }; 2770 }; 2771 }; 2772 2773 out-ports { 2774 port { 2775 tmc_etf_swao_out: endpoint { 2776 remote-endpoint = <&replicator_swao_in>; 2777 }; 2778 }; 2779 }; 2780 }; 2781 2782 replicator@6b0a000 { 2783 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2784 reg = <0x0 0x06b0a000 0x0 0x1000>; 2785 2786 clocks = <&aoss_qmp>; 2787 clock-names = "apb_pclk"; 2788 2789 in-ports { 2790 port { 2791 replicator_swao_in: endpoint { 2792 remote-endpoint = <&tmc_etf_swao_out>; 2793 }; 2794 }; 2795 }; 2796 2797 out-ports { 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 port@0 { 2802 reg = <0>; 2803 2804 replicator_swao_out0: endpoint { 2805 remote-endpoint = <&funnel_in1_in3>; 2806 }; 2807 }; 2808 2809 port@1 { 2810 reg = <1>; 2811 2812 replicator_swao_out1: endpoint { 2813 remote-endpoint = <&eud_in>; 2814 }; 2815 }; 2816 }; 2817 }; 2818 2819 cti@6b21000 { 2820 compatible = "arm,coresight-cti", "arm,primecell"; 2821 reg = <0x0 0x06b21000 0x0 0x1000>; 2822 2823 clocks = <&aoss_qmp>; 2824 clock-names = "apb_pclk"; 2825 }; 2826 2827 tpdm@6b48000 { 2828 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2829 reg = <0x0 0x06b48000 0x0 0x1000>; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 qcom,dsb-element-bits = <32>; 2835 qcom,dsb-msrs-num = <32>; 2836 2837 out-ports { 2838 port { 2839 tpdm_west_out: endpoint { 2840 remote-endpoint = <&tpda_qdss_in12>; 2841 }; 2842 }; 2843 }; 2844 }; 2845 2846 cti@6c13000 { 2847 compatible = "arm,coresight-cti", "arm,primecell"; 2848 reg = <0x0 0x06c13000 0x0 0x1000>; 2849 2850 clocks = <&aoss_qmp>; 2851 clock-names = "apb_pclk"; 2852 2853 /* Not all required clocks can be enabled from the OS */ 2854 status = "fail"; 2855 }; 2856 2857 cti@6c20000 { 2858 compatible = "arm,coresight-cti", "arm,primecell"; 2859 reg = <0x0 0x06c20000 0x0 0x1000>; 2860 2861 clocks = <&aoss_qmp>; 2862 clock-names = "apb_pclk"; 2863 status = "disabled"; 2864 }; 2865 2866 tpdm@6c28000 { 2867 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2868 reg = <0x0 0x06c28000 0x0 0x1000>; 2869 2870 clocks = <&aoss_qmp>; 2871 clock-names = "apb_pclk"; 2872 2873 qcom,dsb-element-bits = <32>; 2874 qcom,dsb-msrs-num = <32>; 2875 2876 out-ports { 2877 port { 2878 tpdm_center_out: endpoint { 2879 remote-endpoint = <&tpda_qdss_in0>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 cti@6c29000 { 2886 compatible = "arm,coresight-cti", "arm,primecell"; 2887 reg = <0x0 0x06c29000 0x0 0x1000>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 }; 2892 2893 cti@6c2a000 { 2894 compatible = "arm,coresight-cti", "arm,primecell"; 2895 reg = <0x0 0x06c2a000 0x0 0x1000>; 2896 2897 clocks = <&aoss_qmp>; 2898 clock-names = "apb_pclk"; 2899 }; 2900 2901 cti@7020000 { 2902 compatible = "arm,coresight-cti", "arm,primecell"; 2903 reg = <0x0 0x07020000 0x0 0x1000>; 2904 2905 clocks = <&aoss_qmp>; 2906 clock-names = "apb_pclk"; 2907 }; 2908 2909 etm@7040000 { 2910 compatible = "arm,primecell"; 2911 reg = <0x0 0x07040000 0x0 0x1000>; 2912 cpu = <&cpu0>; 2913 2914 clocks = <&aoss_qmp>; 2915 clock-names = "apb_pclk"; 2916 2917 arm,coresight-loses-context-with-cpu; 2918 qcom,skip-power-up; 2919 2920 out-ports { 2921 port { 2922 etm0_out: endpoint { 2923 remote-endpoint = <&funnel_apss_in0>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 cti@7120000 { 2930 compatible = "arm,coresight-cti", "arm,primecell"; 2931 reg = <0x0 0x07120000 0x0 0x1000>; 2932 2933 clocks = <&aoss_qmp>; 2934 clock-names = "apb_pclk"; 2935 }; 2936 2937 etm@7140000 { 2938 compatible = "arm,primecell"; 2939 reg = <0x0 0x07140000 0x0 0x1000>; 2940 cpu = <&cpu1>; 2941 2942 clocks = <&aoss_qmp>; 2943 clock-names = "apb_pclk"; 2944 2945 arm,coresight-loses-context-with-cpu; 2946 qcom,skip-power-up; 2947 2948 out-ports { 2949 port { 2950 etm1_out: endpoint { 2951 remote-endpoint = <&funnel_apss_in1>; 2952 }; 2953 }; 2954 }; 2955 }; 2956 2957 cti@7220000 { 2958 compatible = "arm,coresight-cti", "arm,primecell"; 2959 reg = <0x0 0x07220000 0x0 0x1000>; 2960 2961 clocks = <&aoss_qmp>; 2962 clock-names = "apb_pclk"; 2963 }; 2964 2965 etm@7240000 { 2966 compatible = "arm,primecell"; 2967 reg = <0x0 0x07240000 0x0 0x1000>; 2968 cpu = <&cpu2>; 2969 2970 clocks = <&aoss_qmp>; 2971 clock-names = "apb_pclk"; 2972 2973 arm,coresight-loses-context-with-cpu; 2974 qcom,skip-power-up; 2975 2976 out-ports { 2977 port { 2978 etm2_out: endpoint { 2979 remote-endpoint = <&funnel_apss_in2>; 2980 }; 2981 }; 2982 }; 2983 }; 2984 2985 cti@7320000 { 2986 compatible = "arm,coresight-cti", "arm,primecell"; 2987 reg = <0x0 0x07320000 0x0 0x1000>; 2988 2989 clocks = <&aoss_qmp>; 2990 clock-names = "apb_pclk"; 2991 }; 2992 2993 etm@7340000 { 2994 compatible = "arm,primecell"; 2995 reg = <0x0 0x07340000 0x0 0x1000>; 2996 cpu = <&cpu3>; 2997 2998 clocks = <&aoss_qmp>; 2999 clock-names = "apb_pclk"; 3000 3001 arm,coresight-loses-context-with-cpu; 3002 qcom,skip-power-up; 3003 3004 out-ports { 3005 port { 3006 etm3_out: endpoint { 3007 remote-endpoint = <&funnel_apss_in3>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 cti@7420000 { 3014 compatible = "arm,coresight-cti", "arm,primecell"; 3015 reg = <0x0 0x07420000 0x0 0x1000>; 3016 3017 clocks = <&aoss_qmp>; 3018 clock-names = "apb_pclk"; 3019 }; 3020 3021 etm@7440000 { 3022 compatible = "arm,primecell"; 3023 reg = <0x0 0x07440000 0x0 0x1000>; 3024 cpu = <&cpu4>; 3025 3026 clocks = <&aoss_qmp>; 3027 clock-names = "apb_pclk"; 3028 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm4_out: endpoint { 3035 remote-endpoint = <&funnel_apss_in4>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 cti@7520000 { 3042 compatible = "arm,coresight-cti", "arm,primecell"; 3043 reg = <0x0 0x07520000 0x0 0x1000>; 3044 3045 clocks = <&aoss_qmp>; 3046 clock-names = "apb_pclk"; 3047 }; 3048 3049 etm@7540000 { 3050 compatible = "arm,primecell"; 3051 reg = <0x0 0x07540000 0x0 0x1000>; 3052 cpu = <&cpu5>; 3053 3054 clocks = <&aoss_qmp>; 3055 clock-names = "apb_pclk"; 3056 3057 arm,coresight-loses-context-with-cpu; 3058 qcom,skip-power-up; 3059 3060 out-ports { 3061 port { 3062 etm5_out: endpoint { 3063 remote-endpoint = <&funnel_apss_in5>; 3064 }; 3065 }; 3066 }; 3067 }; 3068 3069 cti@7620000 { 3070 compatible = "arm,coresight-cti", "arm,primecell"; 3071 reg = <0x0 0x07620000 0x0 0x1000>; 3072 3073 clocks = <&aoss_qmp>; 3074 clock-names = "apb_pclk"; 3075 }; 3076 3077 etm@7640000 { 3078 compatible = "arm,primecell"; 3079 reg = <0x0 0x07640000 0x0 0x1000>; 3080 cpu = <&cpu6>; 3081 3082 clocks = <&aoss_qmp>; 3083 clock-names = "apb_pclk"; 3084 3085 arm,coresight-loses-context-with-cpu; 3086 qcom,skip-power-up; 3087 3088 out-ports { 3089 port { 3090 etm6_out: endpoint { 3091 remote-endpoint = <&funnel_apss_in6>; 3092 }; 3093 }; 3094 }; 3095 }; 3096 3097 cti@7720000 { 3098 compatible = "arm,coresight-cti", "arm,primecell"; 3099 reg = <0x0 0x07720000 0x0 0x1000>; 3100 3101 clocks = <&aoss_qmp>; 3102 clock-names = "apb_pclk"; 3103 }; 3104 3105 etm@7740000 { 3106 compatible = "arm,primecell"; 3107 reg = <0x0 0x07740000 0x0 0x1000>; 3108 cpu = <&cpu7>; 3109 3110 clocks = <&aoss_qmp>; 3111 clock-names = "apb_pclk"; 3112 3113 arm,coresight-loses-context-with-cpu; 3114 qcom,skip-power-up; 3115 3116 out-ports { 3117 port { 3118 etm7_out: endpoint { 3119 remote-endpoint = <&funnel_apss_in7>; 3120 }; 3121 }; 3122 }; 3123 }; 3124 3125 funnel@7800000 { 3126 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3127 reg = <0x0 0x07800000 0x0 0x1000>; 3128 3129 clocks = <&aoss_qmp>; 3130 clock-names = "apb_pclk"; 3131 3132 in-ports { 3133 #address-cells = <1>; 3134 #size-cells = <0>; 3135 3136 port@0 { 3137 reg = <0>; 3138 3139 funnel_apss_in0: endpoint { 3140 remote-endpoint = <&etm0_out>; 3141 }; 3142 }; 3143 3144 port@1 { 3145 reg = <1>; 3146 3147 funnel_apss_in1: endpoint { 3148 remote-endpoint = <&etm1_out>; 3149 }; 3150 }; 3151 3152 port@2 { 3153 reg = <2>; 3154 3155 funnel_apss_in2: endpoint { 3156 remote-endpoint = <&etm2_out>; 3157 }; 3158 }; 3159 3160 port@3 { 3161 reg = <3>; 3162 3163 funnel_apss_in3: endpoint { 3164 remote-endpoint = <&etm3_out>; 3165 }; 3166 }; 3167 3168 port@4 { 3169 reg = <4>; 3170 3171 funnel_apss_in4: endpoint { 3172 remote-endpoint = <&etm4_out>; 3173 }; 3174 }; 3175 3176 port@5 { 3177 reg = <5>; 3178 3179 funnel_apss_in5: endpoint { 3180 remote-endpoint = <&etm5_out>; 3181 }; 3182 }; 3183 3184 port@6 { 3185 reg = <6>; 3186 3187 funnel_apss_in6: endpoint { 3188 remote-endpoint = <&etm6_out>; 3189 }; 3190 }; 3191 3192 port@7 { 3193 reg = <7>; 3194 3195 funnel_apss_in7: endpoint { 3196 remote-endpoint = <&etm7_out>; 3197 }; 3198 }; 3199 }; 3200 3201 out-ports { 3202 port { 3203 funnel_apss_out: endpoint { 3204 remote-endpoint = <&funnel_apss_merg_in0>; 3205 }; 3206 }; 3207 }; 3208 }; 3209 3210 funnel@7810000 { 3211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3212 reg = <0x0 0x07810000 0x0 0x1000>; 3213 3214 clocks = <&aoss_qmp>; 3215 clock-names = "apb_pclk"; 3216 3217 in-ports { 3218 #address-cells = <1>; 3219 #size-cells = <0>; 3220 3221 port@0 { 3222 reg = <0>; 3223 3224 funnel_apss_merg_in0: endpoint { 3225 remote-endpoint = <&funnel_apss_out>; 3226 }; 3227 }; 3228 3229 port@2 { 3230 reg = <2>; 3231 3232 funnel_apss_merg_in2: endpoint { 3233 remote-endpoint = <&tpda_olc_out>; 3234 }; 3235 }; 3236 3237 port@3 { 3238 reg = <3>; 3239 3240 funnel_apss_merg_in3: endpoint { 3241 remote-endpoint = <&tpda_llm_silver_out>; 3242 }; 3243 }; 3244 3245 port@4 { 3246 reg = <4>; 3247 3248 funnel_apss_merg_in4: endpoint { 3249 remote-endpoint = <&tpda_llm_gold_out>; 3250 }; 3251 }; 3252 3253 port@5 { 3254 reg = <5>; 3255 3256 funnel_apss_merg_in5: endpoint { 3257 remote-endpoint = <&tpda_apss_out>; 3258 }; 3259 }; 3260 }; 3261 3262 out-ports { 3263 port { 3264 funnel_apss_merg_out: endpoint { 3265 remote-endpoint = <&funnel_in1_in7>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 tpdm@7830000 { 3272 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3273 reg = <0x0 0x07830000 0x0 0x1000>; 3274 3275 clocks = <&aoss_qmp>; 3276 clock-names = "apb_pclk"; 3277 3278 qcom,cmb-element-bits = <64>; 3279 qcom,cmb-msrs-num = <32>; 3280 3281 out-ports { 3282 port { 3283 tpdm_olc_out: endpoint { 3284 remote-endpoint = <&tpda_olc_in>; 3285 }; 3286 }; 3287 }; 3288 }; 3289 3290 tpda@7832000 { 3291 compatible = "qcom,coresight-tpda", "arm,primecell"; 3292 reg = <0x0 0x07832000 0x0 0x1000>; 3293 3294 clocks = <&aoss_qmp>; 3295 clock-names = "apb_pclk"; 3296 3297 in-ports { 3298 port { 3299 tpda_olc_in: endpoint { 3300 remote-endpoint = <&tpdm_olc_out>; 3301 }; 3302 }; 3303 }; 3304 3305 out-ports { 3306 port { 3307 tpda_olc_out: endpoint { 3308 remote-endpoint = <&funnel_apss_merg_in2>; 3309 }; 3310 }; 3311 }; 3312 }; 3313 3314 tpdm@7860000 { 3315 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3316 reg = <0x0 0x07860000 0x0 0x1000>; 3317 3318 clocks = <&aoss_qmp>; 3319 clock-names = "apb_pclk"; 3320 3321 qcom,dsb-element-bits = <32>; 3322 qcom,dsb-msrs-num = <32>; 3323 3324 out-ports { 3325 port { 3326 tpdm_apss_out: endpoint { 3327 remote-endpoint = <&tpda_apss_in>; 3328 }; 3329 }; 3330 }; 3331 }; 3332 3333 tpda@7862000 { 3334 compatible = "qcom,coresight-tpda", "arm,primecell"; 3335 reg = <0x0 0x07862000 0x0 0x1000>; 3336 3337 clocks = <&aoss_qmp>; 3338 clock-names = "apb_pclk"; 3339 3340 in-ports { 3341 port { 3342 tpda_apss_in: endpoint { 3343 remote-endpoint = <&tpdm_apss_out>; 3344 }; 3345 }; 3346 }; 3347 3348 out-ports { 3349 port { 3350 tpda_apss_out: endpoint { 3351 remote-endpoint = <&funnel_apss_merg_in5>; 3352 }; 3353 }; 3354 }; 3355 }; 3356 3357 tpdm@78a0000 { 3358 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3359 reg = <0x0 0x078a0000 0x0 0x1000>; 3360 3361 clocks = <&aoss_qmp>; 3362 clock-names = "apb_pclk"; 3363 3364 qcom,cmb-element-bits = <32>; 3365 qcom,cmb-msrs-num = <32>; 3366 3367 out-ports { 3368 port { 3369 tpdm_llm_silver_out: endpoint { 3370 remote-endpoint = <&tpda_llm_silver_in>; 3371 }; 3372 }; 3373 }; 3374 }; 3375 3376 tpdm@78b0000 { 3377 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3378 reg = <0x0 0x078b0000 0x0 0x1000>; 3379 3380 clocks = <&aoss_qmp>; 3381 clock-names = "apb_pclk"; 3382 3383 qcom,cmb-element-bits = <32>; 3384 qcom,cmb-msrs-num = <32>; 3385 3386 out-ports { 3387 port { 3388 tpdm_llm_gold_out: endpoint { 3389 remote-endpoint = <&tpda_llm_gold_in>; 3390 }; 3391 }; 3392 }; 3393 }; 3394 3395 tpda@78c0000 { 3396 compatible = "qcom,coresight-tpda", "arm,primecell"; 3397 reg = <0x0 0x078c0000 0x0 0x1000>; 3398 3399 clocks = <&aoss_qmp>; 3400 clock-names = "apb_pclk"; 3401 3402 in-ports { 3403 port { 3404 tpda_llm_silver_in: endpoint { 3405 remote-endpoint = <&tpdm_llm_silver_out>; 3406 }; 3407 }; 3408 }; 3409 3410 out-ports { 3411 port { 3412 tpda_llm_silver_out: endpoint { 3413 remote-endpoint = <&funnel_apss_merg_in3>; 3414 }; 3415 }; 3416 }; 3417 }; 3418 3419 tpda@78d0000 { 3420 compatible = "qcom,coresight-tpda", "arm,primecell"; 3421 reg = <0x0 0x078d0000 0x0 0x1000>; 3422 3423 clocks = <&aoss_qmp>; 3424 clock-names = "apb_pclk"; 3425 3426 in-ports { 3427 port { 3428 tpda_llm_gold_in: endpoint { 3429 remote-endpoint = <&tpdm_llm_gold_out>; 3430 }; 3431 }; 3432 }; 3433 3434 out-ports { 3435 port { 3436 tpda_llm_gold_out: endpoint { 3437 remote-endpoint = <&funnel_apss_merg_in4>; 3438 }; 3439 }; 3440 }; 3441 }; 3442 3443 cti@78e0000 { 3444 compatible = "arm,coresight-cti", "arm,primecell"; 3445 reg = <0x0 0x078e0000 0x0 0x1000>; 3446 3447 clocks = <&aoss_qmp>; 3448 clock-names = "apb_pclk"; 3449 }; 3450 3451 cti@78f0000 { 3452 compatible = "arm,coresight-cti", "arm,primecell"; 3453 reg = <0x0 0x078f0000 0x0 0x1000>; 3454 3455 clocks = <&aoss_qmp>; 3456 clock-names = "apb_pclk"; 3457 }; 3458 3459 cti@7900000 { 3460 compatible = "arm,coresight-cti", "arm,primecell"; 3461 reg = <0x0 0x07900000 0x0 0x1000>; 3462 3463 clocks = <&aoss_qmp>; 3464 clock-names = "apb_pclk"; 3465 }; 3466 3467 remoteproc_cdsp: remoteproc@8300000 { 3468 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3469 reg = <0x0 0x08300000 0x0 0x4040>; 3470 3471 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3472 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3473 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3474 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3475 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3476 interrupt-names = "wdog", 3477 "fatal", 3478 "ready", 3479 "handover", 3480 "stop-ack"; 3481 3482 clocks = <&rpmhcc RPMH_CXO_CLK>; 3483 clock-names = "xo"; 3484 3485 power-domains = <&rpmhpd RPMHPD_CX>; 3486 power-domain-names = "cx"; 3487 3488 memory-region = <&rproc_cdsp_mem>; 3489 3490 qcom,qmp = <&aoss_qmp>; 3491 3492 qcom,smem-states = <&cdsp_smp2p_out 0>; 3493 qcom,smem-state-names = "stop"; 3494 3495 status = "disabled"; 3496 3497 glink-edge { 3498 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3499 mboxes = <&apss_shared 4>; 3500 label = "cdsp"; 3501 qcom,remote-pid = <5>; 3502 3503 fastrpc { 3504 compatible = "qcom,fastrpc"; 3505 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3506 label = "cdsp"; 3507 #address-cells = <1>; 3508 #size-cells = <0>; 3509 3510 compute-cb@1 { 3511 compatible = "qcom,fastrpc-compute-cb"; 3512 reg = <1>; 3513 iommus = <&apps_smmu 0x1081 0x0>; 3514 dma-coherent; 3515 }; 3516 3517 compute-cb@2 { 3518 compatible = "qcom,fastrpc-compute-cb"; 3519 reg = <2>; 3520 iommus = <&apps_smmu 0x1082 0x0>; 3521 dma-coherent; 3522 }; 3523 3524 compute-cb@3 { 3525 compatible = "qcom,fastrpc-compute-cb"; 3526 reg = <3>; 3527 iommus = <&apps_smmu 0x1083 0x0>; 3528 dma-coherent; 3529 }; 3530 3531 compute-cb@4 { 3532 compatible = "qcom,fastrpc-compute-cb"; 3533 reg = <4>; 3534 iommus = <&apps_smmu 0x1084 0x0>; 3535 dma-coherent; 3536 }; 3537 3538 compute-cb@5 { 3539 compatible = "qcom,fastrpc-compute-cb"; 3540 reg = <5>; 3541 iommus = <&apps_smmu 0x1085 0x0>; 3542 dma-coherent; 3543 }; 3544 3545 compute-cb@6 { 3546 compatible = "qcom,fastrpc-compute-cb"; 3547 reg = <6>; 3548 iommus = <&apps_smmu 0x1086 0x0>; 3549 dma-coherent; 3550 }; 3551 }; 3552 }; 3553 }; 3554 3555 pmu@90b6300 { 3556 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3557 reg = <0x0 0x090b6300 0x0 0x600>; 3558 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3559 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3560 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3561 3562 operating-points-v2 = <&cpu_bwmon_opp_table>; 3563 3564 cpu_bwmon_opp_table: opp-table { 3565 compatible = "operating-points-v2"; 3566 3567 opp-0 { 3568 opp-peak-kBps = <12896000>; 3569 }; 3570 3571 opp-1 { 3572 opp-peak-kBps = <14928000>; 3573 }; 3574 }; 3575 }; 3576 3577 pmu@90cd000 { 3578 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3579 reg = <0x0 0x090cd000 0x0 0x1000>; 3580 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; 3581 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3582 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3583 3584 operating-points-v2 = <&llcc_bwmon_opp_table>; 3585 3586 llcc_bwmon_opp_table: opp-table { 3587 compatible = "operating-points-v2"; 3588 3589 opp-0 { 3590 opp-peak-kBps = <800000>; 3591 }; 3592 3593 opp-1 { 3594 opp-peak-kBps = <1200000>; 3595 }; 3596 3597 opp-2 { 3598 opp-peak-kBps = <1804800>; 3599 }; 3600 3601 opp-3 { 3602 opp-peak-kBps = <2188800>; 3603 }; 3604 3605 opp-4 { 3606 opp-peak-kBps = <2726400>; 3607 }; 3608 3609 opp-5 { 3610 opp-peak-kBps = <3072000>; 3611 }; 3612 3613 opp-6 { 3614 opp-peak-kBps = <4070400>; 3615 }; 3616 3617 opp-7 { 3618 opp-peak-kBps = <5414400>; 3619 }; 3620 3621 opp-8 { 3622 opp-peak-kBps = <6220800>; 3623 }; 3624 }; 3625 }; 3626 3627 sdhc_2: mmc@8804000 { 3628 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3629 reg = <0x0 0x08804000 0x0 0x1000>; 3630 reg-names = "hc"; 3631 3632 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3634 interrupt-names = "hc_irq", 3635 "pwr_irq"; 3636 3637 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3638 <&gcc GCC_SDCC2_APPS_CLK>, 3639 <&rpmhcc RPMH_CXO_CLK>; 3640 clock-names = "iface", 3641 "core", 3642 "xo"; 3643 3644 power-domains = <&rpmhpd RPMHPD_CX>; 3645 operating-points-v2 = <&sdhc2_opp_table>; 3646 iommus = <&apps_smmu 0x02a0 0x0>; 3647 resets = <&gcc GCC_SDCC2_BCR>; 3648 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3649 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3651 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3652 interconnect-names = "sdhc-ddr", 3653 "cpu-sdhc"; 3654 3655 qcom,dll-config = <0x0007642c>; 3656 qcom,ddr-config = <0x80040868>; 3657 dma-coherent; 3658 3659 status = "disabled"; 3660 3661 sdhc2_opp_table: opp-table { 3662 compatible = "operating-points-v2"; 3663 3664 opp-50000000 { 3665 opp-hz = /bits/ 64 <50000000>; 3666 required-opps = <&rpmhpd_opp_low_svs>; 3667 }; 3668 3669 opp-100000000 { 3670 opp-hz = /bits/ 64 <100000000>; 3671 required-opps = <&rpmhpd_opp_svs>; 3672 }; 3673 3674 opp-202000000 { 3675 opp-hz = /bits/ 64 <202000000>; 3676 required-opps = <&rpmhpd_opp_nom>; 3677 }; 3678 }; 3679 }; 3680 3681 dc_noc: interconnect@9160000 { 3682 reg = <0x0 0x09160000 0x0 0x3200>; 3683 compatible = "qcom,qcs615-dc-noc"; 3684 #interconnect-cells = <2>; 3685 qcom,bcm-voters = <&apps_bcm_voter>; 3686 }; 3687 3688 llcc: system-cache-controller@9200000 { 3689 compatible = "qcom,qcs615-llcc"; 3690 reg = <0x0 0x09200000 0x0 0x50000>, 3691 <0x0 0x09600000 0x0 0x50000>; 3692 reg-names = "llcc0_base", 3693 "llcc_broadcast_base"; 3694 }; 3695 3696 gem_noc: interconnect@9680000 { 3697 reg = <0x0 0x09680000 0x0 0x3e200>; 3698 compatible = "qcom,qcs615-gem-noc"; 3699 #interconnect-cells = <2>; 3700 qcom,bcm-voters = <&apps_bcm_voter>; 3701 }; 3702 3703 venus: video-codec@aa00000 { 3704 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 3705 reg = <0x0 0x0aa00000 0x0 0x100000>; 3706 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3707 3708 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3709 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3710 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3711 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3712 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3713 clock-names = "core", 3714 "iface", 3715 "bus", 3716 "vcodec0_core", 3717 "vcodec0_bus"; 3718 3719 power-domains = <&videocc VENUS_GDSC>, 3720 <&videocc VCODEC0_GDSC>, 3721 <&rpmhpd RPMHPD_CX>; 3722 power-domain-names = "venus", 3723 "vcodec0", 3724 "cx"; 3725 3726 operating-points-v2 = <&venus_opp_table>; 3727 3728 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 3729 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3730 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3731 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3732 interconnect-names = "video-mem", 3733 "cpu-cfg"; 3734 3735 iommus = <&apps_smmu 0xe60 0x20>; 3736 3737 memory-region = <&pil_video_mem>; 3738 3739 status = "disabled"; 3740 3741 venus_opp_table: opp-table { 3742 compatible = "operating-points-v2"; 3743 3744 opp-133330000 { 3745 opp-hz = /bits/ 64 <133330000>; 3746 required-opps = <&rpmhpd_opp_low_svs>; 3747 }; 3748 3749 opp-240000000 { 3750 opp-hz = /bits/ 64 <240000000>; 3751 required-opps = <&rpmhpd_opp_svs>; 3752 }; 3753 3754 opp-300000000 { 3755 opp-hz = /bits/ 64 <300000000>; 3756 required-opps = <&rpmhpd_opp_svs_l1>; 3757 }; 3758 3759 opp-380000000 { 3760 opp-hz = /bits/ 64 <380000000>; 3761 required-opps = <&rpmhpd_opp_nom>; 3762 }; 3763 3764 opp-410000000 { 3765 opp-hz = /bits/ 64 <410000000>; 3766 required-opps = <&rpmhpd_opp_nom_l1>; 3767 }; 3768 3769 opp-460000000 { 3770 opp-hz = /bits/ 64 <460000000>; 3771 required-opps = <&rpmhpd_opp_turbo>; 3772 }; 3773 }; 3774 }; 3775 3776 videocc: clock-controller@ab00000 { 3777 compatible = "qcom,qcs615-videocc"; 3778 reg = <0 0x0ab00000 0 0x10000>; 3779 3780 clocks = <&rpmhcc RPMH_CXO_CLK>, 3781 <&sleep_clk>; 3782 3783 #clock-cells = <1>; 3784 #reset-cells = <1>; 3785 #power-domain-cells = <1>; 3786 }; 3787 3788 camcc: clock-controller@ad00000 { 3789 compatible = "qcom,qcs615-camcc"; 3790 reg = <0 0x0ad00000 0 0x10000>; 3791 3792 clocks = <&rpmhcc RPMH_CXO_CLK>; 3793 3794 #clock-cells = <1>; 3795 #reset-cells = <1>; 3796 #power-domain-cells = <1>; 3797 }; 3798 3799 mdss: display-subsystem@ae00000 { 3800 compatible = "qcom,sm6150-mdss"; 3801 reg = <0x0 0x0ae00000 0x0 0x1000>; 3802 reg-names = "mdss"; 3803 3804 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3805 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3806 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3807 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3808 interconnect-names = "mdp0-mem", 3809 "cpu-cfg"; 3810 3811 power-domains = <&dispcc MDSS_CORE_GDSC>; 3812 3813 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3814 <&gcc GCC_DISP_HF_AXI_CLK>, 3815 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3816 3817 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3818 interrupt-controller; 3819 #interrupt-cells = <1>; 3820 3821 iommus = <&apps_smmu 0x800 0x0>; 3822 3823 #address-cells = <2>; 3824 #size-cells = <2>; 3825 ranges; 3826 3827 status = "disabled"; 3828 3829 mdss_mdp: display-controller@ae01000 { 3830 compatible = "qcom,sm6150-dpu"; 3831 reg = <0x0 0x0ae01000 0x0 0x8f000>, 3832 <0x0 0x0aeb0000 0x0 0x2008>; 3833 reg-names = "mdp", 3834 "vbif"; 3835 3836 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3837 <&gcc GCC_DISP_HF_AXI_CLK>, 3838 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3839 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3840 clock-names = "iface", 3841 "bus", 3842 "core", 3843 "vsync"; 3844 3845 operating-points-v2 = <&mdp_opp_table>; 3846 power-domains = <&rpmhpd RPMHPD_CX>; 3847 3848 interrupts-extended = <&mdss 0>; 3849 3850 ports { 3851 #address-cells = <1>; 3852 #size-cells = <0>; 3853 3854 port@0 { 3855 reg = <0>; 3856 3857 dpu_intf0_out: endpoint { 3858 }; 3859 }; 3860 3861 port@1 { 3862 reg = <1>; 3863 3864 dpu_intf1_out: endpoint { 3865 remote-endpoint = <&mdss_dsi0_in>; 3866 }; 3867 }; 3868 }; 3869 3870 mdp_opp_table: opp-table { 3871 compatible = "operating-points-v2"; 3872 3873 opp-192000000 { 3874 opp-hz = /bits/ 64 <192000000>; 3875 required-opps = <&rpmhpd_opp_low_svs>; 3876 }; 3877 3878 opp-256000000 { 3879 opp-hz = /bits/ 64 <256000000>; 3880 required-opps = <&rpmhpd_opp_svs>; 3881 }; 3882 3883 opp-307200000 { 3884 opp-hz = /bits/ 64 <307200000>; 3885 required-opps = <&rpmhpd_opp_nom>; 3886 }; 3887 }; 3888 }; 3889 3890 mdss_dsi0: dsi@ae94000 { 3891 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3892 reg = <0x0 0x0ae94000 0x0 0x400>; 3893 reg-names = "dsi_ctrl"; 3894 3895 interrupts-extended = <&mdss 4>; 3896 3897 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3898 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3899 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3900 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3901 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3902 <&gcc GCC_DISP_HF_AXI_CLK>; 3903 clock-names = "byte", 3904 "byte_intf", 3905 "pixel", 3906 "core", 3907 "iface", 3908 "bus"; 3909 3910 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3911 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3912 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3913 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3914 3915 operating-points-v2 = <&dsi0_opp_table>; 3916 power-domains = <&rpmhpd RPMHPD_CX>; 3917 3918 phys = <&mdss_dsi0_phy>; 3919 3920 #address-cells = <1>; 3921 #size-cells = <0>; 3922 3923 status = "disabled"; 3924 3925 dsi0_opp_table: opp-table { 3926 compatible = "operating-points-v2"; 3927 3928 opp-164000000 { 3929 opp-hz = /bits/ 64 <164000000>; 3930 required-opps = <&rpmhpd_opp_low_svs>; 3931 }; 3932 }; 3933 3934 ports { 3935 #address-cells = <1>; 3936 #size-cells = <0>; 3937 3938 port@0 { 3939 reg = <0>; 3940 3941 mdss_dsi0_in: endpoint { 3942 remote-endpoint = <&dpu_intf1_out>; 3943 }; 3944 }; 3945 3946 port@1 { 3947 reg = <1>; 3948 3949 mdss_dsi0_out: endpoint { 3950 }; 3951 }; 3952 }; 3953 }; 3954 3955 mdss_dsi0_phy: phy@ae94400 { 3956 compatible = "qcom,sm6150-dsi-phy-14nm"; 3957 reg = <0x0 0x0ae94400 0x0 0x100>, 3958 <0x0 0x0ae94500 0x0 0x300>, 3959 <0x0 0x0ae94800 0x0 0x124>; 3960 reg-names = "dsi_phy", 3961 "dsi_phy_lane", 3962 "dsi_pll"; 3963 3964 #clock-cells = <1>; 3965 #phy-cells = <0>; 3966 3967 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3968 <&rpmhcc RPMH_CXO_CLK>; 3969 clock-names = "iface", 3970 "ref"; 3971 3972 status = "disabled"; 3973 }; 3974 }; 3975 3976 dispcc: clock-controller@af00000 { 3977 compatible = "qcom,qcs615-dispcc"; 3978 reg = <0 0x0af00000 0 0x20000>; 3979 3980 clocks = <&rpmhcc RPMH_CXO_CLK>, 3981 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 3982 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3983 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3984 <0>, 3985 <0>, 3986 <0>; 3987 3988 #clock-cells = <1>; 3989 #reset-cells = <1>; 3990 #power-domain-cells = <1>; 3991 }; 3992 3993 pdc: interrupt-controller@b220000 { 3994 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 3995 reg = <0x0 0x0b220000 0x0 0x30000>, 3996 <0x0 0x17c000f0 0x0 0x64>; 3997 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3998 interrupt-parent = <&intc>; 3999 #interrupt-cells = <2>; 4000 interrupt-controller; 4001 }; 4002 4003 aoss_qmp: power-management@c300000 { 4004 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4005 reg = <0x0 0x0c300000 0x0 0x400>; 4006 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4007 mboxes = <&apss_shared 0>; 4008 4009 #clock-cells = <0>; 4010 }; 4011 4012 sram@c3f0000 { 4013 compatible = "qcom,rpmh-stats"; 4014 reg = <0x0 0x0c3f0000 0x0 0x400>; 4015 }; 4016 4017 sram@14680000 { 4018 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4019 reg = <0x0 0x14680000 0x0 0x2c000>; 4020 ranges = <0 0 0x14680000 0x2c000>; 4021 4022 #address-cells = <1>; 4023 #size-cells = <1>; 4024 4025 pil-reloc@2a94c { 4026 compatible = "qcom,pil-reloc-info"; 4027 reg = <0x2a94c 0xc8>; 4028 }; 4029 }; 4030 4031 apps_smmu: iommu@15000000 { 4032 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4033 reg = <0x0 0x15000000 0x0 0x80000>; 4034 #iommu-cells = <2>; 4035 #global-interrupts = <1>; 4036 dma-coherent; 4037 4038 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 4103 }; 4104 4105 spmi_bus: spmi@c440000 { 4106 compatible = "qcom,spmi-pmic-arb"; 4107 reg = <0x0 0x0c440000 0x0 0x1100>, 4108 <0x0 0x0c600000 0x0 0x2000000>, 4109 <0x0 0x0e600000 0x0 0x100000>, 4110 <0x0 0x0e700000 0x0 0xa0000>, 4111 <0x0 0x0c40a000 0x0 0x26000>; 4112 reg-names = "core", 4113 "chnls", 4114 "obsrvr", 4115 "intr", 4116 "cnfg"; 4117 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4118 interrupt-names = "periph_irq"; 4119 interrupt-controller; 4120 #interrupt-cells = <4>; 4121 #address-cells = <2>; 4122 #size-cells = <0>; 4123 qcom,channel = <0>; 4124 qcom,ee = <0>; 4125 }; 4126 4127 intc: interrupt-controller@17a00000 { 4128 compatible = "arm,gic-v3"; 4129 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4130 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4131 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4132 #address-cells = <0>; 4133 #interrupt-cells = <3>; 4134 interrupt-controller; 4135 #redistributor-regions = <1>; 4136 redistributor-stride = <0x0 0x20000>; 4137 }; 4138 4139 apss_shared: mailbox@17c00000 { 4140 compatible = "qcom,qcs615-apss-shared", 4141 "qcom,sdm845-apss-shared"; 4142 reg = <0x0 0x17c00000 0x0 0x1000>; 4143 #mbox-cells = <1>; 4144 }; 4145 4146 watchdog: watchdog@17c10000 { 4147 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4148 reg = <0x0 0x17c10000 0x0 0x1000>; 4149 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4150 clocks = <&sleep_clk>; 4151 }; 4152 4153 timer@17c20000 { 4154 compatible = "arm,armv7-timer-mem"; 4155 reg = <0x0 0x17c20000 0x0 0x1000>; 4156 ranges = <0 0 0 0x20000000>; 4157 #address-cells = <1>; 4158 #size-cells = <1>; 4159 4160 frame@17c21000 { 4161 reg = <0x17c21000 0x1000>, 4162 <0x17c22000 0x1000>; 4163 frame-number = <0>; 4164 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4166 }; 4167 4168 frame@17c23000 { 4169 reg = <0x17c23000 0x1000>; 4170 frame-number = <1>; 4171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4172 status = "disabled"; 4173 }; 4174 4175 frame@17c25000 { 4176 reg = <0x17c25000 0x1000>; 4177 frame-number = <2>; 4178 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4179 status = "disabled"; 4180 }; 4181 4182 frame@17c27000 { 4183 reg = <0x17c27000 0x1000>; 4184 frame-number = <3>; 4185 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4186 status = "disabled"; 4187 }; 4188 4189 frame@17c29000 { 4190 reg = <0x17c29000 0x1000>; 4191 frame-number = <4>; 4192 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4193 status = "disabled"; 4194 }; 4195 4196 frame@17c2b000 { 4197 reg = <0x17c2b000 0x1000>; 4198 frame-number = <5>; 4199 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4200 status = "disabled"; 4201 }; 4202 4203 frame@17c2d000 { 4204 reg = <0x17c2d000 0x1000>; 4205 frame-number = <6>; 4206 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4207 status = "disabled"; 4208 }; 4209 }; 4210 4211 apps_rsc: rsc@18200000 { 4212 compatible = "qcom,rpmh-rsc"; 4213 reg = <0x0 0x18200000 0x0 0x10000>, 4214 <0x0 0x18210000 0x0 0x10000>, 4215 <0x0 0x18220000 0x0 0x10000>; 4216 reg-names = "drv-0", 4217 "drv-1", 4218 "drv-2"; 4219 4220 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4223 4224 qcom,drv-id = <2>; 4225 qcom,tcs-offset = <0xd00>; 4226 qcom,tcs-config = <ACTIVE_TCS 2>, 4227 <SLEEP_TCS 3>, 4228 <WAKE_TCS 3>, 4229 <CONTROL_TCS 1>; 4230 4231 label = "apps_rsc"; 4232 power-domains = <&cluster_pd>; 4233 4234 apps_bcm_voter: bcm-voter { 4235 compatible = "qcom,bcm-voter"; 4236 }; 4237 4238 rpmhcc: clock-controller { 4239 compatible = "qcom,qcs615-rpmh-clk"; 4240 clocks = <&xo_board_clk>; 4241 clock-names = "xo"; 4242 4243 #clock-cells = <1>; 4244 }; 4245 4246 rpmhpd: power-controller { 4247 compatible = "qcom,qcs615-rpmhpd"; 4248 #power-domain-cells = <1>; 4249 operating-points-v2 = <&rpmhpd_opp_table>; 4250 4251 rpmhpd_opp_table: opp-table { 4252 compatible = "operating-points-v2"; 4253 4254 rpmhpd_opp_ret: opp-0 { 4255 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4256 }; 4257 4258 rpmhpd_opp_min_svs: opp-1 { 4259 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4260 }; 4261 4262 rpmhpd_opp_low_svs: opp-2 { 4263 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4264 }; 4265 4266 rpmhpd_opp_svs: opp-3 { 4267 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4268 }; 4269 4270 rpmhpd_opp_svs_l1: opp-4 { 4271 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4272 }; 4273 4274 rpmhpd_opp_nom: opp-5 { 4275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4276 }; 4277 4278 rpmhpd_opp_nom_l1: opp-6 { 4279 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4280 }; 4281 4282 rpmhpd_opp_nom_l2: opp-7 { 4283 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4284 }; 4285 4286 rpmhpd_opp_turbo: opp-8 { 4287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4288 }; 4289 4290 rpmhpd_opp_turbo_l1: opp-9 { 4291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4292 }; 4293 }; 4294 }; 4295 }; 4296 4297 osm_l3: interconnect@18321000 { 4298 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4299 reg = <0x0 0x18321000 0x0 0x1400>; 4300 4301 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4302 clock-names = "xo", "alternate"; 4303 4304 #interconnect-cells = <1>; 4305 }; 4306 4307 usb_1_hsphy: phy@88e2000 { 4308 compatible = "qcom,qcs615-qusb2-phy"; 4309 reg = <0x0 0x88e2000 0x0 0x180>; 4310 4311 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 4312 clock-names = "cfg_ahb", "ref"; 4313 4314 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4315 nvmem-cells = <&qusb2_hstx_trim>; 4316 4317 #phy-cells = <0>; 4318 4319 status = "disabled"; 4320 }; 4321 4322 usb_hsphy_2: phy@88e3000 { 4323 compatible = "qcom,qcs615-qusb2-phy"; 4324 reg = <0x0 0x088e3000 0x0 0x180>; 4325 4326 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4327 <&rpmhcc RPMH_CXO_CLK>; 4328 clock-names = "cfg_ahb", 4329 "ref"; 4330 4331 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4332 4333 #phy-cells = <0>; 4334 4335 status = "disabled"; 4336 }; 4337 4338 usb_qmpphy: phy@88e6000 { 4339 compatible = "qcom,qcs615-qmp-usb3-phy"; 4340 reg = <0x0 0x88e6000 0x0 0x1000>; 4341 4342 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4343 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4344 <&gcc GCC_AHB2PHY_WEST_CLK>, 4345 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4346 clock-names = "aux", 4347 "ref", 4348 "cfg_ahb", 4349 "pipe"; 4350 4351 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4352 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4353 reset-names = "phy", "phy_phy"; 4354 4355 qcom,tcsr-reg = <&tcsr 0xb244>; 4356 4357 clock-output-names = "usb3_phy_pipe_clk_src"; 4358 #clock-cells = <0>; 4359 4360 #phy-cells = <0>; 4361 4362 status = "disabled"; 4363 }; 4364 4365 usb_1: usb@a6f8800 { 4366 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4367 reg = <0x0 0x0a6f8800 0x0 0x400>; 4368 4369 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4370 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4371 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4372 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4373 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4374 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 4375 clock-names = "cfg_noc", 4376 "core", 4377 "iface", 4378 "sleep", 4379 "mock_utmi", 4380 "xo"; 4381 4382 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4383 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4384 assigned-clock-rates = <19200000>, <200000000>; 4385 4386 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4387 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4388 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 4389 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4390 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 4391 interrupt-names = "pwr_event", 4392 "hs_phy_irq", 4393 "dp_hs_phy_irq", 4394 "dm_hs_phy_irq", 4395 "ss_phy_irq"; 4396 4397 power-domains = <&gcc USB30_PRIM_GDSC>; 4398 required-opps = <&rpmhpd_opp_nom>; 4399 4400 resets = <&gcc GCC_USB30_PRIM_BCR>; 4401 4402 #address-cells = <2>; 4403 #size-cells = <2>; 4404 ranges; 4405 4406 status = "disabled"; 4407 4408 usb_1_dwc3: usb@a600000 { 4409 compatible = "snps,dwc3"; 4410 reg = <0x0 0x0a600000 0x0 0xcd00>; 4411 4412 iommus = <&apps_smmu 0x140 0x0>; 4413 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4414 4415 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4416 phy-names = "usb2-phy", "usb3-phy"; 4417 4418 snps,dis-u1-entry-quirk; 4419 snps,dis-u2-entry-quirk; 4420 snps,dis_u2_susphy_quirk; 4421 snps,dis_u3_susphy_quirk; 4422 snps,dis_enblslpm_quirk; 4423 snps,has-lpm-erratum; 4424 snps,hird-threshold = /bits/ 8 <0x10>; 4425 snps,usb3_lpm_capable; 4426 }; 4427 }; 4428 4429 usb_2: usb@a8f8800 { 4430 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4431 reg = <0x0 0x0a8f8800 0x0 0x400>; 4432 4433 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 4434 <&gcc GCC_USB20_SEC_MASTER_CLK>, 4435 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 4436 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 4437 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4438 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 4439 clock-names = "cfg_noc", 4440 "core", 4441 "iface", 4442 "sleep", 4443 "mock_utmi", 4444 "xo"; 4445 4446 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4447 <&gcc GCC_USB20_SEC_MASTER_CLK>; 4448 assigned-clock-rates = <19200000>, <200000000>; 4449 4450 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, 4451 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4452 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4453 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 4454 interrupt-names = "pwr_event", 4455 "hs_phy_irq", 4456 "dp_hs_phy_irq", 4457 "dm_hs_phy_irq"; 4458 4459 power-domains = <&gcc USB20_SEC_GDSC>; 4460 required-opps = <&rpmhpd_opp_nom>; 4461 4462 resets = <&gcc GCC_USB20_SEC_BCR>; 4463 4464 qcom,select-utmi-as-pipe-clk; 4465 4466 #address-cells = <2>; 4467 #size-cells = <2>; 4468 ranges; 4469 4470 status = "disabled"; 4471 4472 usb_2_dwc3: usb@a800000 { 4473 compatible = "snps,dwc3"; 4474 reg = <0x0 0x0a800000 0x0 0xcd00>; 4475 4476 iommus = <&apps_smmu 0xe0 0x0>; 4477 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; 4478 4479 phys = <&usb_hsphy_2>; 4480 phy-names = "usb2-phy"; 4481 4482 snps,dis_u2_susphy_quirk; 4483 snps,dis_u3_susphy_quirk; 4484 snps,dis_enblslpm_quirk; 4485 snps,has-lpm-erratum; 4486 snps,hird-threshold = /bits/ 8 <0x10>; 4487 4488 maximum-speed = "high-speed"; 4489 }; 4490 }; 4491 4492 tsens0: thermal-sensor@c263000 { 4493 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 4494 reg = <0x0 0x0c263000 0x0 0x1000>, 4495 <0x0 0x0c222000 0x0 0x1000>; 4496 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4497 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4498 interrupt-names = "uplow", "critical"; 4499 #qcom,sensors = <16>; 4500 #thermal-sensor-cells = <1>; 4501 }; 4502 4503 remoteproc_adsp: remoteproc@62400000 { 4504 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 4505 reg = <0x0 0x62400000 0x0 0x4040>; 4506 4507 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4508 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4509 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4510 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4511 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4512 interrupt-names = "wdog", 4513 "fatal", 4514 "ready", 4515 "handover", 4516 "stop-ack"; 4517 4518 clocks = <&rpmhcc RPMH_CXO_CLK>; 4519 clock-names = "xo"; 4520 4521 power-domains = <&rpmhpd RPMHPD_CX>; 4522 power-domain-names = "cx"; 4523 4524 memory-region = <&rproc_adsp_mem>; 4525 4526 qcom,qmp = <&aoss_qmp>; 4527 4528 qcom,smem-states = <&adsp_smp2p_out 0>; 4529 qcom,smem-state-names = "stop"; 4530 4531 status = "disabled"; 4532 4533 glink_edge: glink-edge { 4534 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 4535 mboxes = <&apss_shared 24>; 4536 label = "lpass"; 4537 qcom,remote-pid = <2>; 4538 4539 fastrpc { 4540 compatible = "qcom,fastrpc"; 4541 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4542 label = "adsp"; 4543 #address-cells = <1>; 4544 #size-cells = <0>; 4545 4546 compute-cb@3 { 4547 compatible = "qcom,fastrpc-compute-cb"; 4548 reg = <3>; 4549 iommus = <&apps_smmu 0x1723 0x0>; 4550 dma-coherent; 4551 }; 4552 4553 compute-cb@4 { 4554 compatible = "qcom,fastrpc-compute-cb"; 4555 reg = <4>; 4556 iommus = <&apps_smmu 0x1724 0x0>; 4557 dma-coherent; 4558 }; 4559 4560 compute-cb@5 { 4561 compatible = "qcom,fastrpc-compute-cb"; 4562 reg = <5>; 4563 iommus = <&apps_smmu 0x1725 0x0>; 4564 dma-coherent; 4565 }; 4566 4567 compute-cb@6 { 4568 compatible = "qcom,fastrpc-compute-cb"; 4569 reg = <6>; 4570 iommus = <&apps_smmu 0x1726 0x0>; 4571 qcom,nsessions = <5>; 4572 dma-coherent; 4573 }; 4574 }; 4575 }; 4576 }; 4577 4578 cpufreq_hw: cpufreq@18323000 { 4579 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 4580 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 4581 reg-names = "freq-domain0", "freq-domain1"; 4582 4583 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4584 clock-names = "xo", "alternate"; 4585 4586 #freq-domain-cells = <1>; 4587 #clock-cells = <1>; 4588 }; 4589 }; 4590 4591 arch_timer: timer { 4592 compatible = "arm,armv8-timer"; 4593 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4594 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4595 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4596 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4597 }; 4598 4599 thermal-zones { 4600 aoss-thermal { 4601 thermal-sensors = <&tsens0 0>; 4602 4603 trips { 4604 aoss-critical { 4605 temperature = <115000>; 4606 hysteresis = <1000>; 4607 type = "critical"; 4608 }; 4609 }; 4610 }; 4611 4612 cpuss-0-thermal { 4613 thermal-sensors = <&tsens0 1>; 4614 4615 trips { 4616 cpuss0-critical { 4617 temperature = <115000>; 4618 hysteresis = <1000>; 4619 type = "critical"; 4620 }; 4621 }; 4622 }; 4623 4624 cpuss-1-thermal { 4625 thermal-sensors = <&tsens0 2>; 4626 4627 trips { 4628 cpuss1-critical { 4629 temperature = <115000>; 4630 hysteresis = <1000>; 4631 type = "critical"; 4632 }; 4633 }; 4634 }; 4635 4636 cpuss-2-thermal { 4637 thermal-sensors = <&tsens0 3>; 4638 4639 trips { 4640 cpuss2-critical { 4641 temperature = <115000>; 4642 hysteresis = <1000>; 4643 type = "critical"; 4644 }; 4645 }; 4646 }; 4647 4648 cpuss-3-thermal { 4649 thermal-sensors = <&tsens0 4>; 4650 4651 trips { 4652 cpuss3-critical { 4653 temperature = <115000>; 4654 hysteresis = <1000>; 4655 type = "critical"; 4656 }; 4657 }; 4658 }; 4659 4660 cpu-1-0-thermal { 4661 thermal-sensors = <&tsens0 5>; 4662 4663 trips { 4664 cpu-critical { 4665 temperature = <115000>; 4666 hysteresis = <1000>; 4667 type = "critical"; 4668 }; 4669 }; 4670 }; 4671 4672 cpu-1-1-thermal { 4673 thermal-sensors = <&tsens0 6>; 4674 4675 trips { 4676 cpu-critical { 4677 temperature = <115000>; 4678 hysteresis = <1000>; 4679 type = "critical"; 4680 }; 4681 }; 4682 }; 4683 4684 cpu-1-2-thermal { 4685 thermal-sensors = <&tsens0 7>; 4686 4687 trips { 4688 cpu-critical { 4689 temperature = <115000>; 4690 hysteresis = <1000>; 4691 type = "critical"; 4692 }; 4693 }; 4694 }; 4695 4696 cpu-1-3-thermal { 4697 thermal-sensors = <&tsens0 8>; 4698 4699 trips { 4700 cpu-critical { 4701 temperature = <115000>; 4702 hysteresis = <1000>; 4703 type = "critical"; 4704 }; 4705 }; 4706 }; 4707 4708 gpu-thermal { 4709 thermal-sensors = <&tsens0 9>; 4710 4711 trips { 4712 gpu-critical { 4713 temperature = <115000>; 4714 hysteresis = <1000>; 4715 type = "critical"; 4716 }; 4717 }; 4718 }; 4719 4720 q6-hvx-thermal { 4721 thermal-sensors = <&tsens0 10>; 4722 4723 trips { 4724 q6-hvx-critical { 4725 temperature = <115000>; 4726 hysteresis = <1000>; 4727 type = "critical"; 4728 }; 4729 }; 4730 }; 4731 4732 mdm-core-thermal { 4733 thermal-sensors = <&tsens0 11>; 4734 4735 trips { 4736 mdm-core-critical { 4737 temperature = <115000>; 4738 hysteresis = <1000>; 4739 type = "critical"; 4740 }; 4741 }; 4742 }; 4743 4744 camera-thermal { 4745 thermal-sensors = <&tsens0 12>; 4746 4747 trips { 4748 camera-critical { 4749 temperature = <115000>; 4750 hysteresis = <1000>; 4751 type = "critical"; 4752 }; 4753 }; 4754 }; 4755 4756 wlan-thermal { 4757 thermal-sensors = <&tsens0 13>; 4758 4759 trips { 4760 wlan-critical { 4761 temperature = <115000>; 4762 hysteresis = <1000>; 4763 type = "critical"; 4764 }; 4765 }; 4766 }; 4767 4768 display-thermal { 4769 thermal-sensors = <&tsens0 14>; 4770 4771 trips { 4772 display-critical { 4773 temperature = <115000>; 4774 hysteresis = <1000>; 4775 type = "critical"; 4776 }; 4777 }; 4778 }; 4779 4780 video-thermal { 4781 thermal-sensors = <&tsens0 15>; 4782 4783 trips { 4784 video-critical { 4785 temperature = <115000>; 4786 hysteresis = <1000>; 4787 type = "critical"; 4788 }; 4789 }; 4790 }; 4791 }; 4792}; 4793