1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 10#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interconnect/qcom,qcm2290.h> 17#include <dt-bindings/interconnect/qcom,rpm-icc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 #clock-cells = <0>; 38 }; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0 0x0>; 49 clocks = <&cpufreq_hw 0>; 50 capacity-dmips-mhz = <1024>; 51 dynamic-power-coefficient = <100>; 52 enable-method = "psci"; 53 next-level-cache = <&L2_0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 L2_0: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 }; 62 }; 63 64 CPU1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x1>; 68 clocks = <&cpufreq_hw 0>; 69 capacity-dmips-mhz = <1024>; 70 dynamic-power-coefficient = <100>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 qcom,freq-domain = <&cpufreq_hw 0>; 74 power-domains = <&CPU_PD1>; 75 power-domain-names = "psci"; 76 }; 77 78 CPU2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cpufreq_hw 0>; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 enable-method = "psci"; 86 next-level-cache = <&L2_0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 power-domains = <&CPU_PD2>; 89 power-domain-names = "psci"; 90 }; 91 92 CPU3: cpu@3 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x0 0x3>; 96 clocks = <&cpufreq_hw 0>; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 power-domains = <&CPU_PD3>; 103 power-domain-names = "psci"; 104 }; 105 106 cpu-map { 107 cluster0 { 108 core0 { 109 cpu = <&CPU0>; 110 }; 111 112 core1 { 113 cpu = <&CPU1>; 114 }; 115 116 core2 { 117 cpu = <&CPU2>; 118 }; 119 120 core3 { 121 cpu = <&CPU3>; 122 }; 123 }; 124 }; 125 126 domain-idle-states { 127 CLUSTER_SLEEP: cluster-sleep-0 { 128 compatible = "domain-idle-state"; 129 arm,psci-suspend-param = <0x41000043>; 130 entry-latency-us = <800>; 131 exit-latency-us = <2118>; 132 min-residency-us = <7376>; 133 }; 134 }; 135 136 idle-states { 137 entry-method = "psci"; 138 139 CPU_SLEEP: cpu-sleep-0 { 140 compatible = "arm,idle-state"; 141 idle-state-name = "power-collapse"; 142 arm,psci-suspend-param = <0x40000003>; 143 entry-latency-us = <290>; 144 exit-latency-us = <376>; 145 min-residency-us = <1182>; 146 local-timer-stop; 147 }; 148 }; 149 }; 150 151 firmware { 152 scm: scm { 153 compatible = "qcom,scm-qcm2290", "qcom,scm"; 154 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 155 clock-names = "core"; 156 #reset-cells = <1>; 157 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 158 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 159 }; 160 }; 161 162 memory@40000000 { 163 device_type = "memory"; 164 /* We expect the bootloader to fill in the size */ 165 reg = <0 0x40000000 0 0>; 166 }; 167 168 pmu { 169 compatible = "arm,cortex-a53-pmu"; 170 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 171 }; 172 173 psci { 174 compatible = "arm,psci-1.0"; 175 method = "smc"; 176 177 CPU_PD0: power-domain-cpu0 { 178 #power-domain-cells = <0>; 179 power-domains = <&CLUSTER_PD>; 180 domain-idle-states = <&CPU_SLEEP>; 181 }; 182 183 CPU_PD1: power-domain-cpu1 { 184 #power-domain-cells = <0>; 185 power-domains = <&CLUSTER_PD>; 186 domain-idle-states = <&CPU_SLEEP>; 187 }; 188 189 CPU_PD2: power-domain-cpu2 { 190 #power-domain-cells = <0>; 191 power-domains = <&CLUSTER_PD>; 192 domain-idle-states = <&CPU_SLEEP>; 193 }; 194 195 CPU_PD3: power-domain-cpu3 { 196 #power-domain-cells = <0>; 197 power-domains = <&CLUSTER_PD>; 198 domain-idle-states = <&CPU_SLEEP>; 199 }; 200 201 CLUSTER_PD: power-domain-cpu-cluster { 202 #power-domain-cells = <0>; 203 power-domains = <&mpm>; 204 domain-idle-states = <&CLUSTER_SLEEP>; 205 }; 206 }; 207 208 rpm: remoteproc { 209 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 210 211 glink-edge { 212 compatible = "qcom,glink-rpm"; 213 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 214 qcom,rpm-msg-ram = <&rpm_msg_ram>; 215 mboxes = <&apcs_glb 0>; 216 217 rpm_requests: rpm-requests { 218 compatible = "qcom,rpm-qcm2290"; 219 qcom,glink-channels = "rpm_requests"; 220 221 rpmcc: clock-controller { 222 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 223 clocks = <&xo_board>; 224 clock-names = "xo"; 225 #clock-cells = <1>; 226 }; 227 228 rpmpd: power-controller { 229 compatible = "qcom,qcm2290-rpmpd"; 230 #power-domain-cells = <1>; 231 operating-points-v2 = <&rpmpd_opp_table>; 232 233 rpmpd_opp_table: opp-table { 234 compatible = "operating-points-v2"; 235 236 rpmpd_opp_min_svs: opp1 { 237 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 238 }; 239 240 rpmpd_opp_low_svs: opp2 { 241 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 242 }; 243 244 rpmpd_opp_svs: opp3 { 245 opp-level = <RPM_SMD_LEVEL_SVS>; 246 }; 247 248 rpmpd_opp_svs_plus: opp4 { 249 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 250 }; 251 252 rpmpd_opp_nom: opp5 { 253 opp-level = <RPM_SMD_LEVEL_NOM>; 254 }; 255 256 rpmpd_opp_nom_plus: opp6 { 257 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 258 }; 259 260 rpmpd_opp_turbo: opp7 { 261 opp-level = <RPM_SMD_LEVEL_TURBO>; 262 }; 263 264 rpmpd_opp_turbo_plus: opp8 { 265 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 266 }; 267 }; 268 }; 269 }; 270 }; 271 272 mpm: interrupt-controller { 273 compatible = "qcom,mpm"; 274 qcom,rpm-msg-ram = <&apss_mpm>; 275 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 276 mboxes = <&apcs_glb 1>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 #power-domain-cells = <0>; 280 interrupt-parent = <&intc>; 281 qcom,mpm-pin-count = <96>; 282 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 283 <5 296>, /* Soundwire master_irq */ 284 <12 422>, /* DWC3 ss_phy_irq */ 285 <24 79>, /* Soundwire wake_irq */ 286 <86 183>, /* MPM wake, SPMI */ 287 <90 260>; /* QUSB2_PHY DP+DM */ 288 }; 289 }; 290 291 reserved_memory: reserved-memory { 292 #address-cells = <2>; 293 #size-cells = <2>; 294 ranges; 295 296 hyp_mem: hyp@45700000 { 297 reg = <0x0 0x45700000 0x0 0x600000>; 298 no-map; 299 }; 300 301 xbl_aop_mem: xbl-aop@45e00000 { 302 reg = <0x0 0x45e00000 0x0 0x140000>; 303 no-map; 304 }; 305 306 sec_apps_mem: sec-apps@45fff000 { 307 reg = <0x0 0x45fff000 0x0 0x1000>; 308 no-map; 309 }; 310 311 smem_mem: smem@46000000 { 312 compatible = "qcom,smem"; 313 reg = <0x0 0x46000000 0x0 0x200000>; 314 no-map; 315 316 hwlocks = <&tcsr_mutex 3>; 317 qcom,rpm-msg-ram = <&rpm_msg_ram>; 318 }; 319 320 pil_modem_mem: modem@4ab00000 { 321 reg = <0x0 0x4ab00000 0x0 0x6900000>; 322 no-map; 323 }; 324 325 pil_video_mem: video@51400000 { 326 reg = <0x0 0x51400000 0x0 0x500000>; 327 no-map; 328 }; 329 330 wlan_msa_mem: wlan-msa@51900000 { 331 reg = <0x0 0x51900000 0x0 0x100000>; 332 no-map; 333 }; 334 335 pil_adsp_mem: adsp@51a00000 { 336 reg = <0x0 0x51a00000 0x0 0x1c00000>; 337 no-map; 338 }; 339 340 pil_ipa_fw_mem: ipa-fw@53600000 { 341 reg = <0x0 0x53600000 0x0 0x10000>; 342 no-map; 343 }; 344 345 pil_ipa_gsi_mem: ipa-gsi@53610000 { 346 reg = <0x0 0x53610000 0x0 0x5000>; 347 no-map; 348 }; 349 350 pil_gpu_mem: zap@53615000 { 351 compatible = "shared-dma-pool"; 352 reg = <0x0 0x53615000 0x0 0x2000>; 353 no-map; 354 }; 355 356 cont_splash_memory: framebuffer@5c000000 { 357 reg = <0x0 0x5c000000 0x0 0x00f00000>; 358 no-map; 359 }; 360 361 dfps_data_memory: dpfs-data@5cf00000 { 362 reg = <0x0 0x5cf00000 0x0 0x0100000>; 363 no-map; 364 }; 365 366 removed_mem: reserved@60000000 { 367 reg = <0x0 0x60000000 0x0 0x3900000>; 368 no-map; 369 }; 370 371 rmtfs_mem: memory@89b01000 { 372 compatible = "qcom,rmtfs-mem"; 373 reg = <0x0 0x89b01000 0x0 0x200000>; 374 no-map; 375 376 qcom,client-id = <1>; 377 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 378 }; 379 }; 380 381 smp2p-adsp { 382 compatible = "qcom,smp2p"; 383 qcom,smem = <443>, <429>; 384 385 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 386 387 mboxes = <&apcs_glb 10>; 388 389 qcom,local-pid = <0>; 390 qcom,remote-pid = <2>; 391 392 adsp_smp2p_out: master-kernel { 393 qcom,entry-name = "master-kernel"; 394 #qcom,smem-state-cells = <1>; 395 }; 396 397 adsp_smp2p_in: slave-kernel { 398 qcom,entry-name = "slave-kernel"; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 }; 402 }; 403 404 smp2p-mpss { 405 compatible = "qcom,smp2p"; 406 qcom,smem = <435>, <428>; 407 408 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 409 410 mboxes = <&apcs_glb 14>; 411 412 qcom,local-pid = <0>; 413 qcom,remote-pid = <1>; 414 415 modem_smp2p_out: master-kernel { 416 qcom,entry-name = "master-kernel"; 417 #qcom,smem-state-cells = <1>; 418 }; 419 420 modem_smp2p_in: slave-kernel { 421 qcom,entry-name = "slave-kernel"; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 426 wlan_smp2p_in: wlan-wpss-to-ap { 427 qcom,entry-name = "wlan"; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 }; 431 }; 432 433 soc: soc@0 { 434 compatible = "simple-bus"; 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges = <0 0 0 0 0x10 0>; 438 dma-ranges = <0 0 0 0 0x10 0>; 439 440 tcsr_mutex: hwlock@340000 { 441 compatible = "qcom,tcsr-mutex"; 442 reg = <0x0 0x00340000 0x0 0x20000>; 443 #hwlock-cells = <1>; 444 }; 445 446 tcsr_regs: syscon@3c0000 { 447 compatible = "qcom,qcm2290-tcsr", "syscon"; 448 reg = <0x0 0x003c0000 0x0 0x40000>; 449 }; 450 451 tlmm: pinctrl@500000 { 452 compatible = "qcom,qcm2290-tlmm"; 453 reg = <0x0 0x00500000 0x0 0x300000>; 454 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 455 gpio-controller; 456 gpio-ranges = <&tlmm 0 0 127>; 457 wakeup-parent = <&mpm>; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 462 qup_i2c0_default: qup-i2c0-default-state { 463 pins = "gpio0", "gpio1"; 464 function = "qup0"; 465 drive-strength = <2>; 466 bias-pull-up; 467 }; 468 469 qup_i2c1_default: qup-i2c1-default-state { 470 pins = "gpio4", "gpio5"; 471 function = "qup1"; 472 drive-strength = <2>; 473 bias-pull-up; 474 }; 475 476 qup_i2c2_default: qup-i2c2-default-state { 477 pins = "gpio6", "gpio7"; 478 function = "qup2"; 479 drive-strength = <2>; 480 bias-pull-up; 481 }; 482 483 qup_i2c3_default: qup-i2c3-default-state { 484 pins = "gpio8", "gpio9"; 485 function = "qup3"; 486 drive-strength = <2>; 487 bias-pull-up; 488 }; 489 490 qup_i2c4_default: qup-i2c4-default-state { 491 pins = "gpio12", "gpio13"; 492 function = "qup4"; 493 drive-strength = <2>; 494 bias-pull-up; 495 }; 496 497 qup_i2c5_default: qup-i2c5-default-state { 498 pins = "gpio14", "gpio15"; 499 function = "qup5"; 500 drive-strength = <2>; 501 bias-pull-up; 502 }; 503 504 qup_spi0_default: qup-spi0-default-state { 505 pins = "gpio0", "gpio1","gpio2", "gpio3"; 506 function = "qup0"; 507 drive-strength = <2>; 508 bias-pull-up; 509 }; 510 511 qup_spi1_default: qup-spi1-default-state { 512 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 513 function = "qup1"; 514 drive-strength = <2>; 515 bias-pull-up; 516 }; 517 518 qup_spi2_default: qup-spi2-default-state { 519 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 520 function = "qup2"; 521 drive-strength = <2>; 522 bias-pull-up; 523 }; 524 525 qup_spi3_default: qup-spi3-default-state { 526 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 527 function = "qup3"; 528 drive-strength = <2>; 529 bias-pull-up; 530 }; 531 532 qup_spi4_default: qup-spi4-default-state { 533 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 534 function = "qup4"; 535 drive-strength = <2>; 536 bias-pull-up; 537 }; 538 539 qup_spi5_default: qup-spi5-default-state { 540 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 541 function = "qup5"; 542 drive-strength = <2>; 543 bias-pull-up; 544 }; 545 546 qup_uart0_default: qup-uart0-default-state { 547 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 548 function = "qup0"; 549 drive-strength = <2>; 550 bias-disable; 551 }; 552 553 qup_uart4_default: qup-uart4-default-state { 554 pins = "gpio12", "gpio13"; 555 function = "qup4"; 556 drive-strength = <2>; 557 bias-disable; 558 }; 559 560 sdc1_state_on: sdc1-on-state { 561 clk-pins { 562 pins = "sdc1_clk"; 563 drive-strength = <16>; 564 bias-disable; 565 }; 566 567 cmd-pins { 568 pins = "sdc1_cmd"; 569 drive-strength = <10>; 570 bias-pull-up; 571 }; 572 573 data-pins { 574 pins = "sdc1_data"; 575 drive-strength = <10>; 576 bias-pull-up; 577 }; 578 579 rclk-pins { 580 pins = "sdc1_rclk"; 581 bias-pull-down; 582 }; 583 }; 584 585 sdc1_state_off: sdc1-off-state { 586 clk-pins { 587 pins = "sdc1_clk"; 588 drive-strength = <2>; 589 bias-disable; 590 }; 591 592 cmd-pins { 593 pins = "sdc1_cmd"; 594 drive-strength = <2>; 595 bias-pull-up; 596 }; 597 598 data-pins { 599 pins = "sdc1_data"; 600 drive-strength = <2>; 601 bias-pull-up; 602 }; 603 604 rclk-pins { 605 pins = "sdc1_rclk"; 606 bias-pull-down; 607 }; 608 }; 609 610 sdc2_state_on: sdc2-on-state { 611 clk-pins { 612 pins = "sdc2_clk"; 613 drive-strength = <16>; 614 bias-disable; 615 }; 616 617 cmd-pins { 618 pins = "sdc2_cmd"; 619 drive-strength = <10>; 620 bias-pull-up; 621 }; 622 623 data-pins { 624 pins = "sdc2_data"; 625 drive-strength = <10>; 626 bias-pull-up; 627 }; 628 }; 629 630 sdc2_state_off: sdc2-off-state { 631 clk-pins { 632 pins = "sdc2_clk"; 633 drive-strength = <2>; 634 bias-disable; 635 }; 636 637 cmd-pins { 638 pins = "sdc2_cmd"; 639 drive-strength = <2>; 640 bias-pull-up; 641 }; 642 643 data-pins { 644 pins = "sdc2_data"; 645 drive-strength = <2>; 646 bias-pull-up; 647 }; 648 }; 649 }; 650 651 gcc: clock-controller@1400000 { 652 compatible = "qcom,gcc-qcm2290"; 653 reg = <0x0 0x01400000 0x0 0x1f0000>; 654 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 655 clock-names = "bi_tcxo", "sleep_clk"; 656 #clock-cells = <1>; 657 #reset-cells = <1>; 658 #power-domain-cells = <1>; 659 }; 660 661 usb_hsphy: phy@1613000 { 662 compatible = "qcom,qcm2290-qusb2-phy"; 663 reg = <0x0 0x01613000 0x0 0x180>; 664 665 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 666 <&rpmcc RPM_SMD_XO_CLK_SRC>; 667 clock-names = "cfg_ahb", "ref"; 668 669 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 670 nvmem-cells = <&qusb2_hstx_trim>; 671 #phy-cells = <0>; 672 673 status = "disabled"; 674 }; 675 676 usb_qmpphy: phy@1615000 { 677 compatible = "qcom,qcm2290-qmp-usb3-phy"; 678 reg = <0x0 0x01615000 0x0 0x1000>; 679 680 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 681 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 682 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 683 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 684 clock-names = "cfg_ahb", 685 "ref", 686 "com_aux", 687 "pipe"; 688 689 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 690 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 691 reset-names = "phy", 692 "phy_phy"; 693 694 #clock-cells = <0>; 695 clock-output-names = "usb3_phy_pipe_clk_src"; 696 697 #phy-cells = <0>; 698 orientation-switch; 699 700 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 701 702 status = "disabled"; 703 704 ports { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 port@0 { 709 reg = <0>; 710 711 usb_qmpphy_out: endpoint { 712 }; 713 }; 714 715 port@1 { 716 reg = <1>; 717 718 usb_qmpphy_usb_ss_in: endpoint { 719 remote-endpoint = <&usb_dwc3_ss>; 720 }; 721 }; 722 }; 723 }; 724 725 system_noc: interconnect@1880000 { 726 compatible = "qcom,qcm2290-snoc"; 727 reg = <0x0 0x01880000 0x0 0x60200>; 728 #interconnect-cells = <2>; 729 730 qup_virt: interconnect-qup { 731 compatible = "qcom,qcm2290-qup-virt"; 732 #interconnect-cells = <2>; 733 }; 734 735 mmnrt_virt: interconnect-mmnrt { 736 compatible = "qcom,qcm2290-mmnrt-virt"; 737 #interconnect-cells = <2>; 738 }; 739 740 mmrt_virt: interconnect-mmrt { 741 compatible = "qcom,qcm2290-mmrt-virt"; 742 #interconnect-cells = <2>; 743 }; 744 }; 745 746 config_noc: interconnect@1900000 { 747 compatible = "qcom,qcm2290-cnoc"; 748 reg = <0x0 0x01900000 0x0 0x8200>; 749 #interconnect-cells = <2>; 750 }; 751 752 qfprom@1b44000 { 753 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 754 reg = <0x0 0x01b44000 0x0 0x3000>; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 758 qusb2_hstx_trim: hstx-trim@25b { 759 reg = <0x25b 0x1>; 760 bits = <1 4>; 761 }; 762 763 gpu_speed_bin: gpu-speed-bin@2006 { 764 reg = <0x2006 0x2>; 765 bits = <5 8>; 766 }; 767 }; 768 769 pmu@1b8e300 { 770 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 771 reg = <0x0 0x01b8e300 0x0 0x600>; 772 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 773 774 operating-points-v2 = <&cpu_bwmon_opp_table>; 775 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 776 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 777 778 cpu_bwmon_opp_table: opp-table { 779 compatible = "operating-points-v2"; 780 781 opp-0 { 782 opp-peak-kBps = <(200 * 4 * 1000)>; 783 }; 784 785 opp-1 { 786 opp-peak-kBps = <(300 * 4 * 1000)>; 787 }; 788 789 opp-2 { 790 opp-peak-kBps = <(451 * 4 * 1000)>; 791 }; 792 793 opp-3 { 794 opp-peak-kBps = <(547 * 4 * 1000)>; 795 }; 796 797 opp-4 { 798 opp-peak-kBps = <(681 * 4 * 1000)>; 799 }; 800 801 opp-5 { 802 opp-peak-kBps = <(768 * 4 * 1000)>; 803 }; 804 805 opp-6 { 806 opp-peak-kBps = <(1017 * 4 * 1000)>; 807 }; 808 809 opp-7 { 810 opp-peak-kBps = <(1353 * 4 * 1000)>; 811 }; 812 813 opp-8 { 814 opp-peak-kBps = <(1555 * 4 * 1000)>; 815 }; 816 817 opp-9 { 818 opp-peak-kBps = <(1804 * 4 * 1000)>; 819 }; 820 }; 821 }; 822 823 spmi_bus: spmi@1c40000 { 824 compatible = "qcom,spmi-pmic-arb"; 825 reg = <0x0 0x01c40000 0x0 0x1100>, 826 <0x0 0x01e00000 0x0 0x2000000>, 827 <0x0 0x03e00000 0x0 0x100000>, 828 <0x0 0x03f00000 0x0 0xa0000>, 829 <0x0 0x01c0a000 0x0 0x26000>; 830 reg-names = "core", 831 "chnls", 832 "obsrvr", 833 "intr", 834 "cnfg"; 835 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "periph_irq"; 837 qcom,ee = <0>; 838 qcom,channel = <0>; 839 #address-cells = <2>; 840 #size-cells = <0>; 841 interrupt-controller; 842 #interrupt-cells = <4>; 843 }; 844 845 tsens0: thermal-sensor@4411000 { 846 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 847 reg = <0x0 0x04411000 0x0 0x1ff>, 848 <0x0 0x04410000 0x0 0x8>; 849 #qcom,sensors = <10>; 850 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 851 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "uplow", "critical"; 853 #thermal-sensor-cells = <1>; 854 }; 855 856 rng: rng@4453000 { 857 compatible = "qcom,prng-ee"; 858 reg = <0x0 0x04453000 0x0 0x1000>; 859 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 860 clock-names = "core"; 861 }; 862 863 bimc: interconnect@4480000 { 864 compatible = "qcom,qcm2290-bimc"; 865 reg = <0x0 0x04480000 0x0 0x80000>; 866 #interconnect-cells = <2>; 867 }; 868 869 rpm_msg_ram: sram@45f0000 { 870 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 871 reg = <0x0 0x045f0000 0x0 0x7000>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 ranges = <0 0x0 0x045f0000 0x7000>; 875 876 apss_mpm: sram@1b8 { 877 reg = <0x1b8 0x48>; 878 }; 879 }; 880 881 sram@4690000 { 882 compatible = "qcom,rpm-stats"; 883 reg = <0x0 0x04690000 0x0 0x10000>; 884 }; 885 886 sdhc_1: mmc@4744000 { 887 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 888 reg = <0x0 0x04744000 0x0 0x1000>, 889 <0x0 0x04745000 0x0 0x1000>, 890 <0x0 0x04748000 0x0 0x8000>; 891 reg-names = "hc", 892 "cqhci", 893 "ice"; 894 895 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "hc_irq", "pwr_irq"; 898 899 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 900 <&gcc GCC_SDCC1_APPS_CLK>, 901 <&rpmcc RPM_SMD_XO_CLK_SRC>, 902 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 903 clock-names = "iface", 904 "core", 905 "xo", 906 "ice"; 907 908 resets = <&gcc GCC_SDCC1_BCR>; 909 910 power-domains = <&rpmpd QCM2290_VDDCX>; 911 operating-points-v2 = <&sdhc1_opp_table>; 912 iommus = <&apps_smmu 0xc0 0x0>; 913 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 914 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 915 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 916 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 917 interconnect-names = "sdhc-ddr", 918 "cpu-sdhc"; 919 920 qcom,dll-config = <0x000f642c>; 921 qcom,ddr-config = <0x80040868>; 922 bus-width = <8>; 923 924 status = "disabled"; 925 926 sdhc1_opp_table: opp-table { 927 compatible = "operating-points-v2"; 928 929 opp-100000000 { 930 opp-hz = /bits/ 64 <100000000>; 931 required-opps = <&rpmpd_opp_low_svs>; 932 opp-peak-kBps = <250000 133320>; 933 opp-avg-kBps = <102400 65000>; 934 }; 935 936 opp-192000000 { 937 opp-hz = /bits/ 64 <192000000>; 938 required-opps = <&rpmpd_opp_low_svs>; 939 opp-peak-kBps = <800000 300000>; 940 opp-avg-kBps = <204800 200000>; 941 }; 942 943 opp-384000000 { 944 opp-hz = /bits/ 64 <384000000>; 945 required-opps = <&rpmpd_opp_svs_plus>; 946 opp-peak-kBps = <800000 300000>; 947 opp-avg-kBps = <204800 200000>; 948 }; 949 }; 950 }; 951 952 sdhc_2: mmc@4784000 { 953 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 954 reg = <0x0 0x04784000 0x0 0x1000>; 955 reg-names = "hc"; 956 957 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "hc_irq", "pwr_irq"; 960 961 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 962 <&gcc GCC_SDCC2_APPS_CLK>, 963 <&rpmcc RPM_SMD_XO_CLK_SRC>; 964 clock-names = "iface", 965 "core", 966 "xo"; 967 968 resets = <&gcc GCC_SDCC2_BCR>; 969 970 power-domains = <&rpmpd QCM2290_VDDCX>; 971 operating-points-v2 = <&sdhc2_opp_table>; 972 iommus = <&apps_smmu 0xa0 0x0>; 973 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 974 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 975 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 976 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 977 interconnect-names = "sdhc-ddr", 978 "cpu-sdhc"; 979 980 qcom,dll-config = <0x0007642c>; 981 qcom,ddr-config = <0x80040868>; 982 bus-width = <4>; 983 984 status = "disabled"; 985 986 sdhc2_opp_table: opp-table { 987 compatible = "operating-points-v2"; 988 989 opp-100000000 { 990 opp-hz = /bits/ 64 <100000000>; 991 required-opps = <&rpmpd_opp_low_svs>; 992 opp-peak-kBps = <250000 133320>; 993 opp-avg-kBps = <261438 150000>; 994 }; 995 996 opp-202000000 { 997 opp-hz = /bits/ 64 <202000000>; 998 required-opps = <&rpmpd_opp_svs_plus>; 999 opp-peak-kBps = <800000 300000>; 1000 opp-avg-kBps = <261438 300000>; 1001 }; 1002 }; 1003 }; 1004 1005 gpi_dma0: dma-controller@4a00000 { 1006 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1007 reg = <0x0 0x04a00000 0x0 0x60000>; 1008 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1018 dma-channels = <10>; 1019 dma-channel-mask = <0x1f>; 1020 iommus = <&apps_smmu 0xf6 0x0>; 1021 #dma-cells = <3>; 1022 status = "disabled"; 1023 }; 1024 1025 qupv3_id_0: geniqup@4ac0000 { 1026 compatible = "qcom,geni-se-qup"; 1027 reg = <0x0 0x04ac0000 0x0 0x2000>; 1028 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1029 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1030 clock-names = "m-ahb", "s-ahb"; 1031 iommus = <&apps_smmu 0xe3 0x0>; 1032 #address-cells = <2>; 1033 #size-cells = <2>; 1034 ranges; 1035 status = "disabled"; 1036 1037 i2c0: i2c@4a80000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0x0 0x04a80000 0x0 0x4000>; 1040 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1042 clock-names = "se"; 1043 pinctrl-0 = <&qup_i2c0_default>; 1044 pinctrl-names = "default"; 1045 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1046 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1047 dma-names = "tx", "rx"; 1048 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1049 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1050 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1051 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1052 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1053 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1054 interconnect-names = "qup-core", 1055 "qup-config", 1056 "qup-memory"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 spi0: spi@4a80000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0x0 0x04a80000 0x0 0x4000>; 1065 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1067 clock-names = "se"; 1068 pinctrl-0 = <&qup_spi0_default>; 1069 pinctrl-names = "default"; 1070 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1071 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1072 dma-names = "tx", "rx"; 1073 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1074 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1075 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1076 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1077 interconnect-names = "qup-core", 1078 "qup-config"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 uart0: serial@4a80000 { 1085 compatible = "qcom,geni-uart"; 1086 reg = <0x0 0x04a80000 0x0 0x4000>; 1087 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1089 clock-names = "se"; 1090 pinctrl-0 = <&qup_uart0_default>; 1091 pinctrl-names = "default"; 1092 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1093 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1094 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1095 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1096 interconnect-names = "qup-core", 1097 "qup-config"; 1098 status = "disabled"; 1099 }; 1100 1101 i2c1: i2c@4a84000 { 1102 compatible = "qcom,geni-i2c"; 1103 reg = <0x0 0x04a84000 0x0 0x4000>; 1104 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1106 clock-names = "se"; 1107 pinctrl-0 = <&qup_i2c1_default>; 1108 pinctrl-names = "default"; 1109 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1110 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1111 dma-names = "tx", "rx"; 1112 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1113 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1114 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1115 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1116 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1117 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1118 interconnect-names = "qup-core", 1119 "qup-config", 1120 "qup-memory"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 spi1: spi@4a84000 { 1127 compatible = "qcom,geni-spi"; 1128 reg = <0x0 0x04a84000 0x0 0x4000>; 1129 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1131 clock-names = "se"; 1132 pinctrl-0 = <&qup_spi1_default>; 1133 pinctrl-names = "default"; 1134 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1135 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1136 dma-names = "tx", "rx"; 1137 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1138 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1139 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1140 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1141 interconnect-names = "qup-core", 1142 "qup-config"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c2: i2c@4a88000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0x0 0x04a88000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1153 clock-names = "se"; 1154 pinctrl-0 = <&qup_i2c2_default>; 1155 pinctrl-names = "default"; 1156 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1160 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1161 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1162 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1163 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1164 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1165 interconnect-names = "qup-core", 1166 "qup-config", 1167 "qup-memory"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi2: spi@4a88000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0x0 0x04a88000 0x0 0x4000>; 1176 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1178 clock-names = "se"; 1179 pinctrl-0 = <&qup_spi2_default>; 1180 pinctrl-names = "default"; 1181 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1182 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1183 dma-names = "tx", "rx"; 1184 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1185 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1186 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1187 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1188 interconnect-names = "qup-core", 1189 "qup-config"; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c3: i2c@4a8c000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0x0 0x04a8c000 0x0 0x4000>; 1198 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1200 clock-names = "se"; 1201 pinctrl-0 = <&qup_i2c3_default>; 1202 pinctrl-names = "default"; 1203 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1204 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1205 dma-names = "tx", "rx"; 1206 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1207 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1208 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1209 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1210 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1211 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1212 interconnect-names = "qup-core", 1213 "qup-config", 1214 "qup-memory"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 spi3: spi@4a8c000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0x0 0x04a8c000 0x0 0x4000>; 1223 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1225 clock-names = "se"; 1226 pinctrl-0 = <&qup_spi3_default>; 1227 pinctrl-names = "default"; 1228 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1229 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1230 dma-names = "tx", "rx"; 1231 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1232 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1233 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1234 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1235 interconnect-names = "qup-core", 1236 "qup-config"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 i2c4: i2c@4a90000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0x0 0x04a90000 0x0 0x4000>; 1245 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1247 clock-names = "se"; 1248 pinctrl-0 = <&qup_i2c4_default>; 1249 pinctrl-names = "default"; 1250 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1254 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1255 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1256 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1257 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1258 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1259 interconnect-names = "qup-core", 1260 "qup-config", 1261 "qup-memory"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 spi4: spi@4a90000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0x0 0x04a90000 0x0 0x4000>; 1270 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1271 clock-names = "se"; 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1273 pinctrl-names = "default"; 1274 pinctrl-0 = <&qup_spi4_default>; 1275 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1276 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1279 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1280 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1281 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1282 interconnect-names = "qup-core", 1283 "qup-config"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 uart4: serial@4a90000 { 1290 compatible = "qcom,geni-uart"; 1291 reg = <0x0 0x04a90000 0x0 0x4000>; 1292 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1294 clock-names = "se"; 1295 pinctrl-0 = <&qup_uart4_default>; 1296 pinctrl-names = "default"; 1297 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1298 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1299 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1300 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1301 interconnect-names = "qup-core", 1302 "qup-config"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c5: i2c@4a94000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0x0 0x04a94000 0x0 0x4000>; 1309 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1311 clock-names = "se"; 1312 pinctrl-0 = <&qup_i2c5_default>; 1313 pinctrl-names = "default"; 1314 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1315 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1316 dma-names = "tx", "rx"; 1317 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1318 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1319 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1320 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1321 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1322 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1323 interconnect-names = "qup-core", 1324 "qup-config", 1325 "qup-memory"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 spi5: spi@4a94000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0x0 0x04a94000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1336 clock-names = "se"; 1337 pinctrl-0 = <&qup_spi5_default>; 1338 pinctrl-names = "default"; 1339 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1340 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1341 dma-names = "tx", "rx"; 1342 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1343 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1344 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1345 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1346 interconnect-names = "qup-core", 1347 "qup-config"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 }; 1353 1354 usb: usb@4ef8800 { 1355 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1356 reg = <0x0 0x04ef8800 0x0 0x400>; 1357 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1358 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1359 interrupt-names = "hs_phy_irq", 1360 "ss_phy_irq"; 1361 1362 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1363 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1364 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1365 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1366 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1367 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1368 clock-names = "cfg_noc", 1369 "core", 1370 "iface", 1371 "sleep", 1372 "mock_utmi", 1373 "xo"; 1374 1375 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1376 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1377 assigned-clock-rates = <19200000>, <133333333>; 1378 1379 resets = <&gcc GCC_USB30_PRIM_BCR>; 1380 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1381 /* TODO: USB<->IPA path */ 1382 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1383 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1384 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1385 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1386 interconnect-names = "usb-ddr", 1387 "apps-usb"; 1388 wakeup-source; 1389 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 1394 status = "disabled"; 1395 1396 usb_dwc3: usb@4e00000 { 1397 compatible = "snps,dwc3"; 1398 reg = <0x0 0x04e00000 0x0 0xcd00>; 1399 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1400 phys = <&usb_hsphy>, <&usb_qmpphy>; 1401 phy-names = "usb2-phy", "usb3-phy"; 1402 iommus = <&apps_smmu 0x120 0x0>; 1403 snps,dis_u2_susphy_quirk; 1404 snps,dis_enblslpm_quirk; 1405 snps,has-lpm-erratum; 1406 snps,hird-threshold = /bits/ 8 <0x10>; 1407 snps,usb3_lpm_capable; 1408 maximum-speed = "super-speed"; 1409 dr_mode = "otg"; 1410 usb-role-switch; 1411 1412 ports { 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 1416 port@0 { 1417 reg = <0>; 1418 1419 usb_dwc3_hs: endpoint { 1420 }; 1421 }; 1422 1423 port@1 { 1424 reg = <1>; 1425 1426 usb_dwc3_ss: endpoint { 1427 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1428 }; 1429 }; 1430 }; 1431 }; 1432 }; 1433 1434 gpu: gpu@5900000 { 1435 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1436 reg = <0x0 0x05900000 0x0 0x40000>; 1437 reg-names = "kgsl_3d0_reg_memory"; 1438 1439 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1440 1441 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1442 <&gpucc GPU_CC_AHB_CLK>, 1443 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1444 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1445 <&gpucc GPU_CC_CX_GMU_CLK>, 1446 <&gpucc GPU_CC_CXO_CLK>; 1447 clock-names = "core", 1448 "iface", 1449 "mem_iface", 1450 "alt_mem_iface", 1451 "gmu", 1452 "xo"; 1453 1454 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1455 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1456 interconnect-names = "gfx-mem"; 1457 1458 iommus = <&adreno_smmu 0 1>, 1459 <&adreno_smmu 2 0>; 1460 operating-points-v2 = <&gpu_opp_table>; 1461 power-domains = <&rpmpd QCM2290_VDDCX>; 1462 qcom,gmu = <&gmu_wrapper>; 1463 1464 nvmem-cells = <&gpu_speed_bin>; 1465 nvmem-cell-names = "speed_bin"; 1466 #cooling-cells = <2>; 1467 1468 status = "disabled"; 1469 1470 zap-shader { 1471 memory-region = <&pil_gpu_mem>; 1472 }; 1473 1474 gpu_opp_table: opp-table { 1475 compatible = "operating-points-v2"; 1476 1477 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1478 opp-1123200000 { 1479 opp-hz = /bits/ 64 <1123200000>; 1480 required-opps = <&rpmpd_opp_turbo_plus>; 1481 opp-peak-kBps = <6881000>; 1482 opp-supported-hw = <0x3>; 1483 turbo-mode; 1484 }; 1485 1486 opp-1017600000 { 1487 opp-hz = /bits/ 64 <1017600000>; 1488 required-opps = <&rpmpd_opp_turbo>; 1489 opp-peak-kBps = <6881000>; 1490 opp-supported-hw = <0x3>; 1491 turbo-mode; 1492 }; 1493 1494 opp-921600000 { 1495 opp-hz = /bits/ 64 <921600000>; 1496 required-opps = <&rpmpd_opp_nom_plus>; 1497 opp-peak-kBps = <6881000>; 1498 opp-supported-hw = <0x3>; 1499 }; 1500 1501 opp-844800000 { 1502 opp-hz = /bits/ 64 <844800000>; 1503 required-opps = <&rpmpd_opp_nom>; 1504 opp-peak-kBps = <6881000>; 1505 opp-supported-hw = <0x7>; 1506 }; 1507 1508 opp-672000000 { 1509 opp-hz = /bits/ 64 <672000000>; 1510 required-opps = <&rpmpd_opp_svs_plus>; 1511 opp-peak-kBps = <3879000>; 1512 opp-supported-hw = <0xf>; 1513 }; 1514 1515 opp-537600000 { 1516 opp-hz = /bits/ 64 <537600000>; 1517 required-opps = <&rpmpd_opp_svs>; 1518 opp-peak-kBps = <2929000>; 1519 opp-supported-hw = <0xf>; 1520 }; 1521 1522 opp-355200000 { 1523 opp-hz = /bits/ 64 <355200000>; 1524 required-opps = <&rpmpd_opp_low_svs>; 1525 opp-peak-kBps = <1720000>; 1526 opp-supported-hw = <0xf>; 1527 }; 1528 }; 1529 }; 1530 1531 gmu_wrapper: gmu@596a000 { 1532 compatible = "qcom,adreno-gmu-wrapper"; 1533 reg = <0x0 0x0596a000 0x0 0x30000>; 1534 reg-names = "gmu"; 1535 power-domains = <&gpucc GPU_CX_GDSC>, 1536 <&gpucc GPU_GX_GDSC>; 1537 power-domain-names = "cx", 1538 "gx"; 1539 }; 1540 1541 gpucc: clock-controller@5990000 { 1542 compatible = "qcom,qcm2290-gpucc"; 1543 reg = <0x0 0x05990000 0x0 0x9000>; 1544 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1545 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1546 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1547 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1548 power-domains = <&rpmpd QCM2290_VDDCX>; 1549 required-opps = <&rpmpd_opp_low_svs>; 1550 #clock-cells = <1>; 1551 #reset-cells = <1>; 1552 #power-domain-cells = <1>; 1553 }; 1554 1555 adreno_smmu: iommu@59a0000 { 1556 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1557 "qcom,smmu-500", "arm,mmu-500"; 1558 reg = <0x0 0x059a0000 0x0 0x10000>; 1559 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1568 1569 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1570 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1571 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1572 clock-names = "mem", 1573 "hlos", 1574 "iface"; 1575 1576 power-domains = <&gpucc GPU_CX_GDSC>; 1577 1578 #global-interrupts = <1>; 1579 #iommu-cells = <2>; 1580 }; 1581 1582 mdss: display-subsystem@5e00000 { 1583 compatible = "qcom,qcm2290-mdss"; 1584 reg = <0x0 0x05e00000 0x0 0x1000>; 1585 reg-names = "mdss"; 1586 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1587 interrupt-controller; 1588 #interrupt-cells = <1>; 1589 1590 clocks = <&gcc GCC_DISP_AHB_CLK>, 1591 <&gcc GCC_DISP_HF_AXI_CLK>, 1592 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1593 clock-names = "iface", 1594 "bus", 1595 "core"; 1596 1597 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1598 1599 power-domains = <&dispcc MDSS_GDSC>; 1600 1601 iommus = <&apps_smmu 0x420 0x2>, 1602 <&apps_smmu 0x421 0x0>; 1603 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1604 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1605 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1606 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1607 interconnect-names = "mdp0-mem", 1608 "cpu-cfg"; 1609 1610 #address-cells = <2>; 1611 #size-cells = <2>; 1612 ranges; 1613 1614 status = "disabled"; 1615 1616 mdp: display-controller@5e01000 { 1617 compatible = "qcom,qcm2290-dpu"; 1618 reg = <0x0 0x05e01000 0x0 0x8f000>, 1619 <0x0 0x05eb0000 0x0 0x2008>; 1620 reg-names = "mdp", 1621 "vbif"; 1622 1623 interrupt-parent = <&mdss>; 1624 interrupts = <0>; 1625 1626 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1627 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1628 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1629 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1630 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1631 clock-names = "bus", 1632 "iface", 1633 "core", 1634 "lut", 1635 "vsync"; 1636 1637 operating-points-v2 = <&mdp_opp_table>; 1638 power-domains = <&rpmpd QCM2290_VDDCX>; 1639 1640 ports { 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 1644 port@0 { 1645 reg = <0>; 1646 dpu_intf1_out: endpoint { 1647 remote-endpoint = <&mdss_dsi0_in>; 1648 }; 1649 }; 1650 }; 1651 1652 mdp_opp_table: opp-table { 1653 compatible = "operating-points-v2"; 1654 1655 opp-19200000 { 1656 opp-hz = /bits/ 64 <19200000>; 1657 required-opps = <&rpmpd_opp_min_svs>; 1658 }; 1659 1660 opp-192000000 { 1661 opp-hz = /bits/ 64 <192000000>; 1662 required-opps = <&rpmpd_opp_low_svs>; 1663 }; 1664 1665 opp-256000000 { 1666 opp-hz = /bits/ 64 <256000000>; 1667 required-opps = <&rpmpd_opp_svs>; 1668 }; 1669 1670 opp-307200000 { 1671 opp-hz = /bits/ 64 <307200000>; 1672 required-opps = <&rpmpd_opp_svs_plus>; 1673 }; 1674 1675 opp-384000000 { 1676 opp-hz = /bits/ 64 <384000000>; 1677 required-opps = <&rpmpd_opp_nom>; 1678 }; 1679 }; 1680 }; 1681 1682 mdss_dsi0: dsi@5e94000 { 1683 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1684 reg = <0x0 0x05e94000 0x0 0x400>; 1685 reg-names = "dsi_ctrl"; 1686 1687 interrupt-parent = <&mdss>; 1688 interrupts = <4>; 1689 1690 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1691 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1692 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1693 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1694 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1695 <&gcc GCC_DISP_HF_AXI_CLK>; 1696 clock-names = "byte", 1697 "byte_intf", 1698 "pixel", 1699 "core", 1700 "iface", 1701 "bus"; 1702 1703 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1704 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1705 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1706 <&mdss_dsi0_phy 1>; 1707 1708 operating-points-v2 = <&dsi_opp_table>; 1709 power-domains = <&rpmpd QCM2290_VDDCX>; 1710 phys = <&mdss_dsi0_phy>; 1711 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 status = "disabled"; 1716 1717 dsi_opp_table: opp-table { 1718 compatible = "operating-points-v2"; 1719 1720 opp-19200000 { 1721 opp-hz = /bits/ 64 <19200000>; 1722 required-opps = <&rpmpd_opp_min_svs>; 1723 }; 1724 1725 opp-164000000 { 1726 opp-hz = /bits/ 64 <164000000>; 1727 required-opps = <&rpmpd_opp_low_svs>; 1728 }; 1729 1730 opp-187500000 { 1731 opp-hz = /bits/ 64 <187500000>; 1732 required-opps = <&rpmpd_opp_svs>; 1733 }; 1734 }; 1735 1736 ports { 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 1740 port@0 { 1741 reg = <0>; 1742 1743 mdss_dsi0_in: endpoint { 1744 remote-endpoint = <&dpu_intf1_out>; 1745 }; 1746 }; 1747 1748 port@1 { 1749 reg = <1>; 1750 1751 mdss_dsi0_out: endpoint { 1752 }; 1753 }; 1754 }; 1755 }; 1756 1757 mdss_dsi0_phy: phy@5e94400 { 1758 compatible = "qcom,dsi-phy-14nm-2290"; 1759 reg = <0x0 0x05e94400 0x0 0x100>, 1760 <0x0 0x05e94500 0x0 0x300>, 1761 <0x0 0x05e94800 0x0 0x188>; 1762 reg-names = "dsi_phy", 1763 "dsi_phy_lane", 1764 "dsi_pll"; 1765 1766 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1767 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1768 clock-names = "iface", 1769 "ref"; 1770 1771 power-domains = <&rpmpd QCM2290_VDDMX>; 1772 required-opps = <&rpmpd_opp_nom>; 1773 1774 #clock-cells = <1>; 1775 #phy-cells = <0>; 1776 1777 status = "disabled"; 1778 }; 1779 }; 1780 1781 dispcc: clock-controller@5f00000 { 1782 compatible = "qcom,qcm2290-dispcc"; 1783 reg = <0x0 0x05f00000 0x0 0x20000>; 1784 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1785 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 1786 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1787 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1788 <&mdss_dsi0_phy 0>, 1789 <&mdss_dsi0_phy 1>; 1790 clock-names = "bi_tcxo", 1791 "bi_tcxo_ao", 1792 "gcc_disp_gpll0_clk_src", 1793 "gcc_disp_gpll0_div_clk_src", 1794 "dsi0_phy_pll_out_byteclk", 1795 "dsi0_phy_pll_out_dsiclk"; 1796 #power-domain-cells = <1>; 1797 #clock-cells = <1>; 1798 #reset-cells = <1>; 1799 }; 1800 1801 remoteproc_mpss: remoteproc@6080000 { 1802 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1803 reg = <0x0 0x06080000 0x0 0x100>; 1804 1805 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1806 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1807 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1808 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1809 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1810 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1811 interrupt-names = "wdog", 1812 "fatal", 1813 "ready", 1814 "handover", 1815 "stop-ack", 1816 "shutdown-ack"; 1817 1818 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1819 clock-names = "xo"; 1820 1821 power-domains = <&rpmpd QCM2290_VDDCX>; 1822 1823 memory-region = <&pil_modem_mem>; 1824 1825 qcom,smem-states = <&modem_smp2p_out 0>; 1826 qcom,smem-state-names = "stop"; 1827 1828 status = "disabled"; 1829 1830 glink-edge { 1831 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1832 label = "mpss"; 1833 qcom,remote-pid = <1>; 1834 mboxes = <&apcs_glb 12>; 1835 }; 1836 }; 1837 1838 remoteproc_adsp: remoteproc@ab00000 { 1839 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1840 reg = <0x0 0x0ab00000 0x0 0x100>; 1841 1842 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1843 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1844 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1845 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1846 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1847 interrupt-names = "wdog", 1848 "fatal", 1849 "ready", 1850 "handover", 1851 "stop-ack"; 1852 1853 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1854 clock-names = "xo"; 1855 1856 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1857 <&rpmpd QCM2290_VDD_LPI_MX>; 1858 1859 memory-region = <&pil_adsp_mem>; 1860 1861 qcom,smem-states = <&adsp_smp2p_out 0>; 1862 qcom,smem-state-names = "stop"; 1863 1864 status = "disabled"; 1865 1866 glink-edge { 1867 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1868 label = "lpass"; 1869 qcom,remote-pid = <2>; 1870 mboxes = <&apcs_glb 8>; 1871 }; 1872 }; 1873 1874 apps_smmu: iommu@c600000 { 1875 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1876 reg = <0x0 0x0c600000 0x0 0x80000>; 1877 #iommu-cells = <2>; 1878 #global-interrupts = <1>; 1879 1880 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1945 }; 1946 1947 wifi: wifi@c800000 { 1948 compatible = "qcom,wcn3990-wifi"; 1949 reg = <0x0 0x0c800000 0x0 0x800000>; 1950 reg-names = "membase"; 1951 memory-region = <&wlan_msa_mem>; 1952 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1963 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1964 iommus = <&apps_smmu 0x1a0 0x1>; 1965 qcom,msa-fixed-perm; 1966 status = "disabled"; 1967 }; 1968 1969 watchdog@f017000 { 1970 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1971 reg = <0x0 0x0f017000 0x0 0x1000>; 1972 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1974 clocks = <&sleep_clk>; 1975 }; 1976 1977 apcs_glb: mailbox@f111000 { 1978 compatible = "qcom,qcm2290-apcs-hmss-global"; 1979 reg = <0x0 0x0f111000 0x0 0x1000>; 1980 #mbox-cells = <1>; 1981 }; 1982 1983 timer@f120000 { 1984 compatible = "arm,armv7-timer-mem"; 1985 reg = <0x0 0x0f120000 0x0 0x1000>; 1986 #address-cells = <1>; 1987 #size-cells = <1>; 1988 ranges = <0 0x0 0x0f121000 0x8000>; 1989 1990 frame@0 { 1991 reg = <0x0 0x1000>, 1992 <0x1000 0x1000>; 1993 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1994 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1995 frame-number = <0>; 1996 }; 1997 1998 frame@2000 { 1999 reg = <0x2000 0x1000>; 2000 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2001 frame-number = <1>; 2002 status = "disabled"; 2003 }; 2004 2005 frame@3000 { 2006 reg = <0x3000 0x1000>; 2007 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2008 frame-number = <2>; 2009 status = "disabled"; 2010 }; 2011 2012 frame@4000 { 2013 reg = <0x4000 0x1000>; 2014 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2015 frame-number = <3>; 2016 status = "disabled"; 2017 }; 2018 2019 frame@5000 { 2020 reg = <0x5000 0x1000>; 2021 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2022 frame-number = <4>; 2023 status = "disabled"; 2024 }; 2025 2026 frame@6000 { 2027 reg = <0x6000 0x1000>; 2028 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2029 frame-number = <5>; 2030 status = "disabled"; 2031 }; 2032 2033 frame@7000 { 2034 reg = <0x7000 0x1000>; 2035 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2036 frame-number = <6>; 2037 status = "disabled"; 2038 }; 2039 }; 2040 2041 intc: interrupt-controller@f200000 { 2042 compatible = "arm,gic-v3"; 2043 reg = <0x0 0x0f200000 0x0 0x10000>, 2044 <0x0 0x0f300000 0x0 0x100000>; 2045 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2046 #interrupt-cells = <3>; 2047 interrupt-controller; 2048 interrupt-parent = <&intc>; 2049 #redistributor-regions = <1>; 2050 redistributor-stride = <0x0 0x20000>; 2051 }; 2052 2053 cpufreq_hw: cpufreq@f521000 { 2054 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2055 reg = <0x0 0x0f521000 0x0 0x1000>; 2056 reg-names = "freq-domain0"; 2057 interrupts-extended = <&lmh_cluster 0>; 2058 interrupt-names = "dcvsh-irq-0"; 2059 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2060 clock-names = "xo", "alternate"; 2061 2062 #freq-domain-cells = <1>; 2063 #clock-cells = <1>; 2064 }; 2065 2066 lmh_cluster: lmh@f550800 { 2067 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2068 reg = <0x0 0x0f550800 0x0 0x400>; 2069 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2070 cpus = <&CPU0>; 2071 qcom,lmh-temp-arm-millicelsius = <65000>; 2072 qcom,lmh-temp-low-millicelsius = <94500>; 2073 qcom,lmh-temp-high-millicelsius = <95000>; 2074 interrupt-controller; 2075 #interrupt-cells = <1>; 2076 }; 2077 }; 2078 2079 thermal-zones { 2080 mapss-thermal { 2081 thermal-sensors = <&tsens0 0>; 2082 2083 trips { 2084 mapss_alert0: trip-point0 { 2085 temperature = <90000>; 2086 hysteresis = <2000>; 2087 type = "passive"; 2088 }; 2089 2090 mapss_alert1: trip-point1 { 2091 temperature = <95000>; 2092 hysteresis = <2000>; 2093 type = "passive"; 2094 }; 2095 2096 mapss_crit: mapss-crit { 2097 temperature = <110000>; 2098 hysteresis = <1000>; 2099 type = "critical"; 2100 }; 2101 }; 2102 }; 2103 2104 video-thermal { 2105 thermal-sensors = <&tsens0 1>; 2106 2107 trips { 2108 video_alert0: trip-point0 { 2109 temperature = <90000>; 2110 hysteresis = <2000>; 2111 type = "passive"; 2112 }; 2113 2114 video_alert1: trip-point1 { 2115 temperature = <95000>; 2116 hysteresis = <2000>; 2117 type = "passive"; 2118 }; 2119 2120 video_crit: video-crit { 2121 temperature = <110000>; 2122 hysteresis = <1000>; 2123 type = "critical"; 2124 }; 2125 }; 2126 }; 2127 2128 wlan-thermal { 2129 thermal-sensors = <&tsens0 2>; 2130 2131 trips { 2132 wlan_alert0: trip-point0 { 2133 temperature = <90000>; 2134 hysteresis = <2000>; 2135 type = "passive"; 2136 }; 2137 2138 wlan_alert1: trip-point1 { 2139 temperature = <95000>; 2140 hysteresis = <2000>; 2141 type = "passive"; 2142 }; 2143 2144 wlan_crit: wlan-crit { 2145 temperature = <110000>; 2146 hysteresis = <1000>; 2147 type = "critical"; 2148 }; 2149 }; 2150 }; 2151 2152 cpuss0-thermal { 2153 thermal-sensors = <&tsens0 3>; 2154 2155 trips { 2156 cpuss0_alert0: trip-point0 { 2157 temperature = <90000>; 2158 hysteresis = <2000>; 2159 type = "passive"; 2160 }; 2161 2162 cpuss0_alert1: trip-point1 { 2163 temperature = <95000>; 2164 hysteresis = <2000>; 2165 type = "passive"; 2166 }; 2167 2168 cpuss0_crit: cpuss0-crit { 2169 temperature = <110000>; 2170 hysteresis = <1000>; 2171 type = "critical"; 2172 }; 2173 }; 2174 }; 2175 2176 cpuss1-thermal { 2177 thermal-sensors = <&tsens0 4>; 2178 2179 trips { 2180 cpuss1_alert0: trip-point0 { 2181 temperature = <90000>; 2182 hysteresis = <2000>; 2183 type = "passive"; 2184 }; 2185 2186 cpuss1_alert1: trip-point1 { 2187 temperature = <95000>; 2188 hysteresis = <2000>; 2189 type = "passive"; 2190 }; 2191 2192 cpuss1_crit: cpuss1-crit { 2193 temperature = <110000>; 2194 hysteresis = <1000>; 2195 type = "critical"; 2196 }; 2197 }; 2198 }; 2199 2200 mdm0-thermal { 2201 thermal-sensors = <&tsens0 5>; 2202 2203 trips { 2204 mdm0_alert0: trip-point0 { 2205 temperature = <90000>; 2206 hysteresis = <2000>; 2207 type = "passive"; 2208 }; 2209 2210 mdm0_alert1: trip-point1 { 2211 temperature = <95000>; 2212 hysteresis = <2000>; 2213 type = "passive"; 2214 }; 2215 2216 mdm0_crit: mdm0-crit { 2217 temperature = <110000>; 2218 hysteresis = <1000>; 2219 type = "critical"; 2220 }; 2221 }; 2222 }; 2223 2224 mdm1-thermal { 2225 thermal-sensors = <&tsens0 6>; 2226 2227 trips { 2228 mdm1_alert0: trip-point0 { 2229 temperature = <90000>; 2230 hysteresis = <2000>; 2231 type = "passive"; 2232 }; 2233 2234 mdm1_alert1: trip-point1 { 2235 temperature = <95000>; 2236 hysteresis = <2000>; 2237 type = "passive"; 2238 }; 2239 2240 mdm1_crit: mdm1-crit { 2241 temperature = <110000>; 2242 hysteresis = <1000>; 2243 type = "critical"; 2244 }; 2245 }; 2246 }; 2247 2248 gpu-thermal { 2249 thermal-sensors = <&tsens0 7>; 2250 2251 trips { 2252 gpu_alert0: trip-point0 { 2253 temperature = <90000>; 2254 hysteresis = <2000>; 2255 type = "passive"; 2256 }; 2257 2258 gpu_alert1: trip-point1 { 2259 temperature = <95000>; 2260 hysteresis = <2000>; 2261 type = "passive"; 2262 }; 2263 2264 gpu_crit: gpu-crit { 2265 temperature = <110000>; 2266 hysteresis = <1000>; 2267 type = "critical"; 2268 }; 2269 }; 2270 }; 2271 2272 hm-center-thermal { 2273 thermal-sensors = <&tsens0 8>; 2274 2275 trips { 2276 hm_center_alert0: trip-point0 { 2277 temperature = <90000>; 2278 hysteresis = <2000>; 2279 type = "passive"; 2280 }; 2281 2282 hm_center_alert1: trip-point1 { 2283 temperature = <95000>; 2284 hysteresis = <2000>; 2285 type = "passive"; 2286 }; 2287 2288 hm_center_crit: hm-center-crit { 2289 temperature = <110000>; 2290 hysteresis = <1000>; 2291 type = "critical"; 2292 }; 2293 }; 2294 }; 2295 2296 camera-thermal { 2297 thermal-sensors = <&tsens0 9>; 2298 2299 trips { 2300 camera_alert0: trip-point0 { 2301 temperature = <90000>; 2302 hysteresis = <2000>; 2303 type = "passive"; 2304 }; 2305 2306 camera_alert1: trip-point1 { 2307 temperature = <95000>; 2308 hysteresis = <2000>; 2309 type = "passive"; 2310 }; 2311 2312 camera_crit: camera-crit { 2313 temperature = <110000>; 2314 hysteresis = <1000>; 2315 type = "critical"; 2316 }; 2317 }; 2318 }; 2319 }; 2320 2321 timer { 2322 compatible = "arm,armv8-timer"; 2323 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2324 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2325 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2326 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2327 }; 2328}; 2329