1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ5424 device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,apss-ipq.h> 11#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 12#include <dt-bindings/clock/qcom,ipq5424-gcc.h> 13#include <dt-bindings/reset/qcom,ipq5424-gcc.h> 14#include <dt-bindings/interconnect/qcom,ipq5424.h> 15#include <dt-bindings/gpio/gpio.h> 16 17/ { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 interrupt-parent = <&intc>; 21 22 clocks { 23 ref_48mhz_clk: ref-48mhz-clk { 24 compatible = "fixed-factor-clock"; 25 clocks = <&xo_clk>; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 xo_board: xo-board-clk { 35 compatible = "fixed-factor-clock"; 36 clocks = <&ref_48mhz_clk>; 37 #clock-cells = <0>; 38 }; 39 40 xo_clk: xo-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 }; 45 46 cpus: cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 60 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 next-level-cache = <&l3_0>; 66 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 enable-method = "psci"; 79 reg = <0x100>; 80 next-level-cache = <&l2_100>; 81 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 82 clock-names = "cpu"; 83 operating-points-v2 = <&cpu_opp_table>; 84 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 85 86 l2_100: l2-cache { 87 compatible = "cache"; 88 cache-level = <2>; 89 cache-unified; 90 next-level-cache = <&l3_0>; 91 }; 92 }; 93 94 cpu2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 enable-method = "psci"; 98 reg = <0x200>; 99 next-level-cache = <&l2_200>; 100 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 101 clock-names = "cpu"; 102 operating-points-v2 = <&cpu_opp_table>; 103 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 104 105 l2_200: l2-cache { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 next-level-cache = <&l3_0>; 110 }; 111 }; 112 113 cpu3: cpu@300 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a55"; 116 enable-method = "psci"; 117 reg = <0x300>; 118 next-level-cache = <&l2_300>; 119 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 120 clock-names = "cpu"; 121 operating-points-v2 = <&cpu_opp_table>; 122 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 123 124 l2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&l3_0>; 129 }; 130 }; 131 }; 132 133 firmware { 134 scm { 135 compatible = "qcom,scm-ipq5424", "qcom,scm"; 136 qcom,dload-mode = <&tcsr 0x25100>; 137 }; 138 }; 139 140 cpu_opp_table: opp-table-cpu { 141 compatible = "operating-points-v2-kryo-cpu"; 142 opp-shared; 143 nvmem-cells = <&cpu_speed_bin>; 144 145 opp-816000000 { 146 opp-hz = /bits/ 64 <816000000>; 147 opp-microvolt = <850000>; 148 opp-supported-hw = <0x3>; 149 clock-latency-ns = <200000>; 150 opp-peak-kBps = <816000>; 151 }; 152 153 opp-1416000000 { 154 opp-hz = /bits/ 64 <1416000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0x3>; 157 clock-latency-ns = <200000>; 158 opp-peak-kBps = <984000>; 159 }; 160 161 opp-1800000000 { 162 opp-hz = /bits/ 64 <1800000000>; 163 opp-microvolt = <1000000>; 164 opp-supported-hw = <0x1>; 165 clock-latency-ns = <200000>; 166 opp-peak-kBps = <1272000>; 167 }; 168 }; 169 170 memory@80000000 { 171 device_type = "memory"; 172 /* We expect the bootloader to fill in the size */ 173 reg = <0x0 0x80000000 0x0 0x0>; 174 }; 175 176 pmu-a55 { 177 compatible = "arm,cortex-a55-pmu"; 178 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 pmu-dsu { 182 compatible = "arm,dsu-pmu"; 183 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 184 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 185 }; 186 187 psci { 188 compatible = "arm,psci-1.0"; 189 method = "smc"; 190 }; 191 192 reserved-memory { 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 197 bootloader@8a200000 { 198 reg = <0x0 0x8a200000 0x0 0x400000>; 199 no-map; 200 }; 201 202 tz@8a600000 { 203 reg = <0x0 0x8a600000 0x0 0x200000>; 204 no-map; 205 }; 206 207 smem@8a800000 { 208 compatible = "qcom,smem"; 209 reg = <0x0 0x8a800000 0x0 0x32000>; 210 no-map; 211 212 hwlocks = <&tcsr_mutex 3>; 213 }; 214 215 tfa@8a832000 { 216 reg = <0x0 0x8a832000 0x0 0x7d000>; 217 no-map; 218 status = "disabled"; 219 }; 220 }; 221 222 soc@0 { 223 compatible = "simple-bus"; 224 #address-cells = <2>; 225 #size-cells = <2>; 226 ranges = <0 0 0 0 0x10 0>; 227 228 pcie0_phy: phy@84000 { 229 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 230 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 231 reg = <0x0 0x00084000 0x0 0x1000>; 232 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 233 <&gcc GCC_PCIE0_AHB_CLK>, 234 <&gcc GCC_PCIE0_PIPE_CLK>; 235 clock-names = "aux", 236 "cfg_ahb", 237 "pipe"; 238 239 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; 240 assigned-clock-rates = <20000000>; 241 242 resets = <&gcc GCC_PCIE0_PHY_BCR>, 243 <&gcc GCC_PCIE0PHY_PHY_BCR>; 244 reset-names = "phy", 245 "common"; 246 247 #clock-cells = <0>; 248 clock-output-names = "gcc_pcie0_pipe_clk_src"; 249 250 #phy-cells = <0>; 251 status = "disabled"; 252 }; 253 254 pcie1_phy: phy@8c000 { 255 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 256 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 257 reg = <0x0 0x0008c000 0x0 0x1000>; 258 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 259 <&gcc GCC_PCIE1_AHB_CLK>, 260 <&gcc GCC_PCIE1_PIPE_CLK>; 261 clock-names = "aux", 262 "cfg_ahb", 263 "pipe"; 264 265 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; 266 assigned-clock-rates = <20000000>; 267 268 resets = <&gcc GCC_PCIE1_PHY_BCR>, 269 <&gcc GCC_PCIE1PHY_PHY_BCR>; 270 reset-names = "phy", 271 "common"; 272 273 #clock-cells = <0>; 274 clock-output-names = "gcc_pcie1_pipe_clk_src"; 275 276 #phy-cells = <0>; 277 status = "disabled"; 278 }; 279 280 cmn_pll: clock-controller@9b000 { 281 compatible = "qcom,ipq5424-cmn-pll"; 282 reg = <0 0x0009b000 0 0x800>; 283 clocks = <&ref_48mhz_clk>, 284 <&gcc GCC_CMN_12GPLL_AHB_CLK>, 285 <&gcc GCC_CMN_12GPLL_SYS_CLK>; 286 clock-names = "ref", "ahb", "sys"; 287 #clock-cells = <1>; 288 assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>; 289 assigned-clock-rates-u64 = /bits/ 64 <12000000000>; 290 }; 291 292 efuse@a4000 { 293 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 294 reg = <0 0x000a4000 0 0x741>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 298 tsens_sens9_off: s9@3dc { 299 reg = <0x3dc 0x1>; 300 bits = <4 4>; 301 }; 302 303 tsens_sens10_off: s10@3dd { 304 reg = <0x3dd 0x1>; 305 bits = <0 4>; 306 }; 307 308 tsens_sens11_off: s11@3dd { 309 reg = <0x3dd 0x1>; 310 bits = <4 4>; 311 }; 312 313 tsens_sens12_off: s12@3de { 314 reg = <0x3de 0x1>; 315 bits = <0 4>; 316 }; 317 318 tsens_sens13_off: s13@3de { 319 reg = <0x3de 0x1>; 320 bits = <4 4>; 321 }; 322 323 tsens_sens14_off: s14@3e5 { 324 reg = <0x3e5 0x2>; 325 bits = <7 4>; 326 }; 327 328 tsens_sens15_off: s15@3e6 { 329 reg = <0x3e6 0x1>; 330 bits = <3 4>; 331 }; 332 333 tsens_mode: mode@419 { 334 reg = <0x419 0x1>; 335 bits = <0 3>; 336 }; 337 338 tsens_base0: base0@419 { 339 reg = <0x419 0x2>; 340 bits = <3 10>; 341 }; 342 343 tsens_base1: base1@41a { 344 reg = <0x41a 0x2>; 345 bits = <5 10>; 346 }; 347 }; 348 349 pcie2_phy: phy@f4000 { 350 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 351 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 352 reg = <0x0 0x000f4000 0x0 0x2000>; 353 clocks = <&gcc GCC_PCIE2_AUX_CLK>, 354 <&gcc GCC_PCIE2_AHB_CLK>, 355 <&gcc GCC_PCIE2_PIPE_CLK>; 356 clock-names = "aux", 357 "cfg_ahb", 358 "pipe"; 359 360 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; 361 assigned-clock-rates = <20000000>; 362 363 resets = <&gcc GCC_PCIE2_PHY_BCR>, 364 <&gcc GCC_PCIE2PHY_PHY_BCR>; 365 reset-names = "phy", 366 "common"; 367 368 #clock-cells = <0>; 369 clock-output-names = "gcc_pcie2_pipe_clk_src"; 370 371 #phy-cells = <0>; 372 status = "disabled"; 373 }; 374 375 pcie3_phy: phy@fc000 { 376 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 377 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 378 reg = <0x0 0x000fc000 0x0 0x2000>; 379 clocks = <&gcc GCC_PCIE3_AUX_CLK>, 380 <&gcc GCC_PCIE3_AHB_CLK>, 381 <&gcc GCC_PCIE3_PIPE_CLK>; 382 clock-names = "aux", 383 "cfg_ahb", 384 "pipe"; 385 386 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; 387 assigned-clock-rates = <20000000>; 388 389 resets = <&gcc GCC_PCIE3_PHY_BCR>, 390 <&gcc GCC_PCIE3PHY_PHY_BCR>; 391 reset-names = "phy", 392 "common"; 393 394 #clock-cells = <0>; 395 clock-output-names = "gcc_pcie3_pipe_clk_src"; 396 397 #phy-cells = <0>; 398 status = "disabled"; 399 }; 400 401 tsens: thermal-sensor@4a9000 { 402 compatible = "qcom,ipq5424-tsens"; 403 reg = <0 0x004a9000 0 0x1000>, 404 <0 0x004a8000 0 0x1000>; 405 interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>; 406 interrupt-names = "combined"; 407 nvmem-cells = <&tsens_mode>, 408 <&tsens_base0>, 409 <&tsens_base1>, 410 <&tsens_sens9_off>, 411 <&tsens_sens10_off>, 412 <&tsens_sens11_off>, 413 <&tsens_sens12_off>, 414 <&tsens_sens13_off>, 415 <&tsens_sens14_off>, 416 <&tsens_sens15_off>; 417 nvmem-cell-names = "mode", 418 "base0", 419 "base1", 420 "tsens_sens9_off", 421 "tsens_sens10_off", 422 "tsens_sens11_off", 423 "tsens_sens12_off", 424 "tsens_sens13_off", 425 "tsens_sens14_off", 426 "tsens_sens15_off"; 427 #qcom,sensors = <7>; 428 #thermal-sensor-cells = <1>; 429 }; 430 431 rng: rng@4c3000 { 432 compatible = "qcom,ipq5424-trng", "qcom,trng"; 433 reg = <0 0x004c3000 0 0x1000>; 434 clocks = <&gcc GCC_PRNG_AHB_CLK>; 435 clock-names = "core"; 436 }; 437 438 system-cache-controller@800000 { 439 compatible = "qcom,ipq5424-llcc"; 440 reg = <0 0x00800000 0 0x200000>; 441 reg-names = "llcc0_base"; 442 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 443 }; 444 445 qfprom@a6000 { 446 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 447 reg = <0x0 0x000a6000 0x0 0x1000>; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 451 cpu_speed_bin: cpu-speed-bin@234 { 452 reg = <0x234 0x1>; 453 bits = <0 8>; 454 }; 455 }; 456 457 tlmm: pinctrl@1000000 { 458 compatible = "qcom,ipq5424-tlmm"; 459 reg = <0 0x01000000 0 0x300000>; 460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 gpio-ranges = <&tlmm 0 0 50>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 467 uart1_pins: uart1-state { 468 pins = "gpio43", "gpio44"; 469 function = "uart1"; 470 drive-strength = <8>; 471 bias-pull-up; 472 }; 473 }; 474 475 gcc: clock-controller@1800000 { 476 compatible = "qcom,ipq5424-gcc"; 477 reg = <0 0x01800000 0 0x40000>; 478 clocks = <&xo_board>, 479 <&sleep_clk>, 480 <&pcie0_phy>, 481 <&pcie1_phy>, 482 <&pcie2_phy>, 483 <&pcie3_phy>, 484 <0>; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 #interconnect-cells = <1>; 488 }; 489 490 tcsr_mutex: hwlock@1905000 { 491 compatible = "qcom,tcsr-mutex"; 492 reg = <0 0x01905000 0 0x20000>; 493 #hwlock-cells = <1>; 494 }; 495 496 tcsr: syscon@1937000 { 497 compatible = "qcom,tcsr-ipq5424", "syscon"; 498 reg = <0 0x01937000 0 0x2a000>; 499 }; 500 501 qupv3: geniqup@1ac0000 { 502 compatible = "qcom,geni-se-qup"; 503 reg = <0 0x01ac0000 0 0x2000>; 504 ranges; 505 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, 506 <&gcc GCC_QUPV3_AHB_SLV_CLK>; 507 clock-names = "m-ahb", "s-ahb"; 508 #address-cells = <2>; 509 #size-cells = <2>; 510 511 uart0: serial@1a80000 { 512 compatible = "qcom,geni-uart"; 513 reg = <0 0x01a80000 0 0x4000>; 514 clocks = <&gcc GCC_QUPV3_UART0_CLK>; 515 clock-names = "se"; 516 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 517 status = "disabled"; 518 }; 519 520 uart1: serial@1a84000 { 521 compatible = "qcom,geni-debug-uart"; 522 reg = <0 0x01a84000 0 0x4000>; 523 clocks = <&gcc GCC_QUPV3_UART1_CLK>; 524 clock-names = "se"; 525 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 526 }; 527 528 spi0: spi@1a90000 { 529 compatible = "qcom,geni-spi"; 530 reg = <0 0x01a90000 0 0x4000>; 531 clocks = <&gcc GCC_QUPV3_SPI0_CLK>; 532 clock-names = "se"; 533 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 539 spi1: spi@1a94000 { 540 compatible = "qcom,geni-spi"; 541 reg = <0 0x01a94000 0 0x4000>; 542 clocks = <&gcc GCC_QUPV3_SPI1_CLK>; 543 clock-names = "se"; 544 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 }; 550 551 sdhc: mmc@7804000 { 552 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; 553 reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; 554 reg-names = "hc", "cqhci"; 555 556 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-names = "hc_irq", "pwr_irq"; 559 560 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 561 <&gcc GCC_SDCC1_APPS_CLK>, 562 <&xo_board>; 563 clock-names = "iface", "core", "xo"; 564 565 supports-cqe; 566 567 status = "disabled"; 568 }; 569 570 intc: interrupt-controller@f200000 { 571 compatible = "arm,gic-v3"; 572 reg = <0 0xf200000 0 0x10000>, /* GICD */ 573 <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ 574 #address-cells = <0>; 575 #interrupt-cells = <0x3>; 576 interrupt-controller; 577 #redistributor-regions = <1>; 578 redistributor-stride = <0x0 0x20000>; 579 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 580 mbi-ranges = <672 128>; 581 msi-controller; 582 }; 583 584 watchdog@f410000 { 585 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt"; 586 reg = <0 0x0f410000 0 0x1000>; 587 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 588 clocks = <&sleep_clk>; 589 }; 590 591 qusb_phy_1: phy@71000 { 592 compatible = "qcom,ipq5424-qusb2-phy"; 593 reg = <0 0x00071000 0 0x180>; 594 #phy-cells = <0>; 595 596 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 597 <&xo_board>; 598 clock-names = "cfg_ahb", "ref"; 599 600 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 601 status = "disabled"; 602 }; 603 604 usb2: usb2@1e00000 { 605 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 606 reg = <0 0x01ef8800 0 0x400>; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges; 610 611 clocks = <&gcc GCC_USB1_MASTER_CLK>, 612 <&gcc GCC_USB1_SLEEP_CLK>, 613 <&gcc GCC_USB1_MOCK_UTMI_CLK>, 614 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 615 <&gcc GCC_CNOC_USB_CLK>; 616 617 clock-names = "core", 618 "sleep", 619 "mock_utmi", 620 "iface", 621 "cfg_noc"; 622 623 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 624 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 625 assigned-clock-rates = <200000000>, 626 <24000000>; 627 628 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 629 <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 630 <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 631 <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; 632 interrupt-names = "pwr_event", 633 "qusb2_phy", 634 "dm_hs_phy_irq", 635 "dp_hs_phy_irq"; 636 637 resets = <&gcc GCC_USB1_BCR>; 638 qcom,select-utmi-as-pipe-clk; 639 status = "disabled"; 640 641 dwc_1: usb@1e00000 { 642 compatible = "snps,dwc3"; 643 reg = <0 0x01e00000 0 0xe000>; 644 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; 645 clock-names = "ref"; 646 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 647 phys = <&qusb_phy_1>; 648 phy-names = "usb2-phy"; 649 tx-fifo-resize; 650 snps,is-utmi-l1-suspend; 651 snps,hird-threshold = /bits/ 8 <0x0>; 652 snps,dis_u2_susphy_quirk; 653 snps,dis_u3_susphy_quirk; 654 }; 655 }; 656 657 qusb_phy_0: phy@7b000 { 658 compatible = "qcom,ipq5424-qusb2-phy"; 659 reg = <0 0x0007b000 0 0x180>; 660 #phy-cells = <0>; 661 662 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 663 <&xo_board>; 664 clock-names = "cfg_ahb", "ref"; 665 666 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 667 status = "disabled"; 668 }; 669 670 ssphy_0: phy@7d000 { 671 compatible = "qcom,ipq5424-qmp-usb3-phy"; 672 reg = <0 0x0007d000 0 0xa00>; 673 #phy-cells = <0>; 674 675 clocks = <&gcc GCC_USB0_AUX_CLK>, 676 <&xo_board>, 677 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 678 <&gcc GCC_USB0_PIPE_CLK>; 679 clock-names = "aux", 680 "ref", 681 "cfg_ahb", 682 "pipe"; 683 684 resets = <&gcc GCC_USB0_PHY_BCR>, 685 <&gcc GCC_USB3PHY_0_PHY_BCR>; 686 reset-names = "phy", 687 "phy_phy"; 688 689 #clock-cells = <0>; 690 clock-output-names = "usb0_pipe_clk"; 691 692 status = "disabled"; 693 }; 694 695 usb3: usb3@8a00000 { 696 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 697 reg = <0 0x08af8800 0 0x400>; 698 699 #address-cells = <2>; 700 #size-cells = <2>; 701 ranges; 702 703 clocks = <&gcc GCC_USB0_MASTER_CLK>, 704 <&gcc GCC_USB0_SLEEP_CLK>, 705 <&gcc GCC_USB0_MOCK_UTMI_CLK>, 706 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 707 <&gcc GCC_CNOC_USB_CLK>; 708 709 clock-names = "core", 710 "sleep", 711 "mock_utmi", 712 "iface", 713 "cfg_noc"; 714 715 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 716 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 717 assigned-clock-rates = <200000000>, 718 <24000000>; 719 720 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 721 <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 722 <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 723 <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-names = "pwr_event", 725 "qusb2_phy", 726 "dm_hs_phy_irq", 727 "dp_hs_phy_irq"; 728 729 resets = <&gcc GCC_USB_BCR>; 730 status = "disabled"; 731 732 dwc_0: usb@8a00000 { 733 compatible = "snps,dwc3"; 734 reg = <0 0x08a00000 0 0xcd00>; 735 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 736 clock-names = "ref"; 737 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 738 phys = <&qusb_phy_0>, <&ssphy_0>; 739 phy-names = "usb2-phy", "usb3-phy"; 740 tx-fifo-resize; 741 snps,is-utmi-l1-suspend; 742 snps,hird-threshold = /bits/ 8 <0x0>; 743 snps,dis_u2_susphy_quirk; 744 snps,dis_u3_susphy_quirk; 745 snps,dis-u1-entry-quirk; 746 snps,dis-u2-entry-quirk; 747 }; 748 }; 749 750 timer@f420000 { 751 compatible = "arm,armv7-timer-mem"; 752 reg = <0 0xf420000 0 0x1000>; 753 ranges = <0 0 0 0x10000000>; 754 #address-cells = <1>; 755 #size-cells = <1>; 756 757 frame@f421000 { 758 reg = <0xf421000 0x1000>, 759 <0xf422000 0x1000>; 760 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 762 frame-number = <0>; 763 }; 764 765 frame@f423000 { 766 reg = <0xf423000 0x1000>; 767 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 768 frame-number = <1>; 769 status = "disabled"; 770 }; 771 772 frame@f425000 { 773 reg = <0xf425000 0x1000>, 774 <0xf426000 0x1000>; 775 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 776 frame-number = <2>; 777 status = "disabled"; 778 }; 779 780 frame@f427000 { 781 reg = <0xf427000 0x1000>; 782 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 783 frame-number = <3>; 784 status = "disabled"; 785 }; 786 787 frame@f429000 { 788 reg = <0xf429000 0x1000>; 789 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 790 frame-number = <4>; 791 status = "disabled"; 792 }; 793 794 frame@f42b000 { 795 reg = <0xf42b000 0x1000>; 796 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 797 frame-number = <5>; 798 status = "disabled"; 799 }; 800 801 frame@f42d000 { 802 reg = <0xf42d000 0x1000>; 803 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 804 frame-number = <6>; 805 status = "disabled"; 806 }; 807 }; 808 809 apss_clk: clock-controller@fa80000 { 810 compatible = "qcom,ipq5424-apss-clk"; 811 reg = <0x0 0x0fa80000 0x0 0x20000>; 812 clocks = <&xo_board>, 813 <&gcc GPLL0>; 814 #clock-cells = <1>; 815 #interconnect-cells = <1>; 816 }; 817 818 pcie3: pcie@40000000 { 819 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 820 reg = <0x0 0x40000000 0x0 0xf1c>, 821 <0x0 0x40000f20 0x0 0xa8>, 822 <0x0 0x40001000 0x0 0x1000>, 823 <0x0 0x000f8000 0x0 0x3000>, 824 <0x0 0x40100000 0x0 0x1000>, 825 <0x0 0x000fe000 0x0 0x1000>; 826 reg-names = "dbi", 827 "elbi", 828 "atu", 829 "parf", 830 "config", 831 "mhi"; 832 device_type = "pci"; 833 linux,pci-domain = <3>; 834 num-lanes = <2>; 835 #address-cells = <3>; 836 #size-cells = <2>; 837 838 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, 839 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; 840 841 msi-map = <0x0 &intc 0x0 0x1000>; 842 843 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; 852 853 interrupt-names = "msi0", 854 "msi1", 855 "msi2", 856 "msi3", 857 "msi4", 858 "msi5", 859 "msi6", 860 "msi7", 861 "global"; 862 863 #interrupt-cells = <1>; 864 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 865 interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 866 <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, 867 <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 868 <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, 871 <&gcc GCC_PCIE3_AXI_S_CLK>, 872 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, 873 <&gcc GCC_PCIE3_RCHNG_CLK>, 874 <&gcc GCC_PCIE3_AHB_CLK>, 875 <&gcc GCC_PCIE3_AUX_CLK>; 876 clock-names = "axi_m", 877 "axi_s", 878 "axi_bridge", 879 "rchng", 880 "ahb", 881 "aux"; 882 883 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>; 884 assigned-clock-rates = <100000000>; 885 886 resets = <&gcc GCC_PCIE3_PIPE_ARES>, 887 <&gcc GCC_PCIE3_CORE_STICKY_RESET>, 888 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, 889 <&gcc GCC_PCIE3_AXI_S_ARES>, 890 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, 891 <&gcc GCC_PCIE3_AXI_M_ARES>, 892 <&gcc GCC_PCIE3_AUX_ARES>, 893 <&gcc GCC_PCIE3_AHB_ARES>; 894 reset-names = "pipe", 895 "sticky", 896 "axi_s_sticky", 897 "axi_s", 898 "axi_m_sticky", 899 "axi_m", 900 "aux", 901 "ahb"; 902 903 phys = <&pcie3_phy>; 904 phy-names = "pciephy"; 905 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, 906 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; 907 interconnect-names = "pcie-mem", "cpu-pcie"; 908 909 status = "disabled"; 910 911 pcie@0 { 912 device_type = "pci"; 913 reg = <0x0 0x0 0x0 0x0 0x0>; 914 bus-range = <0x01 0xff>; 915 916 #address-cells = <3>; 917 #size-cells = <2>; 918 ranges; 919 }; 920 }; 921 922 pcie2: pcie@50000000 { 923 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 924 reg = <0x0 0x50000000 0x0 0xf1c>, 925 <0x0 0x50000f20 0x0 0xa8>, 926 <0x0 0x50001000 0x0 0x1000>, 927 <0x0 0x000f0000 0x0 0x3000>, 928 <0x0 0x50100000 0x0 0x1000>, 929 <0x0 0x000f6000 0x0 0x1000>; 930 reg-names = "dbi", 931 "elbi", 932 "atu", 933 "parf", 934 "config", 935 "mhi"; 936 device_type = "pci"; 937 linux,pci-domain = <2>; 938 num-lanes = <2>; 939 #address-cells = <3>; 940 #size-cells = <2>; 941 942 ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, 943 <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; 944 945 msi-map = <0x0 &intc 0x0 0x1000>; 946 947 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "msi0", 957 "msi1", 958 "msi2", 959 "msi3", 960 "msi4", 961 "msi5", 962 "msi6", 963 "msi7", 964 "global"; 965 966 #interrupt-cells = <1>; 967 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 968 interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 969 <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 970 <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 971 <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 972 973 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, 974 <&gcc GCC_PCIE2_AXI_S_CLK>, 975 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, 976 <&gcc GCC_PCIE2_RCHNG_CLK>, 977 <&gcc GCC_PCIE2_AHB_CLK>, 978 <&gcc GCC_PCIE2_AUX_CLK>; 979 clock-names = "axi_m", 980 "axi_s", 981 "axi_bridge", 982 "rchng", 983 "ahb", 984 "aux"; 985 986 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>; 987 assigned-clock-rates = <100000000>; 988 989 resets = <&gcc GCC_PCIE2_PIPE_ARES>, 990 <&gcc GCC_PCIE2_CORE_STICKY_RESET>, 991 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, 992 <&gcc GCC_PCIE2_AXI_S_ARES>, 993 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, 994 <&gcc GCC_PCIE2_AXI_M_ARES>, 995 <&gcc GCC_PCIE2_AUX_ARES>, 996 <&gcc GCC_PCIE2_AHB_ARES>; 997 reset-names = "pipe", 998 "sticky", 999 "axi_s_sticky", 1000 "axi_s", 1001 "axi_m_sticky", 1002 "axi_m", 1003 "aux", 1004 "ahb"; 1005 1006 phys = <&pcie2_phy>; 1007 phy-names = "pciephy"; 1008 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, 1009 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; 1010 interconnect-names = "pcie-mem", "cpu-pcie"; 1011 1012 status = "disabled"; 1013 1014 pcie@0 { 1015 device_type = "pci"; 1016 reg = <0x0 0x0 0x0 0x0 0x0>; 1017 bus-range = <0x01 0xff>; 1018 1019 #address-cells = <3>; 1020 #size-cells = <2>; 1021 ranges; 1022 }; 1023 }; 1024 1025 pcie1: pcie@60000000 { 1026 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 1027 reg = <0x0 0x60000000 0x0 0xf1c>, 1028 <0x0 0x60000f20 0x0 0xa8>, 1029 <0x0 0x60001000 0x0 0x1000>, 1030 <0x0 0x00088000 0x0 0x3000>, 1031 <0x0 0x60100000 0x0 0x1000>, 1032 <0x0 0x0008e000 0x0 0x1000>; 1033 reg-names = "dbi", 1034 "elbi", 1035 "atu", 1036 "parf", 1037 "config", 1038 "mhi"; 1039 device_type = "pci"; 1040 linux,pci-domain = <1>; 1041 num-lanes = <1>; 1042 #address-cells = <3>; 1043 #size-cells = <2>; 1044 1045 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, 1046 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; 1047 1048 msi-map = <0x0 &intc 0x0 0x1000>; 1049 1050 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-names = "msi0", 1060 "msi1", 1061 "msi2", 1062 "msi3", 1063 "msi4", 1064 "msi5", 1065 "msi6", 1066 "msi7", 1067 "global"; 1068 1069 #interrupt-cells = <1>; 1070 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1071 interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1072 <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1073 <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1074 <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 1075 1076 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, 1077 <&gcc GCC_PCIE1_AXI_S_CLK>, 1078 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, 1079 <&gcc GCC_PCIE1_RCHNG_CLK>, 1080 <&gcc GCC_PCIE1_AHB_CLK>, 1081 <&gcc GCC_PCIE1_AUX_CLK>; 1082 clock-names = "axi_m", 1083 "axi_s", 1084 "axi_bridge", 1085 "rchng", 1086 "ahb", 1087 "aux"; 1088 1089 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>; 1090 assigned-clock-rates = <100000000>; 1091 1092 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 1093 <&gcc GCC_PCIE1_CORE_STICKY_RESET>, 1094 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, 1095 <&gcc GCC_PCIE1_AXI_S_ARES>, 1096 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, 1097 <&gcc GCC_PCIE1_AXI_M_ARES>, 1098 <&gcc GCC_PCIE1_AUX_ARES>, 1099 <&gcc GCC_PCIE1_AHB_ARES>; 1100 reset-names = "pipe", 1101 "sticky", 1102 "axi_s_sticky", 1103 "axi_s", 1104 "axi_m_sticky", 1105 "axi_m", 1106 "aux", 1107 "ahb"; 1108 1109 phys = <&pcie1_phy>; 1110 phy-names = "pciephy"; 1111 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, 1112 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; 1113 interconnect-names = "pcie-mem", "cpu-pcie"; 1114 1115 status = "disabled"; 1116 1117 pcie@0 { 1118 device_type = "pci"; 1119 reg = <0x0 0x0 0x0 0x0 0x0>; 1120 bus-range = <0x01 0xff>; 1121 1122 #address-cells = <3>; 1123 #size-cells = <2>; 1124 ranges; 1125 }; 1126 }; 1127 1128 pcie0: pcie@70000000 { 1129 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 1130 reg = <0x0 0x70000000 0x0 0xf1c>, 1131 <0x0 0x70000f20 0x0 0xa8>, 1132 <0x0 0x70001000 0x0 0x1000>, 1133 <0x0 0x00080000 0x0 0x3000>, 1134 <0x0 0x70100000 0x0 0x1000>, 1135 <0x0 0x00086000 0x0 0x1000>; 1136 reg-names = "dbi", 1137 "elbi", 1138 "atu", 1139 "parf", 1140 "config", 1141 "mhi"; 1142 device_type = "pci"; 1143 linux,pci-domain = <0>; 1144 num-lanes = <1>; 1145 #address-cells = <3>; 1146 #size-cells = <2>; 1147 1148 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, 1149 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; 1150 1151 msi-map = <0x0 &intc 0x0 0x1000>; 1152 1153 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1162 interrupt-names = "msi0", 1163 "msi1", 1164 "msi2", 1165 "msi3", 1166 "msi4", 1167 "msi5", 1168 "msi6", 1169 "msi7", 1170 "global"; 1171 1172 #interrupt-cells = <1>; 1173 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1174 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 1175 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 1176 <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 1177 <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; 1178 1179 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, 1180 <&gcc GCC_PCIE0_AXI_S_CLK>, 1181 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 1182 <&gcc GCC_PCIE0_RCHNG_CLK>, 1183 <&gcc GCC_PCIE0_AHB_CLK>, 1184 <&gcc GCC_PCIE0_AUX_CLK>; 1185 clock-names = "axi_m", 1186 "axi_s", 1187 "axi_bridge", 1188 "rchng", 1189 "ahb", 1190 "aux"; 1191 1192 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>; 1193 assigned-clock-rates = <100000000>; 1194 1195 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 1196 <&gcc GCC_PCIE0_CORE_STICKY_RESET>, 1197 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, 1198 <&gcc GCC_PCIE0_AXI_S_ARES>, 1199 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, 1200 <&gcc GCC_PCIE0_AXI_M_ARES>, 1201 <&gcc GCC_PCIE0_AUX_ARES>, 1202 <&gcc GCC_PCIE0_AHB_ARES>; 1203 reset-names = "pipe", 1204 "sticky", 1205 "axi_s_sticky", 1206 "axi_s", 1207 "axi_m_sticky", 1208 "axi_m", 1209 "aux", 1210 "ahb"; 1211 1212 phys = <&pcie0_phy>; 1213 phy-names = "pciephy"; 1214 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, 1215 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; 1216 interconnect-names = "pcie-mem", "cpu-pcie"; 1217 1218 status = "disabled"; 1219 1220 pcie@0 { 1221 device_type = "pci"; 1222 reg = <0x0 0x0 0x0 0x0 0x0>; 1223 bus-range = <0x01 0xff>; 1224 1225 #address-cells = <3>; 1226 #size-cells = <2>; 1227 ranges; 1228 }; 1229 }; 1230 }; 1231 1232 thermal_zones: thermal-zones { 1233 cpu0-thermal { 1234 polling-delay-passive = <100>; 1235 thermal-sensors = <&tsens 14>; 1236 1237 trips { 1238 cpu-critical { 1239 temperature = <120000>; 1240 hysteresis = <9000>; 1241 type = "critical"; 1242 }; 1243 1244 cpu-passive { 1245 temperature = <110000>; 1246 hysteresis = <9000>; 1247 type = "passive"; 1248 }; 1249 }; 1250 }; 1251 1252 cpu1-thermal { 1253 polling-delay-passive = <100>; 1254 thermal-sensors = <&tsens 12>; 1255 1256 trips { 1257 cpu-critical { 1258 temperature = <120000>; 1259 hysteresis = <9000>; 1260 type = "critical"; 1261 }; 1262 1263 cpu-passive { 1264 temperature = <110000>; 1265 hysteresis = <9000>; 1266 type = "passive"; 1267 }; 1268 }; 1269 }; 1270 1271 cpu2-thermal { 1272 polling-delay-passive = <100>; 1273 thermal-sensors = <&tsens 11>; 1274 1275 trips { 1276 cpu-critical { 1277 temperature = <120000>; 1278 hysteresis = <9000>; 1279 type = "critical"; 1280 }; 1281 1282 cpu-passive { 1283 temperature = <110000>; 1284 hysteresis = <9000>; 1285 type = "passive"; 1286 }; 1287 }; 1288 }; 1289 1290 cpu3-thermal { 1291 polling-delay-passive = <100>; 1292 thermal-sensors = <&tsens 13>; 1293 1294 trips { 1295 cpu-critical { 1296 temperature = <120000>; 1297 hysteresis = <9000>; 1298 type = "critical"; 1299 }; 1300 1301 cpu-passive { 1302 temperature = <110000>; 1303 hysteresis = <9000>; 1304 type = "passive"; 1305 }; 1306 }; 1307 }; 1308 1309 wcss-tile2-thermal { 1310 thermal-sensors = <&tsens 9>; 1311 1312 trips { 1313 wcss-tile2-critical { 1314 temperature = <125000>; 1315 hysteresis = <9000>; 1316 type = "critical"; 1317 }; 1318 }; 1319 }; 1320 1321 wcss-tile3-thermal { 1322 thermal-sensors = <&tsens 10>; 1323 1324 trips { 1325 wcss-tile3-critical { 1326 temperature = <125000>; 1327 hysteresis = <9000>; 1328 type = "critical"; 1329 }; 1330 }; 1331 }; 1332 1333 top-glue-thermal { 1334 thermal-sensors = <&tsens 15>; 1335 1336 trips { 1337 top-glue-critical { 1338 temperature = <125000>; 1339 hysteresis = <9000>; 1340 type = "critical"; 1341 }; 1342 }; 1343 }; 1344 }; 1345 1346 timer { 1347 compatible = "arm,armv8-timer"; 1348 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1349 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1350 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1351 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1352 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1353 }; 1354}; 1355