1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * IPQ5018 SoC device tree source 4 * 5 * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,gcc-ipq5018.h> 10#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,gcc-ipq5018.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 gephy_rx_clk: gephy-rx-clk { 22 compatible = "fixed-clock"; 23 clock-frequency = <125000000>; 24 #clock-cells = <0>; 25 }; 26 27 gephy_tx_clk: gephy-tx-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <125000000>; 30 #clock-cells = <0>; 31 }; 32 33 ref_96mhz_clk: ref-96mhz-clk { 34 compatible = "fixed-factor-clock"; 35 clocks = <&xo_clk>; 36 #clock-cells = <0>; 37 clock-div = <1>; 38 clock-mult = <2>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 xo_board_clk: xo-board-clk { 47 compatible = "fixed-factor-clock"; 48 clocks = <&ref_96mhz_clk>; 49 #clock-cells = <0>; 50 }; 51 52 xo_clk: xo-clk { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <48000000>; 56 }; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0>; 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 #cooling-cells = <2>; 72 }; 73 74 cpu1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 enable-method = "psci"; 79 next-level-cache = <&l2_0>; 80 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 81 operating-points-v2 = <&cpu_opp_table>; 82 #cooling-cells = <2>; 83 }; 84 85 l2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-size = <0x80000>; 89 cache-unified; 90 }; 91 }; 92 93 cpu_opp_table: opp-table-cpu { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-800000000 { 98 opp-hz = /bits/ 64 <800000000>; 99 opp-microvolt = <1100000>; 100 clock-latency-ns = <200000>; 101 }; 102 103 opp-1008000000 { 104 opp-hz = /bits/ 64 <1008000000>; 105 opp-microvolt = <1100000>; 106 clock-latency-ns = <200000>; 107 }; 108 }; 109 110 firmware { 111 scm { 112 compatible = "qcom,scm-ipq5018", "qcom,scm"; 113 qcom,dload-mode = <&tcsr 0x6100>; 114 qcom,sdi-enabled; 115 }; 116 }; 117 118 memory@40000000 { 119 device_type = "memory"; 120 /* We expect the bootloader to fill in the size */ 121 reg = <0x0 0x40000000 0x0 0x0>; 122 }; 123 124 pmu { 125 compatible = "arm,cortex-a53-pmu"; 126 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 127 }; 128 129 psci { 130 compatible = "arm,psci-1.0"; 131 method = "smc"; 132 }; 133 134 reserved-memory { 135 #address-cells = <2>; 136 #size-cells = <2>; 137 ranges; 138 139 bootloader@4a800000 { 140 reg = <0x0 0x4a800000 0x0 0x200000>; 141 no-map; 142 }; 143 144 sbl@4aa00000 { 145 reg = <0x0 0x4aa00000 0x0 0x100000>; 146 no-map; 147 }; 148 149 smem@4ab00000 { 150 compatible = "qcom,smem"; 151 reg = <0x0 0x4ab00000 0x0 0x100000>; 152 no-map; 153 154 hwlocks = <&tcsr_mutex 3>; 155 }; 156 157 tz_region: tz@4ac00000 { 158 reg = <0x0 0x4ac00000 0x0 0x200000>; 159 no-map; 160 }; 161 }; 162 163 soc: soc@0 { 164 compatible = "simple-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges = <0 0 0 0xffffffff>; 168 169 usbphy0: phy@5b000 { 170 compatible = "qcom,ipq5018-usb-hsphy"; 171 reg = <0x0005b000 0x120>; 172 173 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; 174 175 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 176 177 #phy-cells = <0>; 178 179 status = "disabled"; 180 }; 181 182 pcie1_phy: phy@7e000 { 183 compatible = "qcom,ipq5018-uniphy-pcie-phy"; 184 reg = <0x0007e000 0x800>; 185 186 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 187 188 resets = <&gcc GCC_PCIE1_PHY_BCR>, 189 <&gcc GCC_PCIE1PHY_PHY_BCR>; 190 191 #clock-cells = <0>; 192 #phy-cells = <0>; 193 194 num-lanes = <1>; 195 196 status = "disabled"; 197 }; 198 199 pcie0_phy: phy@86000 { 200 compatible = "qcom,ipq5018-uniphy-pcie-phy"; 201 reg = <0x00086000 0x1000>; 202 203 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 204 205 resets = <&gcc GCC_PCIE0_PHY_BCR>, 206 <&gcc GCC_PCIE0PHY_PHY_BCR>; 207 208 #clock-cells = <0>; 209 #phy-cells = <0>; 210 211 num-lanes = <2>; 212 213 status = "disabled"; 214 }; 215 216 mdio0: mdio@88000 { 217 compatible = "qcom,ipq5018-mdio"; 218 reg = <0x00088000 0x64>, 219 <0x019475c4 0x4>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 223 clocks = <&gcc GCC_MDIO0_AHB_CLK>; 224 clock-names = "gcc_mdio_ahb_clk"; 225 226 status = "disabled"; 227 228 ge_phy: ethernet-phy@7 { 229 compatible = "ethernet-phy-id004d.d0c0"; 230 reg = <7>; 231 232 resets = <&gcc GCC_GEPHY_MISC_ARES>; 233 }; 234 }; 235 236 mdio1: mdio@90000 { 237 compatible = "qcom,ipq5018-mdio"; 238 reg = <0x00090000 0x64>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 clocks = <&gcc GCC_MDIO1_AHB_CLK>; 243 clock-names = "gcc_mdio_ahb_clk"; 244 245 status = "disabled"; 246 }; 247 248 cmn_pll: clock-controller@9b000 { 249 compatible = "qcom,ipq5018-cmn-pll"; 250 reg = <0x0009b000 0x800>; 251 clocks = <&ref_96mhz_clk>, 252 <&gcc GCC_CMN_BLK_AHB_CLK>, 253 <&gcc GCC_CMN_BLK_SYS_CLK>; 254 clock-names = "ref", 255 "ahb", 256 "sys"; 257 #clock-cells = <1>; 258 assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; 259 assigned-clock-rates-u64 = /bits/ 64 <9600000000>; 260 }; 261 262 qfprom: qfprom@a0000 { 263 compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; 264 reg = <0x000a0000 0x1000>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 268 tsens_mode: mode@249 { 269 reg = <0x249 0x1>; 270 bits = <0 3>; 271 }; 272 273 tsens_base1: base1@249 { 274 reg = <0x249 0x2>; 275 bits = <3 8>; 276 }; 277 278 tsens_base2: base2@24a { 279 reg = <0x24a 0x2>; 280 bits = <3 8>; 281 }; 282 283 tsens_s0_p1: s0-p1@24b { 284 reg = <0x24b 0x2>; 285 bits = <2 6>; 286 }; 287 288 tsens_s0_p2: s0-p2@24c { 289 reg = <0x24c 0x1>; 290 bits = <1 6>; 291 }; 292 293 tsens_s1_p1: s1-p1@24c { 294 reg = <0x24c 0x2>; 295 bits = <7 6>; 296 }; 297 298 tsens_s1_p2: s1-p2@24d { 299 reg = <0x24d 0x2>; 300 bits = <5 6>; 301 }; 302 303 tsens_s2_p1: s2-p1@24e { 304 reg = <0x24e 0x2>; 305 bits = <3 6>; 306 }; 307 308 tsens_s2_p2: s2-p2@24f { 309 reg = <0x24f 0x1>; 310 bits = <1 6>; 311 }; 312 313 tsens_s3_p1: s3-p1@24f { 314 reg = <0x24f 0x2>; 315 bits = <7 6>; 316 }; 317 318 tsens_s3_p2: s3-p2@250 { 319 reg = <0x250 0x2>; 320 bits = <5 6>; 321 }; 322 323 tsens_s4_p1: s4-p1@251 { 324 reg = <0x251 0x2>; 325 bits = <3 6>; 326 }; 327 328 tsens_s4_p2: s4-p2@254 { 329 reg = <0x254 0x1>; 330 bits = <0 6>; 331 }; 332 }; 333 334 prng: rng@e3000 { 335 compatible = "qcom,prng-ee"; 336 reg = <0x000e3000 0x1000>; 337 clocks = <&gcc GCC_PRNG_AHB_CLK>; 338 clock-names = "core"; 339 status = "disabled"; 340 }; 341 342 tsens: thermal-sensor@4a9000 { 343 compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; 344 reg = <0x004a9000 0x1000>, 345 <0x004a8000 0x1000>; 346 347 nvmem-cells = <&tsens_mode>, 348 <&tsens_base1>, 349 <&tsens_base2>, 350 <&tsens_s0_p1>, 351 <&tsens_s0_p2>, 352 <&tsens_s1_p1>, 353 <&tsens_s1_p2>, 354 <&tsens_s2_p1>, 355 <&tsens_s2_p2>, 356 <&tsens_s3_p1>, 357 <&tsens_s3_p2>, 358 <&tsens_s4_p1>, 359 <&tsens_s4_p2>; 360 361 nvmem-cell-names = "mode", 362 "base1", 363 "base2", 364 "s0_p1", 365 "s0_p2", 366 "s1_p1", 367 "s1_p2", 368 "s2_p1", 369 "s2_p2", 370 "s3_p1", 371 "s3_p2", 372 "s4_p1", 373 "s4_p2"; 374 375 interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>; 376 interrupt-names = "uplow"; 377 #qcom,sensors = <5>; 378 #thermal-sensor-cells = <1>; 379 }; 380 381 cryptobam: dma-controller@704000 { 382 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 383 reg = <0x00704000 0x20000>; 384 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 385 386 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 387 clock-names = "bam_clk"; 388 389 #dma-cells = <1>; 390 qcom,ee = <1>; 391 qcom,controlled-remotely; 392 }; 393 394 crypto: crypto@73a000 { 395 compatible = "qcom,crypto-v5.1"; 396 reg = <0x0073a000 0x6000>; 397 398 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 399 <&gcc GCC_CRYPTO_AXI_CLK>, 400 <&gcc GCC_CRYPTO_CLK>; 401 clock-names = "iface", 402 "bus", 403 "core"; 404 405 dmas = <&cryptobam 2>, 406 <&cryptobam 3>; 407 dma-names = "rx", 408 "tx"; 409 }; 410 411 tlmm: pinctrl@1000000 { 412 compatible = "qcom,ipq5018-tlmm"; 413 reg = <0x01000000 0x300000>; 414 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 gpio-ranges = <&tlmm 0 0 47>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 421 uart1_pins: uart1-state { 422 pins = "gpio31", "gpio32", "gpio33", "gpio34"; 423 function = "blsp1_uart1"; 424 drive-strength = <8>; 425 bias-pull-down; 426 }; 427 }; 428 429 gcc: clock-controller@1800000 { 430 compatible = "qcom,gcc-ipq5018"; 431 reg = <0x01800000 0x80000>; 432 clocks = <&xo_board_clk>, 433 <&sleep_clk>, 434 <&pcie0_phy>, 435 <&pcie1_phy>, 436 <0>, 437 <&gephy_rx_clk>, 438 <&gephy_tx_clk>, 439 <0>, 440 <0>; 441 #clock-cells = <1>; 442 #reset-cells = <1>; 443 }; 444 445 tcsr_mutex: hwlock@1905000 { 446 compatible = "qcom,tcsr-mutex"; 447 reg = <0x01905000 0x20000>; 448 #hwlock-cells = <1>; 449 }; 450 451 tcsr: syscon@1937000 { 452 compatible = "qcom,tcsr-ipq5018", "syscon"; 453 reg = <0x01937000 0x21000>; 454 }; 455 456 sdhc_1: mmc@7804000 { 457 compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; 458 reg = <0x7804000 0x1000>; 459 reg-names = "hc"; 460 461 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "hc_irq", "pwr_irq"; 464 465 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 466 <&gcc GCC_SDCC1_APPS_CLK>, 467 <&xo_board_clk>; 468 clock-names = "iface", "core", "xo"; 469 non-removable; 470 status = "disabled"; 471 }; 472 473 blsp_dma: dma-controller@7884000 { 474 compatible = "qcom,bam-v1.7.0"; 475 reg = <0x07884000 0x1d000>; 476 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 478 clock-names = "bam_clk"; 479 #dma-cells = <1>; 480 qcom,ee = <0>; 481 }; 482 483 blsp1_uart1: serial@78af000 { 484 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 485 reg = <0x078af000 0x200>; 486 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 488 <&gcc GCC_BLSP1_AHB_CLK>; 489 clock-names = "core", "iface"; 490 status = "disabled"; 491 }; 492 493 blsp1_uart2: serial@78b0000 { 494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 495 reg = <0x078b0000 0x200>; 496 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 498 <&gcc GCC_BLSP1_AHB_CLK>; 499 clock-names = "core", "iface"; 500 status = "disabled"; 501 }; 502 503 blsp1_spi1: spi@78b5000 { 504 compatible = "qcom,spi-qup-v2.2.1"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 reg = <0x078b5000 0x600>; 508 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 510 <&gcc GCC_BLSP1_AHB_CLK>; 511 clock-names = "core", "iface"; 512 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 513 dma-names = "tx", "rx"; 514 status = "disabled"; 515 }; 516 517 blsp1_i2c3: i2c@78b7000 { 518 compatible = "qcom,i2c-qup-v2.2.1"; 519 reg = <0x078b7000 0x600>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 524 <&gcc GCC_BLSP1_AHB_CLK>; 525 clock-names = "core", "iface"; 526 clock-frequency = <400000>; 527 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 528 dma-names = "tx", "rx"; 529 status = "disabled"; 530 }; 531 532 qpic_bam: dma-controller@7984000 { 533 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 534 reg = <0x07984000 0x1c000>; 535 536 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 537 538 clocks = <&gcc GCC_QPIC_AHB_CLK>; 539 clock-names = "bam_clk"; 540 541 #dma-cells = <1>; 542 qcom,ee = <0>; 543 544 status = "disabled"; 545 }; 546 547 qpic_nand: spi@79b0000 { 548 compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; 549 reg = <0x079b0000 0x10000>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 553 clocks = <&gcc GCC_QPIC_CLK>, 554 <&gcc GCC_QPIC_AHB_CLK>, 555 <&gcc GCC_QPIC_IO_MACRO_CLK>; 556 clock-names = "core", 557 "aon", 558 "iom"; 559 560 dmas = <&qpic_bam 0>, 561 <&qpic_bam 1>, 562 <&qpic_bam 2>; 563 dma-names = "tx", 564 "rx", 565 "cmd"; 566 567 status = "disabled"; 568 }; 569 570 usb: usb@8af8800 { 571 compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; 572 reg = <0x08af8800 0x400>; 573 574 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 575 interrupt-names = "hs_phy_irq"; 576 577 clocks = <&gcc GCC_USB0_MASTER_CLK>, 578 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 579 <&gcc GCC_USB0_SLEEP_CLK>, 580 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 581 clock-names = "core", 582 "iface", 583 "sleep", 584 "mock_utmi"; 585 586 resets = <&gcc GCC_USB0_BCR>; 587 588 qcom,select-utmi-as-pipe-clk; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges; 592 593 status = "disabled"; 594 595 usb_dwc: usb@8a00000 { 596 compatible = "snps,dwc3"; 597 reg = <0x08a00000 0xe000>; 598 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 599 clock-names = "ref"; 600 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 601 phy-names = "usb2-phy"; 602 phys = <&usbphy0>; 603 tx-fifo-resize; 604 snps,is-utmi-l1-suspend; 605 snps,hird-threshold = /bits/ 8 <0x0>; 606 snps,dis_u2_susphy_quirk; 607 snps,dis_u3_susphy_quirk; 608 }; 609 }; 610 611 intc: interrupt-controller@b000000 { 612 compatible = "qcom,msm-qgic2"; 613 reg = <0x0b000000 0x1000>, /* GICD */ 614 <0x0b002000 0x2000>, /* GICC */ 615 <0x0b001000 0x1000>, /* GICH */ 616 <0x0b004000 0x2000>; /* GICV */ 617 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 618 interrupt-controller; 619 #interrupt-cells = <3>; 620 #address-cells = <1>; 621 #size-cells = <1>; 622 ranges = <0 0x0b00a000 0x1ffa>; 623 624 v2m0: v2m@0 { 625 compatible = "arm,gic-v2m-frame"; 626 reg = <0x00000000 0xff8>; 627 msi-controller; 628 }; 629 630 v2m1: v2m@1000 { 631 compatible = "arm,gic-v2m-frame"; 632 reg = <0x00001000 0xff8>; 633 msi-controller; 634 }; 635 }; 636 637 watchdog: watchdog@b017000 { 638 compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt"; 639 reg = <0x0b017000 0x40>; 640 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 641 clocks = <&sleep_clk>; 642 }; 643 644 apcs_glb: mailbox@b111000 { 645 compatible = "qcom,ipq5018-apcs-apps-global", 646 "qcom,ipq6018-apcs-apps-global"; 647 reg = <0x0b111000 0x1000>; 648 #clock-cells = <1>; 649 clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>; 650 clock-names = "pll", "xo", "gpll0"; 651 #mbox-cells = <1>; 652 }; 653 654 a53pll: clock@b116000 { 655 compatible = "qcom,ipq5018-a53pll"; 656 reg = <0x0b116000 0x40>; 657 #clock-cells = <0>; 658 clocks = <&xo_board_clk>; 659 clock-names = "xo"; 660 }; 661 662 timer@b120000 { 663 compatible = "arm,armv7-timer-mem"; 664 reg = <0x0b120000 0x1000>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 ranges; 668 669 frame@b120000 { 670 reg = <0x0b121000 0x1000>, 671 <0x0b122000 0x1000>; 672 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 674 frame-number = <0>; 675 }; 676 677 frame@b123000 { 678 reg = <0xb123000 0x1000>; 679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 680 frame-number = <1>; 681 status = "disabled"; 682 }; 683 684 frame@b124000 { 685 frame-number = <2>; 686 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 687 reg = <0x0b124000 0x1000>; 688 status = "disabled"; 689 }; 690 691 frame@b125000 { 692 reg = <0x0b125000 0x1000>; 693 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 694 frame-number = <3>; 695 status = "disabled"; 696 }; 697 698 frame@b126000 { 699 reg = <0x0b126000 0x1000>; 700 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 701 frame-number = <4>; 702 status = "disabled"; 703 }; 704 705 frame@b127000 { 706 reg = <0x0b127000 0x1000>; 707 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 708 frame-number = <5>; 709 status = "disabled"; 710 }; 711 712 frame@b128000 { 713 reg = <0x0b128000 0x1000>; 714 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 715 frame-number = <6>; 716 status = "disabled"; 717 }; 718 }; 719 720 pcie1: pcie@80000000 { 721 compatible = "qcom,pcie-ipq5018"; 722 reg = <0x80000000 0xf1d>, 723 <0x80000f20 0xa8>, 724 <0x80001000 0x1000>, 725 <0x00078000 0x3000>, 726 <0x80100000 0x1000>, 727 <0x0007b000 0x1000>; 728 reg-names = "dbi", 729 "elbi", 730 "atu", 731 "parf", 732 "config", 733 "mhi"; 734 device_type = "pci"; 735 linux,pci-domain = <1>; 736 bus-range = <0x00 0xff>; 737 num-lanes = <1>; 738 #address-cells = <3>; 739 #size-cells = <2>; 740 741 /* The controller supports Gen3, but the connected PHY is Gen2-capable */ 742 max-link-speed = <2>; 743 744 phys = <&pcie1_phy>; 745 phy-names = "pciephy"; 746 747 ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, 748 <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; 749 750 msi-map = <0x0 &v2m0 0x0 0xff8>; 751 752 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "msi0", 762 "msi1", 763 "msi2", 764 "msi3", 765 "msi4", 766 "msi5", 767 "msi6", 768 "msi7", 769 "global"; 770 771 #interrupt-cells = <1>; 772 interrupt-map-mask = <0 0 0 0x7>; 773 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 774 <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 775 <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 776 <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 777 778 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 779 <&gcc GCC_PCIE1_AXI_M_CLK>, 780 <&gcc GCC_PCIE1_AXI_S_CLK>, 781 <&gcc GCC_PCIE1_AHB_CLK>, 782 <&gcc GCC_PCIE1_AUX_CLK>, 783 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; 784 clock-names = "iface", 785 "axi_m", 786 "axi_s", 787 "ahb", 788 "aux", 789 "axi_bridge"; 790 791 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 792 <&gcc GCC_PCIE1_SLEEP_ARES>, 793 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 794 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 795 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 796 <&gcc GCC_PCIE1_AHB_ARES>, 797 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, 798 <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; 799 reset-names = "pipe", 800 "sleep", 801 "sticky", 802 "axi_m", 803 "axi_s", 804 "ahb", 805 "axi_m_sticky", 806 "axi_s_sticky"; 807 808 status = "disabled"; 809 810 pcie@0 { 811 device_type = "pci"; 812 reg = <0x0 0x0 0x0 0x0 0x0>; 813 bus-range = <0x01 0xff>; 814 815 #address-cells = <3>; 816 #size-cells = <2>; 817 ranges; 818 }; 819 }; 820 821 pcie0: pcie@a0000000 { 822 compatible = "qcom,pcie-ipq5018"; 823 reg = <0xa0000000 0xf1d>, 824 <0xa0000f20 0xa8>, 825 <0xa0001000 0x1000>, 826 <0x00080000 0x3000>, 827 <0xa0100000 0x1000>, 828 <0x00083000 0x1000>; 829 reg-names = "dbi", 830 "elbi", 831 "atu", 832 "parf", 833 "config", 834 "mhi"; 835 device_type = "pci"; 836 linux,pci-domain = <0>; 837 bus-range = <0x00 0xff>; 838 num-lanes = <2>; 839 #address-cells = <3>; 840 #size-cells = <2>; 841 842 /* The controller supports Gen3, but the connected PHY is Gen2-capable */ 843 max-link-speed = <2>; 844 845 phys = <&pcie0_phy>; 846 phy-names = "pciephy"; 847 848 ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, 849 <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; 850 851 msi-map = <0x0 &v2m0 0x0 0xff8>; 852 853 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "msi0", 863 "msi1", 864 "msi2", 865 "msi3", 866 "msi4", 867 "msi5", 868 "msi6", 869 "msi7", 870 "global"; 871 872 #interrupt-cells = <1>; 873 interrupt-map-mask = <0 0 0 0x7>; 874 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 875 <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 876 <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 877 <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 878 879 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 880 <&gcc GCC_PCIE0_AXI_M_CLK>, 881 <&gcc GCC_PCIE0_AXI_S_CLK>, 882 <&gcc GCC_PCIE0_AHB_CLK>, 883 <&gcc GCC_PCIE0_AUX_CLK>, 884 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; 885 clock-names = "iface", 886 "axi_m", 887 "axi_s", 888 "ahb", 889 "aux", 890 "axi_bridge"; 891 892 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 893 <&gcc GCC_PCIE0_SLEEP_ARES>, 894 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 895 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 896 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 897 <&gcc GCC_PCIE0_AHB_ARES>, 898 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 899 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 900 reset-names = "pipe", 901 "sleep", 902 "sticky", 903 "axi_m", 904 "axi_s", 905 "ahb", 906 "axi_m_sticky", 907 "axi_s_sticky"; 908 909 status = "disabled"; 910 911 pcie@0 { 912 device_type = "pci"; 913 reg = <0x0 0x0 0x0 0x0 0x0>; 914 bus-range = <0x01 0xff>; 915 916 #address-cells = <3>; 917 #size-cells = <2>; 918 ranges; 919 }; 920 }; 921 }; 922 923 thermal-zones { 924 cpu-thermal { 925 thermal-sensors = <&tsens 2>; 926 927 trips { 928 cpu-critical { 929 temperature = <120000>; 930 hysteresis = <1000>; 931 type = "critical"; 932 }; 933 934 cpu_alert: cpu-passive { 935 temperature = <100000>; 936 hysteresis = <1000>; 937 type = "passive"; 938 }; 939 }; 940 941 cooling-maps { 942 map0 { 943 trip = <&cpu_alert>; 944 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 945 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 946 }; 947 }; 948 }; 949 950 gephy-thermal { 951 thermal-sensors = <&tsens 4>; 952 953 trips { 954 gephy-critical { 955 temperature = <120000>; 956 hysteresis = <1000>; 957 type = "critical"; 958 }; 959 }; 960 }; 961 962 top-glue-thermal { 963 thermal-sensors = <&tsens 3>; 964 965 trips { 966 top-glue-critical { 967 temperature = <120000>; 968 hysteresis = <1000>; 969 type = "critical"; 970 }; 971 }; 972 }; 973 974 ubi32-thermal { 975 thermal-sensors = <&tsens 1>; 976 977 trips { 978 ubi32-critical { 979 temperature = <120000>; 980 hysteresis = <1000>; 981 type = "critical"; 982 }; 983 }; 984 }; 985 }; 986 987 timer { 988 compatible = "arm,armv8-timer"; 989 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 990 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 991 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 992 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 993 }; 994}; 995