xref: /linux/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2025 Grinn sp. z o.o.
4 * Author: Mateusz Koza <mateusz.koza@grinn-global.com>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10	chassis-type = "embedded";
11
12	aliases {
13		ethernet0 = &eth;
14		i2c0 = &i2c0;
15		i2c2 = &i2c2;
16		i2c3 = &i2c3;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		serial0 = &uart0;
20	};
21
22	chosen {
23		stdout-path = "serial0:921600n8";
24	};
25
26	firmware {
27		optee {
28			compatible = "linaro,optee-tz";
29			method = "smc";
30		};
31	};
32
33	reserved-memory {
34		#address-cells = <2>;
35		#size-cells = <2>;
36		ranges;
37
38		/*
39		 * 12 MiB reserved for OP-TEE (BL32)
40		 * +-----------------------+ 0x43e0_0000
41		 * |      SHMEM 2MiB       |
42		 * +-----------------------+ 0x43c0_0000
43		 * |        | TA_RAM  8MiB |
44		 * + TZDRAM +--------------+ 0x4340_0000
45		 * |        | TEE_RAM 2MiB |
46		 * +-----------------------+ 0x4320_0000
47		 */
48		optee_reserved: optee@43200000 {
49			no-map;
50			reg = <0 0x43200000 0 0x00c00000>;
51		};
52
53		scp_mem: memory@50000000 {
54			compatible = "shared-dma-pool";
55			reg = <0 0x50000000 0 0x2900000>;
56			no-map;
57		};
58
59		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
60		bl31_secmon_reserved: memory@54600000 {
61			no-map;
62			reg = <0 0x54600000 0x0 0x200000>;
63		};
64
65		apu_mem: memory@55000000 {
66			compatible = "shared-dma-pool";
67			reg = <0 0x55000000 0 0x1400000>; /* 20 MB */
68		};
69
70		vpu_mem: memory@57000000 {
71			compatible = "shared-dma-pool";
72			reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
73		};
74
75		adsp_mem: memory@60000000 {
76			compatible = "shared-dma-pool";
77			reg = <0 0x60000000 0 0xf00000>;
78			no-map;
79		};
80
81		afe_dma_mem: memory@60f00000 {
82			compatible = "shared-dma-pool";
83			reg = <0 0x60f00000 0 0x100000>;
84			no-map;
85		};
86
87		adsp_dma_mem: memory@61000000 {
88			compatible = "shared-dma-pool";
89			reg = <0 0x61000000 0 0x100000>;
90			no-map;
91		};
92	};
93
94	reg_sbc_vsys: regulator-vsys {
95		compatible = "regulator-fixed";
96		regulator-name = "vsys";
97		regulator-always-on;
98		regulator-boot-on;
99	};
100
101	reg_fixed_5v: regulator-0 {
102		compatible = "regulator-fixed";
103		regulator-name = "fixed-5v0";
104		regulator-min-microvolt = <5000000>;
105		regulator-max-microvolt = <5000000>;
106		enable-active-high;
107		regulator-always-on;
108		vin-supply = <&reg_sbc_vsys>;
109	};
110
111	reg_fixed_4v2: regulator-1 {
112		compatible = "regulator-fixed";
113		regulator-name = "fixed-4v2";
114		regulator-min-microvolt = <4200000>;
115		regulator-max-microvolt = <4200000>;
116		enable-active-high;
117		regulator-always-on;
118		vin-supply = <&reg_sbc_vsys>;
119	};
120
121	reg_fixed_3v3: regulator-2 {
122		compatible = "regulator-fixed";
123		regulator-name = "fixed-3v3";
124		regulator-min-microvolt = <3300000>;
125		regulator-max-microvolt = <3300000>;
126		enable-active-high;
127		regulator-always-on;
128		vin-supply = <&reg_sbc_vsys>;
129	};
130};
131
132&pio {
133	gpio-line-names =
134	/*  0 -  4   */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4",
135	/*  5 -  9   */ "", "RPI_GPIO6", "", "", "RPI_GPIO9",
136	/* 10 - 14   */ "RPI_GPIO10", "RPI_GPIO11", "", "", "",
137	/* 15 - 19   */ "", "", "", "", "",
138	/* 20 - 24   */ "", "RPI_GPIO21", "", "RPI_GPIO23", "",
139	/* 25 - 29   */ "", "", "", "", "",
140	/* 30 - 34   */ "RPI_GPIO30", "", "", "", "",
141	/* 35 - 39   */ "RPI_GPIO35", "RPI_GPIO36", "", "", "",
142	/* 40 - 44   */ "", "", "", "", "",
143	/* 45 - 49   */ "", "", "", "", "",
144	/* 50 - 54   */ "", "", "", "", "",
145	/* 55 - 59   */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59",
146	/* 60 - 64   */ "RPI_GPIO60", "", "", "", "",
147	/* 65 - 69   */ "", "", "", "", "RPI_GPIO69",
148	/* 70 - 74   */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74",
149	/* 75 - 79   */ "", "", "", "", "RPI_GPIO79",
150	/* 80 - 84   */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "",
151	/* 85 - 89   */ "", "", "", "", "",
152	/* 90 - 94   */ "", "", "", "", "",
153	/* 95 - 99   */ "", "", "", "", "",
154	/*100 - 104  */ "", "", "", "", "",
155	/*105 - 109  */ "", "", "", "", "",
156	/*110 - 114  */ "", "", "", "", "",
157	/*115 - 119  */ "", "", "", "", "",
158	/*120 - 124  */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124";
159
160	i2c0_pins: i2c0-pins {
161		pins {
162			pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
163				 <PINMUX_GPIO55__FUNC_B1_SCL0>;
164			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
165			drive-strength-microamp = <1000>;
166		};
167	};
168
169	i2c2_pins: i2c2-pins {
170		pins {
171			pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
172				 <PINMUX_GPIO59__FUNC_B1_SCL2>;
173			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
174			drive-strength-microamp = <1000>;
175		};
176	};
177
178	i2c3_pins: i2c3-pins {
179		pins {
180			pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
181				 <PINMUX_GPIO61__FUNC_B1_SCL3>;
182			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
183			drive-strength-microamp = <1000>;
184		};
185	};
186
187	i2c5_pins: i2c5-pins {
188		pins {
189			pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
190				 <PINMUX_GPIO65__FUNC_B1_SCL5>;
191			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
192			drive-strength-microamp = <1000>;
193		};
194	};
195
196	i2c6_pins: i2c6-pins {
197		pins {
198			pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
199				 <PINMUX_GPIO67__FUNC_B1_SCL6>;
200			bias-pull-up = <MTK_PULL_SET_RSEL_011>;
201			drive-strength-microamp = <1000>;
202		};
203	};
204
205	uart0_pins: uart0-pins {
206		pins {
207			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
208				 <PINMUX_GPIO32__FUNC_I1_URXD0>;
209			bias-pull-up;
210		};
211	};
212
213	uart1_pins: uart1-pins {
214		pins {
215			pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>,
216				 <PINMUX_GPIO87__FUNC_I1_URXD1>;
217			bias-pull-up;
218		};
219	};
220
221	uart2_pins: uart2-pins {
222		pins {
223			pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>,
224				 <PINMUX_GPIO36__FUNC_I1_URXD2>;
225			bias-pull-up;
226		};
227	};
228
229	pcie_pins_default: pcie-default {
230		mux {
231			pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
232				 <PINMUX_GPIO48__FUNC_O_PERSTN>,
233				 <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
234			bias-pull-up;
235		};
236	};
237
238	eth_default_pins: eth-default-pins {
239		pins-cc {
240			pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>,
241				 <PINMUX_GPIO140__FUNC_I0_GBE_RXC>,
242				 <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>,
243				 <PINMUX_GPIO142__FUNC_O_GBE_TXEN>;
244			drive-strength = <8>;
245		};
246
247		pins-mdio {
248			pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>,
249				 <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>;
250			drive-strength = <8>;
251			input-enable;
252		};
253
254		pins-power {
255			pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>,
256				 <PINMUX_GPIO146__FUNC_B_GPIO146>;
257			output-high;
258		};
259
260		pins-rxd {
261			pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>,
262				 <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>,
263				 <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>,
264				 <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>;
265			drive-strength = <8>;
266		};
267
268		pins-txd {
269			pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>,
270				 <PINMUX_GPIO132__FUNC_O_GBE_TXD2>,
271				 <PINMUX_GPIO133__FUNC_O_GBE_TXD1>,
272				 <PINMUX_GPIO134__FUNC_O_GBE_TXD0>;
273			drive-strength = <8>;
274		};
275	};
276
277	eth_sleep_pins: eth-sleep-pins {
278		pins-cc {
279			pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>,
280				 <PINMUX_GPIO140__FUNC_B_GPIO140>,
281				 <PINMUX_GPIO141__FUNC_B_GPIO141>,
282				 <PINMUX_GPIO142__FUNC_B_GPIO142>;
283		};
284
285		pins-mdio {
286			pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>,
287				 <PINMUX_GPIO144__FUNC_B_GPIO144>;
288			input-disable;
289			bias-disable;
290		};
291
292		pins-rxd {
293			pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>,
294				 <PINMUX_GPIO136__FUNC_B_GPIO136>,
295				 <PINMUX_GPIO137__FUNC_B_GPIO137>,
296				 <PINMUX_GPIO138__FUNC_B_GPIO138>;
297		};
298
299		pins-txd {
300			pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>,
301				 <PINMUX_GPIO132__FUNC_B_GPIO132>,
302				 <PINMUX_GPIO133__FUNC_B_GPIO133>,
303				 <PINMUX_GPIO134__FUNC_B_GPIO134>;
304		};
305	};
306
307	spi2_pins: spi2-pins {
308		pins-spi {
309			pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
310				<PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
311				<PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
312				<PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
313			bias-disable;
314		};
315	};
316
317	audio_default_pins: audio-default-pins {
318		pins-cmd-dat {
319			pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>,
320				 <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>,
321				 <PINMUX_GPIO123__FUNC_O_PCM_DO>,
322				 <PINMUX_GPIO124__FUNC_I0_PCM_DI>;
323		};
324	};
325
326	usb_default_pins: usb-default-pins {
327		pins-valid {
328			pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>;
329			input-enable;
330		};
331	};
332};
333
334&eth {
335	phy-mode = "rgmii-id";
336	phy-handle = <&ethernet_phy0>;
337	pinctrl-names = "default", "sleep";
338	pinctrl-0 = <&eth_default_pins>;
339	pinctrl-1 = <&eth_sleep_pins>;
340	mediatek,mac-wol;
341	mediatek,tx-delay-ps = <30>;
342	snps,reset-active-low;
343	snps,reset-delays-us = <0 11000 200000>;
344	snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>;
345	status = "okay";
346};
347
348&eth_mdio {
349	ethernet_phy0: ethernet-phy@3 {
350		compatible = "ethernet-phy-ieee802.3-c22";
351		reg = <3>;
352		interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>;
353		eee-broken-1000t;
354	};
355};
356
357&i2c0 {
358	pinctrl-names = "default";
359	pinctrl-0 = <&i2c0_pins>;
360	clock-frequency = <400000>;
361	status = "okay";
362};
363
364&i2c2 {
365	pinctrl-names = "default";
366	pinctrl-0 = <&i2c2_pins>;
367	clock-frequency = <400000>;
368	status = "okay";
369};
370
371&i2c3 {
372	pinctrl-names = "default";
373	pinctrl-0 = <&i2c3_pins>;
374	clock-frequency = <400000>;
375	status = "okay";
376};
377
378&i2c5 {
379	pinctrl-names = "default";
380	pinctrl-0 = <&i2c5_pins>;
381	clock-frequency = <400000>;
382	status = "okay";
383};
384
385&i2c6 {
386	pinctrl-names = "default";
387	pinctrl-0 = <&i2c6_pins>;
388	clock-frequency = <400000>;
389	status = "okay";
390};
391
392&uart0 {
393	pinctrl-names = "default";
394	pinctrl-0 = <&uart0_pins>;
395	status = "okay";
396};
397
398&uart1 {
399	pinctrl-names = "default";
400	pinctrl-0 = <&uart1_pins>;
401	status = "okay";
402};
403
404&uart2 {
405	pinctrl-names = "default";
406	pinctrl-0 = <&uart2_pins>;
407	status = "okay";
408};
409
410&pcie {
411	pinctrl-names = "default";
412	pinctrl-0 = <&pcie_pins_default>;
413	status = "okay";
414};
415
416&pciephy {
417	status = "okay";
418};
419
420&spi2 {
421	pinctrl-names = "default";
422	pinctrl-0 = <&spi2_pins>;
423	mediatek,pad-select = <0>;
424	#address-cells = <1>;
425	#size-cells = <0>;
426	status = "okay";
427};
428
429&u3phy0 {
430	status = "okay";
431};
432
433&u3phy1 {
434	status = "okay";
435};
436
437&u3phy2 {
438	status = "okay";
439};
440
441&xhci1 {
442	#address-cells = <1>;
443	#size-cells = <0>;
444	vusb33-supply = <&mt6359_vusb_ldo_reg>;
445	status = "okay";
446
447	hub_2_0: hub@1 {
448		compatible = "usb451,8027";
449		reg = <1>;
450		peer-hub = <&hub_3_0>;
451		reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
452		vdd-supply = <&reg_fixed_3v3>;
453	};
454
455	hub_3_0: hub@2 {
456		compatible = "usb451,8025";
457		reg = <2>;
458		peer-hub = <&hub_2_0>;
459		reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
460		vdd-supply = <&reg_fixed_3v3>;
461	};
462};
463
464&xhci2 {
465	#address-cells = <1>;
466	#size-cells = <0>;
467	vusb33-supply = <&mt6359_vusb_ldo_reg>;
468	status = "okay";
469
470	hub@1 {
471		compatible = "microchip,usb2513bi";
472		reg = <1>;
473		vdd-supply = <&reg_fixed_3v3>;
474	};
475};
476
477&ssusb0 {
478	dr_mode = "peripheral";
479	pinctrl-names = "default";
480	pinctrl-0 = <&usb_default_pins>;
481	vusb33-supply = <&mt6359_vusb_ldo_reg>;
482	status = "okay";
483};
484
485&ssusb1 {
486	dr_mode = "host";
487	maximum-speed = "super-speed";
488	vusb33-supply = <&mt6359_vusb_ldo_reg>;
489	status = "okay";
490};
491
492&ssusb2 {
493	dr_mode = "host";
494	maximum-speed = "high-speed";
495	vusb33-supply = <&mt6359_vusb_ldo_reg>;
496	status = "okay";
497};
498
499&scp_cluster {
500	status = "okay";
501};
502
503&scp_c0 {
504	memory-region = <&scp_mem>;
505	status = "okay";
506};
507
508&gpu {
509	mali-supply = <&mt6359_vproc2_buck_reg>;
510	status = "okay";
511};
512
513&adsp {
514	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
515	status = "okay";
516};
517
518&afe {
519	memory-region = <&afe_dma_mem>;
520	status = "okay";
521};
522
523&sound {
524	compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
525	model = "mt8390-evk";
526	pinctrl-names = "default";
527	pinctrl-0 = <&audio_default_pins>;
528	audio-routing =
529		"Headphone", "Headphone L",
530		"Headphone", "Headphone R",
531		"AP DMIC", "AUDGLB",
532		"AP DMIC", "MIC_BIAS_0",
533		"AP DMIC", "MIC_BIAS_2",
534		"DMIC_INPUT", "AP DMIC";
535
536	mediatek,adsp = <&adsp>;
537	status = "okay";
538};
539