1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Christoph Stoidner <c.stoidner@phytec.de> 5 * 6 * Product homepage: 7 * phyBOARD-Segin carrier board is reused for the i.MX91 design. 8 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ 9 */ 10/dts-v1/; 11 12#include "imx91-phycore-som.dtsi" 13 14/{ 15 model = "PHYTEC phyBOARD-Segin-i.MX91"; 16 compatible = "phytec,imx91-phyboard-segin", "phytec,imx91-phycore-som", 17 "fsl,imx91"; 18 19 aliases { 20 ethernet1 = &eqos; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 i2c0 = &lpi2c1; 26 i2c1 = &lpi2c2; 27 mmc0 = &usdhc1; 28 mmc1 = &usdhc2; 29 rtc0 = &i2c_rtc; 30 rtc1 = &bbnsm_rtc; 31 serial0 = &lpuart1; 32 }; 33 34 chosen { 35 stdout-path = &lpuart1; 36 }; 37 38 flexcan1_tc: can-phy0 { 39 /* TI SN65HVD234D CAN-CC 1MBit/s */ 40 compatible = "ti,tcan1043"; 41 #phy-cells = <0>; 42 max-bitrate = <1000000>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_flexcan1_tc>; 45 enable-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 46 }; 47 48 reg_sound_1v8: regulator-sound-1v8 { 49 compatible = "regulator-fixed"; 50 regulator-max-microvolt = <1800000>; 51 regulator-min-microvolt = <1800000>; 52 regulator-name = "VCC1V8_AUDIO"; 53 }; 54 55 reg_sound_3v3: regulator-sound-3v3 { 56 compatible = "regulator-fixed"; 57 regulator-max-microvolt = <3300000>; 58 regulator-min-microvolt = <3300000>; 59 regulator-name = "VCC3V3_ANALOG"; 60 }; 61 62 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 63 compatible = "regulator-fixed"; 64 regulator-name = "USB_OTG1_VBUS"; 65 regulator-max-microvolt = <5000000>; 66 regulator-min-microvolt = <5000000>; 67 regulator-always-on; 68 }; 69 70 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 71 compatible = "regulator-fixed"; 72 regulator-name = "USB_OTG2_VBUS"; 73 regulator-max-microvolt = <5000000>; 74 regulator-min-microvolt = <5000000>; 75 regulator-always-on; 76 }; 77 78 reg_usdhc2_vmmc: regulator-usdhc2 { 79 compatible = "regulator-fixed"; 80 enable-active-high; 81 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 84 regulator-max-microvolt = <3300000>; 85 regulator-min-microvolt = <3300000>; 86 regulator-name = "VCC_SD"; 87 }; 88 89 sound: sound { 90 compatible = "simple-audio-card"; 91 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007"; 92 simple-audio-card,format = "i2s"; 93 simple-audio-card,bitclock-master = <&dailink_master>; 94 simple-audio-card,frame-master = <&dailink_master>; 95 simple-audio-card,widgets = 96 "Line", "Line In", 97 "Line", "Line Out", 98 "Speaker", "Speaker"; 99 simple-audio-card,routing = 100 "Line Out", "LLOUT", 101 "Line Out", "RLOUT", 102 "Speaker", "SPOP", 103 "Speaker", "SPOM", 104 "LINE1L", "Line In", 105 "LINE1R", "Line In"; 106 107 simple-audio-card,cpu { 108 sound-dai = <&sai1>; 109 }; 110 111 dailink_master: simple-audio-card,codec { 112 sound-dai = <&audio_codec>; 113 clocks = <&clk IMX93_CLK_SAI1>; 114 }; 115 }; 116}; 117 118/* Ethernet */ 119&eqos { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_eqos>; 122 phy-mode = "rmii"; 123 phy-handle = <ðphy2>; 124 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 125 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 126 assigned-clock-rates = <100000000>, <50000000>; 127 status = "okay"; 128}; 129 130&mdio { 131 ethphy2: ethernet-phy@2 { 132 compatible = "ethernet-phy-id0022.1561"; 133 reg = <2>; 134 clocks = <&clk IMX91_CLK_ENET2_REGULAR>; 135 clock-names = "rmii-ref"; 136 micrel,led-mode = <1>; 137 }; 138}; 139 140/* CAN */ 141&flexcan1 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_flexcan1>; 144 phys = <&flexcan1_tc>; 145 status = "okay"; 146}; 147 148/* I2C2 */ 149&lpi2c2 { 150 clock-frequency = <400000>; 151 pinctrl-names = "default", "gpio"; 152 pinctrl-0 = <&pinctrl_lpi2c2>; 153 pinctrl-1 = <&pinctrl_lpi2c2_gpio>; 154 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 155 sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 156 status = "okay"; 157 158 /* Codec */ 159 audio_codec: audio-codec@18 { 160 compatible = "ti,tlv320aic3007"; 161 reg = <0x18>; 162 #sound-dai-cells = <0>; 163 AVDD-supply = <®_sound_3v3>; 164 IOVDD-supply = <®_sound_3v3>; 165 DRVDD-supply = <®_sound_3v3>; 166 DVDD-supply = <®_sound_1v8>; 167 }; 168 169 /* RTC */ 170 i2c_rtc: rtc@68 { 171 compatible = "microcrystal,rv4162"; 172 reg = <0x68>; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_rtc>; 175 interrupt-parent = <&gpio4>; 176 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 177 }; 178}; 179 180/* Console */ 181&lpuart1 { 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_uart1>; 184 status = "okay"; 185}; 186 187/* Audio */ 188&sai1 { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_sai1>; 191 assigned-clocks = <&clk IMX93_CLK_SAI1>; 192 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 193 assigned-clock-rates = <19200000>; 194 fsl,sai-mclk-direction-output; 195 status = "okay"; 196}; 197 198/* USB */ 199&usbphynop1 { 200 vbus-supply = <®_usb_otg1_vbus>; 201}; 202 203&usbphynop2 { 204 vbus-supply = <®_usb_otg2_vbus>; 205}; 206 207&usbotg1 { 208 disable-over-current; 209 dr_mode = "otg"; 210 status = "okay"; 211}; 212 213&usbotg2 { 214 disable-over-current; 215 dr_mode = "host"; 216 status = "okay"; 217}; 218 219/* SD-Card */ 220&usdhc2 { 221 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 222 pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; 223 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 224 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 225 bus-width = <4>; 226 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 227 disable-wp; 228 no-mmc; 229 no-sdio; 230 vmmc-supply = <®_usdhc2_vmmc>; 231 status = "okay"; 232}; 233 234&iomuxc { 235 pinctrl_eqos: eqosgrp { 236 fsl,pins = < 237 MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x4000050e 238 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 239 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 240 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x50e 241 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x50e 242 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 243 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x50e 244 MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x57e 245 >; 246 }; 247 248 pinctrl_flexcan1: flexcan1grp { 249 fsl,pins = < 250 MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 251 MX91_PAD_PDM_CLK__CAN1_TX 0x139e 252 >; 253 }; 254 255 pinctrl_flexcan1_tc: flexcan1tcgrp { 256 fsl,pins = < 257 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x31e 258 >; 259 }; 260 261 pinctrl_lpi2c2: lpi2c2grp { 262 fsl,pins = < 263 MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 264 MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 265 >; 266 }; 267 268 pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { 269 fsl,pins = < 270 MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e 271 MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e 272 >; 273 }; 274 275 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 276 fsl,pins = < 277 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e 278 >; 279 }; 280 281 pinctrl_rtc: rtcgrp { 282 fsl,pins = < 283 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x31e 284 >; 285 }; 286 287 pinctrl_sai1: sai1grp { 288 fsl,pins = < 289 MX91_PAD_UART2_RXD__SAI1_MCLK 0x1202 290 MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x1202 291 MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x1202 292 MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x1402 293 MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x1402 294 >; 295 }; 296 297 pinctrl_uart1: uart1grp { 298 fsl,pins = < 299 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 300 MX91_PAD_UART1_TXD__LPUART1_TX 0x30e 301 >; 302 }; 303 304 pinctrl_usdhc2_cd: usdhc2cdgrp { 305 fsl,pins = < 306 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 307 >; 308 }; 309 310 pinctrl_usdhc2_default: usdhc2grp { 311 fsl,pins = < 312 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 313 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 314 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386 315 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 316 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 317 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 318 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 319 >; 320 }; 321 322 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 323 fsl,pins = < 324 MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e 325 MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e 326 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 327 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 328 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 329 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 330 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 331 >; 332 }; 333 334 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 335 fsl,pins = < 336 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 337 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 338 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e 339 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e 340 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 341 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 342 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 343 >; 344 }; 345}; 346