1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6#include "imx8mn-overdrive.dtsi" 7 8/ { 9 aliases { 10 rtc0 = &rtc; 11 rtc1 = &snvs_rtc; 12 spi0 = &flexspi; 13 }; 14 15 usdhc1_pwrseq: usdhc1_pwrseq { 16 compatible = "mmc-pwrseq-simple"; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&pinctrl_usdhc1_gpio>; 19 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 20 clocks = <&osc_32k>; 21 clock-names = "ext_clock"; 22 post-power-on-delay-ms = <80>; 23 }; 24 25 memory@40000000 { 26 device_type = "memory"; 27 reg = <0x0 0x40000000 0 0x80000000>; 28 }; 29}; 30 31&A53_0 { 32 cpu-supply = <&buck2_reg>; 33}; 34 35&A53_1 { 36 cpu-supply = <&buck2_reg>; 37}; 38 39&A53_2 { 40 cpu-supply = <&buck2_reg>; 41}; 42 43&A53_3 { 44 cpu-supply = <&buck2_reg>; 45}; 46 47/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ 48&a53_opp_table { 49 opp-1200000000 { 50 opp-microvolt = <950000>; 51 }; 52}; 53 54&ddrc { 55 operating-points-v2 = <&ddrc_opp_table>; 56 57 ddrc_opp_table: opp-table { 58 compatible = "operating-points-v2"; 59 60 opp-25000000 { 61 opp-hz = /bits/ 64 <25000000>; 62 }; 63 64 opp-100000000 { 65 opp-hz = /bits/ 64 <100000000>; 66 }; 67 68 opp-800000000 { 69 opp-hz = /bits/ 64 <800000000>; 70 }; 71 }; 72}; 73 74&fec1 { 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 phy-mode = "rgmii-id"; 78 phy-handle = <ðphy0>; 79 phy-supply = <&buck6_reg>; 80 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 81 fsl,magic-packet; 82 status = "okay"; 83 84 mdio { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 ethphy0: ethernet-phy@0 { 89 compatible = "ethernet-phy-ieee802.3-c22"; 90 reg = <0>; 91 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 92 interrupt-parent = <&gpio1>; 93 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 94 }; 95 }; 96}; 97 98&flexspi { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_flexspi>; 101 status = "okay"; 102 103 flash@0 { 104 reg = <0>; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 compatible = "jedec,spi-nor"; 108 spi-max-frequency = <80000000>; 109 spi-tx-bus-width = <1>; 110 spi-rx-bus-width = <4>; 111 }; 112}; 113 114&i2c1 { 115 clock-frequency = <400000>; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_i2c1>; 118 status = "okay"; 119 120 pmic@4b { 121 compatible = "rohm,bd71847"; 122 reg = <0x4b>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_pmic>; 125 interrupt-parent = <&gpio1>; 126 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 127 rohm,reset-snvs-powered; 128 #clock-cells = <0>; 129 clocks = <&osc_32k>; 130 clock-output-names = "clk-32k-out"; 131 132 regulators { 133 buck1_reg: BUCK1 { 134 regulator-name = "buck1"; 135 regulator-min-microvolt = <700000>; 136 regulator-max-microvolt = <1300000>; 137 regulator-boot-on; 138 regulator-always-on; 139 regulator-ramp-delay = <1250>; 140 }; 141 142 buck2_reg: BUCK2 { 143 regulator-name = "buck2"; 144 regulator-min-microvolt = <700000>; 145 regulator-max-microvolt = <1300000>; 146 regulator-boot-on; 147 regulator-always-on; 148 regulator-ramp-delay = <1250>; 149 rohm,dvs-run-voltage = <1000000>; 150 rohm,dvs-idle-voltage = <900000>; 151 }; 152 153 buck3_reg: BUCK3 { 154 // BUCK5 in datasheet 155 regulator-name = "buck3"; 156 regulator-min-microvolt = <700000>; 157 regulator-max-microvolt = <1350000>; 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 162 buck4_reg: BUCK4 { 163 // BUCK6 in datasheet 164 regulator-name = "buck4"; 165 regulator-min-microvolt = <3000000>; 166 regulator-max-microvolt = <3300000>; 167 regulator-boot-on; 168 regulator-always-on; 169 }; 170 171 buck5_reg: BUCK5 { 172 // BUCK7 in datasheet 173 regulator-name = "buck5"; 174 regulator-min-microvolt = <1605000>; 175 regulator-max-microvolt = <1995000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 buck6_reg: BUCK6 { 181 // BUCK8 in datasheet 182 regulator-name = "buck6"; 183 regulator-min-microvolt = <800000>; 184 regulator-max-microvolt = <1400000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 ldo1_reg: LDO1 { 190 regulator-name = "ldo1"; 191 regulator-min-microvolt = <1600000>; 192 regulator-max-microvolt = <3300000>; 193 regulator-boot-on; 194 regulator-always-on; 195 }; 196 197 ldo2_reg: LDO2 { 198 regulator-name = "ldo2"; 199 regulator-min-microvolt = <800000>; 200 regulator-max-microvolt = <900000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 205 ldo3_reg: LDO3 { 206 regulator-name = "ldo3"; 207 regulator-min-microvolt = <1800000>; 208 regulator-max-microvolt = <3300000>; 209 regulator-boot-on; 210 regulator-always-on; 211 }; 212 213 ldo4_reg: LDO4 { 214 regulator-name = "ldo4"; 215 regulator-min-microvolt = <900000>; 216 regulator-max-microvolt = <1800000>; 217 regulator-boot-on; 218 regulator-always-on; 219 }; 220 221 ldo6_reg: LDO6 { 222 regulator-name = "ldo6"; 223 regulator-min-microvolt = <900000>; 224 regulator-max-microvolt = <1800000>; 225 regulator-boot-on; 226 regulator-always-on; 227 }; 228 }; 229 }; 230}; 231 232&i2c3 { 233 clock-frequency = <400000>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_i2c3>; 236 status = "okay"; 237 238 eeprom@50 { 239 compatible = "microchip,24c64", "atmel,24c64"; 240 pagesize = <32>; 241 read-only; /* Manufacturing EEPROM programmed at factory */ 242 reg = <0x50>; 243 }; 244 245 rtc: rtc@51 { 246 compatible = "nxp,pcf85263"; 247 reg = <0x51>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_rtc>; 250 interrupt-parent = <&gpio1>; 251 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 252 quartz-load-femtofarads = <12500>; 253 wakeup-source; 254 }; 255}; 256 257&uart1 { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_uart1>; 260 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 261 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 262 uart-has-rtscts; 263 status = "okay"; 264 265 bluetooth { 266 compatible = "brcm,bcm43438-bt"; 267 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 268 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 269 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 270 clocks = <&osc_32k>; 271 max-speed = <4000000>; 272 clock-names = "extclk"; 273 }; 274}; 275 276&usdhc1 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 280 pinctrl-0 = <&pinctrl_usdhc1>; 281 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 282 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 283 vmmc-supply = <&buck4_reg>; 284 vqmmc-supply = <&buck5_reg>; 285 bus-width = <4>; 286 non-removable; 287 cap-power-off-card; 288 keep-power-in-suspend; 289 mmc-pwrseq = <&usdhc1_pwrseq>; 290 status = "okay"; 291 292 brcmf: wifi@1 { 293 reg = <1>; 294 compatible = "brcm,bcm4329-fmac"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_wlan>; 297 interrupt-parent = <&gpio2>; 298 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-names = "host-wake"; 300 }; 301}; 302 303&usdhc3 { 304 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 305 pinctrl-0 = <&pinctrl_usdhc3>; 306 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 307 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 308 assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; 309 assigned-clock-rates = <400000000>; 310 bus-width = <8>; 311 non-removable; 312 status = "okay"; 313}; 314 315&wdog1 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_wdog>; 318 fsl,ext-reset-output; 319 status = "okay"; 320}; 321 322&iomuxc { 323 pinctrl_fec1: fec1grp { 324 fsl,pins = < 325 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 326 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 327 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 328 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 329 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 330 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 331 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 332 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 333 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 334 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 335 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 336 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 337 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 338 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 339 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 340 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 341 >; 342 }; 343 344 pinctrl_i2c1: i2c1grp { 345 fsl,pins = < 346 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 347 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 348 >; 349 }; 350 351 pinctrl_i2c3: i2c3grp { 352 fsl,pins = < 353 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 354 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 355 >; 356 }; 357 358 pinctrl_flexspi: flexspigrp { 359 fsl,pins = < 360 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 361 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 362 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 363 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 364 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 365 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 366 >; 367 }; 368 369 pinctrl_pmic: pmicirqgrp { 370 fsl,pins = < 371 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 372 >; 373 }; 374 375 pinctrl_rtc: rtcgrp { 376 fsl,pins = < 377 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 378 >; 379 }; 380 381 pinctrl_uart1: uart1grp { 382 fsl,pins = < 383 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 384 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 385 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 386 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 387 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 388 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 389 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 390 MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 391 >; 392 }; 393 394 pinctrl_usdhc1_gpio: usdhc1gpiogrp { 395 fsl,pins = < 396 MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 397 >; 398 }; 399 400 pinctrl_usdhc1: usdhc1grp { 401 fsl,pins = < 402 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 403 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 404 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 405 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 406 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 407 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 408 >; 409 }; 410 411 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 412 fsl,pins = < 413 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 414 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 415 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 416 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 417 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 418 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 419 >; 420 }; 421 422 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 423 fsl,pins = < 424 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 425 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 426 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 427 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 428 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 429 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 430 >; 431 }; 432 433 pinctrl_usdhc3: usdhc3grp { 434 fsl,pins = < 435 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 436 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 437 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 438 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 439 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 440 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 441 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 442 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 443 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 444 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 445 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 446 >; 447 }; 448 449 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 450 fsl,pins = < 451 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 452 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 453 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 454 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 455 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 456 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 457 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 458 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 459 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 460 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 461 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 462 >; 463 }; 464 465 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 466 fsl,pins = < 467 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 468 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 469 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 470 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 471 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 472 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 473 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 474 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 475 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 476 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 477 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 478 >; 479 }; 480 481 pinctrl_wdog: wdoggrp { 482 fsl,pins = < 483 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 484 >; 485 }; 486 487 pinctrl_wlan: wlangrp { 488 fsl,pins = < 489 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 490 >; 491 }; 492}; 493