10dcd27bdSDong Aisheng// SPDX-License-Identifier: GPL-2.0+ 20dcd27bdSDong Aisheng/* 30dcd27bdSDong Aisheng * Copyright 2018-2019 NXP 40dcd27bdSDong Aisheng * Dong Aisheng <aisheng.dong@nxp.com> 50dcd27bdSDong Aisheng */ 60dcd27bdSDong Aisheng 79de8a226SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 89de8a226SDong Aisheng#include <dt-bindings/firmware/imx/rsrc.h> 99de8a226SDong Aisheng 100dcd27bdSDong Aishengconn_subsys: bus@5b000000 { 110dcd27bdSDong Aisheng compatible = "simple-bus"; 120dcd27bdSDong Aisheng #address-cells = <1>; 130dcd27bdSDong Aisheng #size-cells = <1>; 140dcd27bdSDong Aisheng ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 150dcd27bdSDong Aisheng 169de8a226SDong Aisheng conn_axi_clk: clock-conn-axi { 179de8a226SDong Aisheng compatible = "fixed-clock"; 189de8a226SDong Aisheng #clock-cells = <0>; 199de8a226SDong Aisheng clock-frequency = <333333333>; 209de8a226SDong Aisheng clock-output-names = "conn_axi_clk"; 219de8a226SDong Aisheng }; 229de8a226SDong Aisheng 239de8a226SDong Aisheng conn_ahb_clk: clock-conn-ahb { 249de8a226SDong Aisheng compatible = "fixed-clock"; 259de8a226SDong Aisheng #clock-cells = <0>; 269de8a226SDong Aisheng clock-frequency = <166666666>; 279de8a226SDong Aisheng clock-output-names = "conn_ahb_clk"; 289de8a226SDong Aisheng }; 299de8a226SDong Aisheng 309de8a226SDong Aisheng conn_ipg_clk: clock-conn-ipg { 319de8a226SDong Aisheng compatible = "fixed-clock"; 329de8a226SDong Aisheng #clock-cells = <0>; 339de8a226SDong Aisheng clock-frequency = <83333333>; 349de8a226SDong Aisheng clock-output-names = "conn_ipg_clk"; 350dcd27bdSDong Aisheng }; 360dcd27bdSDong Aisheng 378065fc93SFrank Li usbotg1: usb@5b0d0000 { 38*276dd9a6SPeng Fan compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; 398065fc93SFrank Li reg = <0x5b0d0000 0x200>; 408065fc93SFrank Li interrupt-parent = <&gic>; 418065fc93SFrank Li interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 428065fc93SFrank Li fsl,usbphy = <&usbphy1>; 438065fc93SFrank Li fsl,usbmisc = <&usbmisc1 0>; 448065fc93SFrank Li clocks = <&usb2_lpcg 0>; 458065fc93SFrank Li ahb-burst-config = <0x0>; 468065fc93SFrank Li tx-burst-size-dword = <0x10>; 478065fc93SFrank Li rx-burst-size-dword = <0x10>; 488065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0>; 498065fc93SFrank Li status = "disabled"; 508065fc93SFrank Li }; 518065fc93SFrank Li 528065fc93SFrank Li usbmisc1: usbmisc@5b0d0200 { 538065fc93SFrank Li #index-cells = <1>; 54*276dd9a6SPeng Fan compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 558065fc93SFrank Li reg = <0x5b0d0200 0x200>; 568065fc93SFrank Li }; 578065fc93SFrank Li 588065fc93SFrank Li usbphy1: usbphy@5b100000 { 598065fc93SFrank Li compatible = "fsl,imx7ulp-usbphy"; 608065fc93SFrank Li reg = <0x5b100000 0x1000>; 618065fc93SFrank Li clocks = <&usb2_lpcg 1>; 628065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0_PHY>; 638065fc93SFrank Li status = "disabled"; 648065fc93SFrank Li }; 658065fc93SFrank Li 660dcd27bdSDong Aisheng usdhc1: mmc@5b010000 { 670dcd27bdSDong Aisheng interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 680dcd27bdSDong Aisheng reg = <0x5b010000 0x10000>; 6916c4ea75SDong Aisheng clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 7006acb824SPeng Fan <&sdhc0_lpcg IMX_LPCG_CLK_0>, 7106acb824SPeng Fan <&sdhc0_lpcg IMX_LPCG_CLK_5>; 7206acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 730dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 740dcd27bdSDong Aisheng status = "disabled"; 750dcd27bdSDong Aisheng }; 760dcd27bdSDong Aisheng 770dcd27bdSDong Aisheng usdhc2: mmc@5b020000 { 780dcd27bdSDong Aisheng interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 790dcd27bdSDong Aisheng reg = <0x5b020000 0x10000>; 8016c4ea75SDong Aisheng clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 8106acb824SPeng Fan <&sdhc1_lpcg IMX_LPCG_CLK_0>, 8206acb824SPeng Fan <&sdhc1_lpcg IMX_LPCG_CLK_5>; 8306acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 840dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 850dcd27bdSDong Aisheng fsl,tuning-start-tap = <20>; 860dcd27bdSDong Aisheng fsl,tuning-step = <2>; 870dcd27bdSDong Aisheng status = "disabled"; 880dcd27bdSDong Aisheng }; 890dcd27bdSDong Aisheng 900dcd27bdSDong Aisheng usdhc3: mmc@5b030000 { 910dcd27bdSDong Aisheng interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 920dcd27bdSDong Aisheng reg = <0x5b030000 0x10000>; 9316c4ea75SDong Aisheng clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 9406acb824SPeng Fan <&sdhc2_lpcg IMX_LPCG_CLK_0>, 9506acb824SPeng Fan <&sdhc2_lpcg IMX_LPCG_CLK_5>; 9606acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 970dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 980dcd27bdSDong Aisheng status = "disabled"; 990dcd27bdSDong Aisheng }; 1000dcd27bdSDong Aisheng 1010dcd27bdSDong Aisheng fec1: ethernet@5b040000 { 1020dcd27bdSDong Aisheng reg = <0x5b040000 0x10000>; 1030dcd27bdSDong Aisheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1040dcd27bdSDong Aisheng <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1050dcd27bdSDong Aisheng <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1060dcd27bdSDong Aisheng <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 10716c4ea75SDong Aisheng clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 10816c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_2>, 109dfda1fd1SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_3>, 11016c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_0>; 1110dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 112dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 113dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 114dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 1150dcd27bdSDong Aisheng fsl,num-tx-queues = <3>; 1160dcd27bdSDong Aisheng fsl,num-rx-queues = <3>; 1170dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 1180dcd27bdSDong Aisheng status = "disabled"; 1190dcd27bdSDong Aisheng }; 1200dcd27bdSDong Aisheng 1210dcd27bdSDong Aisheng fec2: ethernet@5b050000 { 1220dcd27bdSDong Aisheng reg = <0x5b050000 0x10000>; 1230dcd27bdSDong Aisheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1240dcd27bdSDong Aisheng <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1250dcd27bdSDong Aisheng <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1260dcd27bdSDong Aisheng <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 12716c4ea75SDong Aisheng clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 12816c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_2>, 129dfda1fd1SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_3>, 13016c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_0>; 1310dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 132dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 133dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 134dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 1350dcd27bdSDong Aisheng fsl,num-tx-queues = <3>; 1360dcd27bdSDong Aisheng fsl,num-rx-queues = <3>; 1370dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 1380dcd27bdSDong Aisheng status = "disabled"; 1390dcd27bdSDong Aisheng }; 1409de8a226SDong Aisheng 1419de8a226SDong Aisheng /* LPCG clocks */ 1429de8a226SDong Aisheng sdhc0_lpcg: clock-controller@5b200000 { 14316c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1449de8a226SDong Aisheng reg = <0x5b200000 0x10000>; 1459de8a226SDong Aisheng #clock-cells = <1>; 14626de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 1479de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1489de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1499de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1509de8a226SDong Aisheng clock-output-names = "sdhc0_lpcg_per_clk", 1519de8a226SDong Aisheng "sdhc0_lpcg_ipg_clk", 1529de8a226SDong Aisheng "sdhc0_lpcg_ahb_clk"; 1539de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 1549de8a226SDong Aisheng }; 1559de8a226SDong Aisheng 1569de8a226SDong Aisheng sdhc1_lpcg: clock-controller@5b210000 { 15716c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1589de8a226SDong Aisheng reg = <0x5b210000 0x10000>; 1599de8a226SDong Aisheng #clock-cells = <1>; 16026de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 1619de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1629de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1639de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1649de8a226SDong Aisheng clock-output-names = "sdhc1_lpcg_per_clk", 1659de8a226SDong Aisheng "sdhc1_lpcg_ipg_clk", 1669de8a226SDong Aisheng "sdhc1_lpcg_ahb_clk"; 1679de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 1689de8a226SDong Aisheng }; 1699de8a226SDong Aisheng 1709de8a226SDong Aisheng sdhc2_lpcg: clock-controller@5b220000 { 17116c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1729de8a226SDong Aisheng reg = <0x5b220000 0x10000>; 1739de8a226SDong Aisheng #clock-cells = <1>; 17426de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 1759de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1769de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1779de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1789de8a226SDong Aisheng clock-output-names = "sdhc2_lpcg_per_clk", 1799de8a226SDong Aisheng "sdhc2_lpcg_ipg_clk", 1809de8a226SDong Aisheng "sdhc2_lpcg_ahb_clk"; 1819de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 1829de8a226SDong Aisheng }; 1839de8a226SDong Aisheng 1849de8a226SDong Aisheng enet0_lpcg: clock-controller@5b230000 { 18516c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1869de8a226SDong Aisheng reg = <0x5b230000 0x10000>; 1879de8a226SDong Aisheng #clock-cells = <1>; 18826de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 18926de33a1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 190dfda1fd1SDong Aisheng <&conn_axi_clk>, 191dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 192dfda1fd1SDong Aisheng <&conn_ipg_clk>, 193dfda1fd1SDong Aisheng <&conn_ipg_clk>; 1949de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 195dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 196dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 197dfda1fd1SDong Aisheng clock-output-names = "enet0_lpcg_timer_clk", 198dfda1fd1SDong Aisheng "enet0_lpcg_txc_sampling_clk", 199dfda1fd1SDong Aisheng "enet0_lpcg_ahb_clk", 200dfda1fd1SDong Aisheng "enet0_lpcg_rgmii_txc_clk", 201dfda1fd1SDong Aisheng "enet0_lpcg_ipg_clk", 202dfda1fd1SDong Aisheng "enet0_lpcg_ipg_s_clk"; 2039de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 2049de8a226SDong Aisheng }; 2059de8a226SDong Aisheng 2069de8a226SDong Aisheng enet1_lpcg: clock-controller@5b240000 { 20716c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 2089de8a226SDong Aisheng reg = <0x5b240000 0x10000>; 2099de8a226SDong Aisheng #clock-cells = <1>; 21026de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 21126de33a1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 212dfda1fd1SDong Aisheng <&conn_axi_clk>, 213dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, 214dfda1fd1SDong Aisheng <&conn_ipg_clk>, 215dfda1fd1SDong Aisheng <&conn_ipg_clk>; 2169de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 217dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 218dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 219dfda1fd1SDong Aisheng clock-output-names = "enet1_lpcg_timer_clk", 220dfda1fd1SDong Aisheng "enet1_lpcg_txc_sampling_clk", 221dfda1fd1SDong Aisheng "enet1_lpcg_ahb_clk", 222dfda1fd1SDong Aisheng "enet1_lpcg_rgmii_txc_clk", 223dfda1fd1SDong Aisheng "enet1_lpcg_ipg_clk", 224dfda1fd1SDong Aisheng "enet1_lpcg_ipg_s_clk"; 2259de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 2269de8a226SDong Aisheng }; 2278065fc93SFrank Li 2288065fc93SFrank Li usb2_lpcg: clock-controller@5b270000 { 2298065fc93SFrank Li compatible = "fsl,imx8qxp-lpcg"; 2308065fc93SFrank Li reg = <0x5b270000 0x10000>; 2318065fc93SFrank Li #clock-cells = <1>; 2328065fc93SFrank Li clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; 2338065fc93SFrank Li clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 2348065fc93SFrank Li clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; 2358065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0_PHY>; 2368065fc93SFrank Li }; 2370dcd27bdSDong Aisheng}; 238