1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/irq.h> 4 5/ { 6 compatible = "bst,c1200"; 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 14 cpu@0 { 15 device_type = "cpu"; 16 compatible = "arm,cortex-a78"; 17 reg = <0x0>; 18 enable-method = "psci"; 19 next-level-cache = <&l2_cache>; 20 }; 21 22 cpu@1 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a78"; 25 reg = <0x100>; 26 enable-method = "psci"; 27 next-level-cache = <&l2_cache>; 28 }; 29 30 cpu@2 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a78"; 33 reg = <0x200>; 34 enable-method = "psci"; 35 next-level-cache = <&l2_cache>; 36 }; 37 38 cpu@3 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a78"; 41 reg = <0x300>; 42 enable-method = "psci"; 43 next-level-cache = <&l2_cache>; 44 }; 45 46 l2_cache: l2-cache { 47 compatible = "cache"; 48 cache-level = <2>; 49 cache-unified; 50 }; 51 }; 52 53 psci { 54 compatible = "arm,psci-1.0"; 55 method = "smc"; 56 }; 57 58 soc { 59 compatible = "simple-bus"; 60 ranges; 61 #address-cells = <2>; 62 #size-cells = <2>; 63 interrupt-parent = <&gic>; 64 65 uart0: serial@20008000 { 66 compatible = "snps,dw-apb-uart"; 67 reg = <0x0 0x20008000 0x0 0x1000>; 68 clock-frequency = <25000000>; 69 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 70 reg-shift = <2>; 71 reg-io-width = <4>; 72 status = "disabled"; 73 }; 74 75 gic: interrupt-controller@32800000 { 76 compatible = "arm,gic-v3"; 77 reg = <0x0 0x32800000 0x0 0x10000>, 78 <0x0 0x32880000 0x0 0x100000>; 79 ranges; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 85 }; 86 }; 87 88 timer { 89 compatible = "arm,armv8-timer"; 90 always-on; 91 interrupt-parent = <&gic>; 92 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 93 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 94 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 95 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 96 }; 97}; 98