1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 * This DTSI is for the B0 and later revision of the SoC 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "brcm,bcm63158", "brcm,bcmbca"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 interrupt-parent = <&gic>; 16 17 cpus { 18 #address-cells = <2>; 19 #size-cells = <0>; 20 21 B53_0: cpu@0 { 22 compatible = "brcm,brahma-b53"; 23 device_type = "cpu"; 24 reg = <0x0 0x0>; 25 next-level-cache = <&L2_0>; 26 enable-method = "psci"; 27 }; 28 29 B53_1: cpu@1 { 30 compatible = "brcm,brahma-b53"; 31 device_type = "cpu"; 32 reg = <0x0 0x1>; 33 next-level-cache = <&L2_0>; 34 enable-method = "psci"; 35 }; 36 37 B53_2: cpu@2 { 38 compatible = "brcm,brahma-b53"; 39 device_type = "cpu"; 40 reg = <0x0 0x2>; 41 next-level-cache = <&L2_0>; 42 enable-method = "psci"; 43 }; 44 45 B53_3: cpu@3 { 46 compatible = "brcm,brahma-b53"; 47 device_type = "cpu"; 48 reg = <0x0 0x3>; 49 next-level-cache = <&L2_0>; 50 enable-method = "psci"; 51 }; 52 53 L2_0: l2-cache0 { 54 compatible = "cache"; 55 cache-level = <2>; 56 cache-unified; 57 }; 58 }; 59 60 timer { 61 compatible = "arm,armv8-timer"; 62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 63 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 64 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 66 }; 67 68 pmu: pmu { 69 compatible = "arm,cortex-a53-pmu"; 70 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 74 interrupt-affinity = <&B53_0>, <&B53_1>, 75 <&B53_2>, <&B53_3>; 76 }; 77 78 clocks: clocks { 79 periph_clk: periph-clk { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <200000000>; 83 }; 84 85 uart_clk: uart-clk { 86 compatible = "fixed-factor-clock"; 87 #clock-cells = <0>; 88 clocks = <&periph_clk>; 89 clock-div = <4>; 90 clock-mult = <1>; 91 }; 92 93 hsspi_pll: hsspi-pll { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <400000000>; 97 }; 98 }; 99 100 psci { 101 compatible = "arm,psci-0.2"; 102 method = "smc"; 103 }; 104 105 axi@81000000 { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0x0 0x0 0x81000000 0x8000>; 110 111 gic: interrupt-controller@1000 { 112 compatible = "arm,gic-400"; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 reg = <0x1000 0x1000>, 117 <0x2000 0x2000>, 118 <0x4000 0x2000>, 119 <0x6000 0x2000>; 120 }; 121 }; 122 123 bus@ff800000 { 124 compatible = "simple-bus"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x0 0x0 0xff800000 0x800000>; 128 129 /* GPIOs 0 .. 31 */ 130 gpio0: gpio@500 { 131 compatible = "brcm,bcm6345-gpio"; 132 reg = <0x500 0x04>, <0x520 0x04>; 133 reg-names = "dirout", "dat"; 134 gpio-controller; 135 #gpio-cells = <2>; 136 status = "disabled"; 137 }; 138 139 /* GPIOs 32 .. 63 */ 140 gpio1: gpio@504 { 141 compatible = "brcm,bcm6345-gpio"; 142 reg = <0x504 0x04>, <0x524 0x04>; 143 reg-names = "dirout", "dat"; 144 gpio-controller; 145 #gpio-cells = <2>; 146 status = "disabled"; 147 }; 148 149 /* GPIOs 64 .. 95 */ 150 gpio2: gpio@508 { 151 compatible = "brcm,bcm6345-gpio"; 152 reg = <0x508 0x04>, <0x528 0x04>; 153 reg-names = "dirout", "dat"; 154 gpio-controller; 155 #gpio-cells = <2>; 156 status = "disabled"; 157 }; 158 159 /* GPIOs 96 .. 127 */ 160 gpio3: gpio@50c { 161 compatible = "brcm,bcm6345-gpio"; 162 reg = <0x50c 0x04>, <0x52c 0x04>; 163 reg-names = "dirout", "dat"; 164 gpio-controller; 165 #gpio-cells = <2>; 166 status = "disabled"; 167 }; 168 169 /* GPIOs 128 .. 159 */ 170 gpio4: gpio@510 { 171 compatible = "brcm,bcm6345-gpio"; 172 reg = <0x510 0x04>, <0x530 0x04>; 173 reg-names = "dirout", "dat"; 174 gpio-controller; 175 #gpio-cells = <2>; 176 status = "disabled"; 177 }; 178 179 /* GPIOs 160 .. 191 */ 180 gpio5: gpio@514 { 181 compatible = "brcm,bcm6345-gpio"; 182 reg = <0x514 0x04>, <0x534 0x04>; 183 reg-names = "dirout", "dat"; 184 gpio-controller; 185 #gpio-cells = <2>; 186 status = "disabled"; 187 }; 188 189 /* GPIOs 192 .. 223 */ 190 gpio6: gpio@518 { 191 compatible = "brcm,bcm6345-gpio"; 192 reg = <0x518 0x04>, <0x538 0x04>; 193 reg-names = "dirout", "dat"; 194 gpio-controller; 195 #gpio-cells = <2>; 196 status = "disabled"; 197 }; 198 199 /* GPIOs 224 .. 255 */ 200 gpio7: gpio@51c { 201 compatible = "brcm,bcm6345-gpio"; 202 reg = <0x51c 0x04>, <0x53c 0x04>; 203 reg-names = "dirout", "dat"; 204 gpio-controller; 205 #gpio-cells = <2>; 206 status = "disabled"; 207 }; 208 209 210 leds: led-controller@800 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 compatible = "brcm,bcm63138-leds"; 214 reg = <0x800 0xdc>; 215 status = "disabled"; 216 }; 217 218 rng@b80 { 219 compatible = "brcm,iproc-rng200"; 220 reg = <0xb80 0x28>; 221 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 hsspi: spi@1000 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0"; 228 reg = <0x1000 0x600>; 229 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&hsspi_pll &hsspi_pll>; 231 clock-names = "hsspi", "pll"; 232 num-cs = <8>; 233 status = "disabled"; 234 }; 235 236 nand_controller: nand-controller@1800 { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 240 reg = <0x1800 0x600>, <0x2000 0x10>; 241 reg-names = "nand", "nand-int-base"; 242 status = "disabled"; 243 244 nandcs: nand@0 { 245 compatible = "brcm,nandcs"; 246 reg = <0>; 247 }; 248 }; 249 250 /* B0 AHB Peripherals */ 251 pl081_dma: dma-controller@11000 { 252 compatible = "arm,pl081", "arm,primecell"; 253 // The magic B105F00D info is missing 254 arm,primecell-periphid = <0x00041081>; 255 reg = <0x11000 0x1000>; 256 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 257 memcpy-burst-size = <256>; 258 memcpy-bus-width = <32>; 259 clocks = <&periph_clk>; 260 clock-names = "apb_pclk"; 261 #dma-cells = <2>; 262 }; 263 264 /* B0 ARM UART Peripheral block */ 265 uart0: serial@12000 { 266 compatible = "arm,pl011", "arm,primecell"; 267 reg = <0x12000 0x1000>; 268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&uart_clk>, <&uart_clk>; 270 clock-names = "uartclk", "apb_pclk"; 271 status = "disabled"; 272 }; 273 274 uart1: serial@13000 { 275 compatible = "arm,pl011", "arm,primecell"; 276 reg = <0x13000 0x1000>; 277 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&uart_clk>, <&uart_clk>; 279 clock-names = "uartclk", "apb_pclk"; 280 status = "disabled"; 281 }; 282 283 uart2: serial@14000 { 284 compatible = "arm,pl011", "arm,primecell"; 285 reg = <0x14000 0x1000>; 286 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&uart_clk>, <&uart_clk>; 288 clock-names = "uartclk", "apb_pclk"; 289 status = "disabled"; 290 }; 291 }; 292}; 293