1e6d7f6dcSSudeep Holla/* 2e6d7f6dcSSudeep Holla * ARM Ltd. Juno Platform 3e6d7f6dcSSudeep Holla * 4e6d7f6dcSSudeep Holla * Copyright (c) 2015 ARM Ltd. 5e6d7f6dcSSudeep Holla * 6e6d7f6dcSSudeep Holla * This file is licensed under a dual GPLv2 or BSD license. 7e6d7f6dcSSudeep Holla */ 8e6d7f6dcSSudeep Holla 9e6d7f6dcSSudeep Holla/dts-v1/; 10e6d7f6dcSSudeep Holla 11e6d7f6dcSSudeep Holla#include <dt-bindings/interrupt-controller/arm-gic.h> 12e7676a00SMike Leach#include <dt-bindings/arm/coresight-cti-dt.h> 13d29e849cSSudeep Holla#include "juno-base.dtsi" 14cdc07e96SMike Leach#include "juno-cs-r1r2.dtsi" 15e6d7f6dcSSudeep Holla 16e6d7f6dcSSudeep Holla/ { 17e6d7f6dcSSudeep Holla model = "ARM Juno development board (r2)"; 18e6d7f6dcSSudeep Holla compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; 19e6d7f6dcSSudeep Holla interrupt-parent = <&gic>; 20e6d7f6dcSSudeep Holla #address-cells = <2>; 21e6d7f6dcSSudeep Holla #size-cells = <2>; 22e6d7f6dcSSudeep Holla 23e6d7f6dcSSudeep Holla aliases { 24e6d7f6dcSSudeep Holla serial0 = &soc_uart0; 25e6d7f6dcSSudeep Holla }; 26e6d7f6dcSSudeep Holla 27e6d7f6dcSSudeep Holla chosen { 28e6d7f6dcSSudeep Holla stdout-path = "serial0:115200n8"; 29e6d7f6dcSSudeep Holla }; 30e6d7f6dcSSudeep Holla 31e6d7f6dcSSudeep Holla psci { 32e6d7f6dcSSudeep Holla compatible = "arm,psci-0.2"; 33e6d7f6dcSSudeep Holla method = "smc"; 34e6d7f6dcSSudeep Holla }; 35e6d7f6dcSSudeep Holla 36e6d7f6dcSSudeep Holla cpus { 37e6d7f6dcSSudeep Holla #address-cells = <2>; 38e6d7f6dcSSudeep Holla #size-cells = <0>; 39e6d7f6dcSSudeep Holla 40e6d7f6dcSSudeep Holla cpu-map { 41e6d7f6dcSSudeep Holla cluster0 { 42e6d7f6dcSSudeep Holla core0 { 43e6d7f6dcSSudeep Holla cpu = <&A72_0>; 44e6d7f6dcSSudeep Holla }; 45e6d7f6dcSSudeep Holla core1 { 46e6d7f6dcSSudeep Holla cpu = <&A72_1>; 47e6d7f6dcSSudeep Holla }; 48e6d7f6dcSSudeep Holla }; 49e6d7f6dcSSudeep Holla 50e6d7f6dcSSudeep Holla cluster1 { 51e6d7f6dcSSudeep Holla core0 { 52e6d7f6dcSSudeep Holla cpu = <&A53_0>; 53e6d7f6dcSSudeep Holla }; 54e6d7f6dcSSudeep Holla core1 { 55e6d7f6dcSSudeep Holla cpu = <&A53_1>; 56e6d7f6dcSSudeep Holla }; 57e6d7f6dcSSudeep Holla core2 { 58e6d7f6dcSSudeep Holla cpu = <&A53_2>; 59e6d7f6dcSSudeep Holla }; 60e6d7f6dcSSudeep Holla core3 { 61e6d7f6dcSSudeep Holla cpu = <&A53_3>; 62e6d7f6dcSSudeep Holla }; 63e6d7f6dcSSudeep Holla }; 64e6d7f6dcSSudeep Holla }; 65e6d7f6dcSSudeep Holla 66e6d7f6dcSSudeep Holla idle-states { 67e9880240SAmit Kucheria entry-method = "psci"; 68e6d7f6dcSSudeep Holla 69e6d7f6dcSSudeep Holla CPU_SLEEP_0: cpu-sleep-0 { 70e6d7f6dcSSudeep Holla compatible = "arm,idle-state"; 71e6d7f6dcSSudeep Holla arm,psci-suspend-param = <0x0010000>; 72e6d7f6dcSSudeep Holla local-timer-stop; 73e6d7f6dcSSudeep Holla entry-latency-us = <300>; 74e6d7f6dcSSudeep Holla exit-latency-us = <1200>; 75e6d7f6dcSSudeep Holla min-residency-us = <2000>; 76e6d7f6dcSSudeep Holla }; 77e6d7f6dcSSudeep Holla 78e6d7f6dcSSudeep Holla CLUSTER_SLEEP_0: cluster-sleep-0 { 79e6d7f6dcSSudeep Holla compatible = "arm,idle-state"; 80e6d7f6dcSSudeep Holla arm,psci-suspend-param = <0x1010000>; 81e6d7f6dcSSudeep Holla local-timer-stop; 82909e481eSSudeep Holla entry-latency-us = <400>; 83e6d7f6dcSSudeep Holla exit-latency-us = <1200>; 84e6d7f6dcSSudeep Holla min-residency-us = <2500>; 85e6d7f6dcSSudeep Holla }; 86e6d7f6dcSSudeep Holla }; 87e6d7f6dcSSudeep Holla 88e6d7f6dcSSudeep Holla A72_0: cpu@0 { 8931af04cdSRob Herring compatible = "arm,cortex-a72"; 90e6d7f6dcSSudeep Holla reg = <0x0 0x0>; 91e6d7f6dcSSudeep Holla device_type = "cpu"; 92e6d7f6dcSSudeep Holla enable-method = "psci"; 93f9936c4aSSudeep Holla i-cache-size = <0xc000>; 94f9936c4aSSudeep Holla i-cache-line-size = <64>; 95f9936c4aSSudeep Holla i-cache-sets = <256>; 96f9936c4aSSudeep Holla d-cache-size = <0x8000>; 97f9936c4aSSudeep Holla d-cache-line-size = <64>; 98f9936c4aSSudeep Holla d-cache-sets = <256>; 99e6d7f6dcSSudeep Holla next-level-cache = <&A72_L2>; 100e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 0>; 101e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 102c1ab65b2SJuri Lelli capacity-dmips-mhz = <1024>; 1034daa001aSDietmar Eggemann dynamic-power-coefficient = <450>; 104e6d7f6dcSSudeep Holla }; 105e6d7f6dcSSudeep Holla 106e6d7f6dcSSudeep Holla A72_1: cpu@1 { 10731af04cdSRob Herring compatible = "arm,cortex-a72"; 108e6d7f6dcSSudeep Holla reg = <0x0 0x1>; 109e6d7f6dcSSudeep Holla device_type = "cpu"; 110e6d7f6dcSSudeep Holla enable-method = "psci"; 111f9936c4aSSudeep Holla i-cache-size = <0xc000>; 112f9936c4aSSudeep Holla i-cache-line-size = <64>; 113f9936c4aSSudeep Holla i-cache-sets = <256>; 114f9936c4aSSudeep Holla d-cache-size = <0x8000>; 115f9936c4aSSudeep Holla d-cache-line-size = <64>; 116f9936c4aSSudeep Holla d-cache-sets = <256>; 117e6d7f6dcSSudeep Holla next-level-cache = <&A72_L2>; 118e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 0>; 119e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 120c1ab65b2SJuri Lelli capacity-dmips-mhz = <1024>; 1214daa001aSDietmar Eggemann dynamic-power-coefficient = <450>; 122e6d7f6dcSSudeep Holla }; 123e6d7f6dcSSudeep Holla 124e6d7f6dcSSudeep Holla A53_0: cpu@100 { 12531af04cdSRob Herring compatible = "arm,cortex-a53"; 126e6d7f6dcSSudeep Holla reg = <0x0 0x100>; 127e6d7f6dcSSudeep Holla device_type = "cpu"; 128e6d7f6dcSSudeep Holla enable-method = "psci"; 129f9936c4aSSudeep Holla i-cache-size = <0x8000>; 130f9936c4aSSudeep Holla i-cache-line-size = <64>; 131f9936c4aSSudeep Holla i-cache-sets = <256>; 132f9936c4aSSudeep Holla d-cache-size = <0x8000>; 133f9936c4aSSudeep Holla d-cache-line-size = <64>; 134f9936c4aSSudeep Holla d-cache-sets = <128>; 135e6d7f6dcSSudeep Holla next-level-cache = <&A53_L2>; 136e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 1>; 137e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 138c1ab65b2SJuri Lelli capacity-dmips-mhz = <485>; 1394daa001aSDietmar Eggemann dynamic-power-coefficient = <140>; 140e6d7f6dcSSudeep Holla }; 141e6d7f6dcSSudeep Holla 142e6d7f6dcSSudeep Holla A53_1: cpu@101 { 14331af04cdSRob Herring compatible = "arm,cortex-a53"; 144e6d7f6dcSSudeep Holla reg = <0x0 0x101>; 145e6d7f6dcSSudeep Holla device_type = "cpu"; 146e6d7f6dcSSudeep Holla enable-method = "psci"; 147f9936c4aSSudeep Holla i-cache-size = <0x8000>; 148f9936c4aSSudeep Holla i-cache-line-size = <64>; 149f9936c4aSSudeep Holla i-cache-sets = <256>; 150f9936c4aSSudeep Holla d-cache-size = <0x8000>; 151f9936c4aSSudeep Holla d-cache-line-size = <64>; 152f9936c4aSSudeep Holla d-cache-sets = <128>; 153e6d7f6dcSSudeep Holla next-level-cache = <&A53_L2>; 154e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 1>; 155e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 156c1ab65b2SJuri Lelli capacity-dmips-mhz = <485>; 1574daa001aSDietmar Eggemann dynamic-power-coefficient = <140>; 158e6d7f6dcSSudeep Holla }; 159e6d7f6dcSSudeep Holla 160e6d7f6dcSSudeep Holla A53_2: cpu@102 { 16131af04cdSRob Herring compatible = "arm,cortex-a53"; 162e6d7f6dcSSudeep Holla reg = <0x0 0x102>; 163e6d7f6dcSSudeep Holla device_type = "cpu"; 164e6d7f6dcSSudeep Holla enable-method = "psci"; 165f9936c4aSSudeep Holla i-cache-size = <0x8000>; 166f9936c4aSSudeep Holla i-cache-line-size = <64>; 167f9936c4aSSudeep Holla i-cache-sets = <256>; 168f9936c4aSSudeep Holla d-cache-size = <0x8000>; 169f9936c4aSSudeep Holla d-cache-line-size = <64>; 170f9936c4aSSudeep Holla d-cache-sets = <128>; 171e6d7f6dcSSudeep Holla next-level-cache = <&A53_L2>; 172e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 1>; 173e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174c1ab65b2SJuri Lelli capacity-dmips-mhz = <485>; 1754daa001aSDietmar Eggemann dynamic-power-coefficient = <140>; 176e6d7f6dcSSudeep Holla }; 177e6d7f6dcSSudeep Holla 178e6d7f6dcSSudeep Holla A53_3: cpu@103 { 17931af04cdSRob Herring compatible = "arm,cortex-a53"; 180e6d7f6dcSSudeep Holla reg = <0x0 0x103>; 181e6d7f6dcSSudeep Holla device_type = "cpu"; 182e6d7f6dcSSudeep Holla enable-method = "psci"; 183f9936c4aSSudeep Holla i-cache-size = <0x8000>; 184f9936c4aSSudeep Holla i-cache-line-size = <64>; 185f9936c4aSSudeep Holla i-cache-sets = <256>; 186f9936c4aSSudeep Holla d-cache-size = <0x8000>; 187f9936c4aSSudeep Holla d-cache-line-size = <64>; 188f9936c4aSSudeep Holla d-cache-sets = <128>; 189e6d7f6dcSSudeep Holla next-level-cache = <&A53_L2>; 190e6d7f6dcSSudeep Holla clocks = <&scpi_dvfs 1>; 191e6d7f6dcSSudeep Holla cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 192c1ab65b2SJuri Lelli capacity-dmips-mhz = <485>; 1934daa001aSDietmar Eggemann dynamic-power-coefficient = <140>; 194e6d7f6dcSSudeep Holla }; 195e6d7f6dcSSudeep Holla 196e6d7f6dcSSudeep Holla A72_L2: l2-cache0 { 197e6d7f6dcSSudeep Holla compatible = "cache"; 198*59fb813fSPierre Gondois cache-unified; 199f9936c4aSSudeep Holla cache-size = <0x200000>; 200f9936c4aSSudeep Holla cache-line-size = <64>; 201f9936c4aSSudeep Holla cache-sets = <2048>; 202156c9041SSudeep Holla cache-level = <2>; 203e6d7f6dcSSudeep Holla }; 204e6d7f6dcSSudeep Holla 205e6d7f6dcSSudeep Holla A53_L2: l2-cache1 { 206e6d7f6dcSSudeep Holla compatible = "cache"; 207*59fb813fSPierre Gondois cache-unified; 208f9936c4aSSudeep Holla cache-size = <0x100000>; 209f9936c4aSSudeep Holla cache-line-size = <64>; 210f9936c4aSSudeep Holla cache-sets = <1024>; 211156c9041SSudeep Holla cache-level = <2>; 212e6d7f6dcSSudeep Holla }; 213e6d7f6dcSSudeep Holla }; 214e6d7f6dcSSudeep Holla 215506eeeabSSudeep Holla pmu-a72 { 216e6d7f6dcSSudeep Holla compatible = "arm,cortex-a72-pmu"; 217e6d7f6dcSSudeep Holla interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 218e6d7f6dcSSudeep Holla <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; 219e6d7f6dcSSudeep Holla interrupt-affinity = <&A72_0>, 220e6d7f6dcSSudeep Holla <&A72_1>; 221e6d7f6dcSSudeep Holla }; 222e6d7f6dcSSudeep Holla 223506eeeabSSudeep Holla pmu-a53 { 224e6d7f6dcSSudeep Holla compatible = "arm,cortex-a53-pmu"; 225e6d7f6dcSSudeep Holla interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 226e6d7f6dcSSudeep Holla <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 227e6d7f6dcSSudeep Holla <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 228e6d7f6dcSSudeep Holla <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 229e6d7f6dcSSudeep Holla interrupt-affinity = <&A53_0>, 230e6d7f6dcSSudeep Holla <&A53_1>, 231e6d7f6dcSSudeep Holla <&A53_2>, 232e6d7f6dcSSudeep Holla <&A53_3>; 233e6d7f6dcSSudeep Holla }; 234e6d7f6dcSSudeep Holla}; 235e6d7f6dcSSudeep Holla 236e6d7f6dcSSudeep Holla&memtimer { 237e6d7f6dcSSudeep Holla status = "okay"; 238e6d7f6dcSSudeep Holla}; 239e6d7f6dcSSudeep Holla 240e6d7f6dcSSudeep Holla&pcie_ctlr { 241e6d7f6dcSSudeep Holla status = "okay"; 242e6d7f6dcSSudeep Holla}; 2433e287cf6SSudeep Holla 244d9df28baSRobin Murphy&smmu_pcie { 245d9df28baSRobin Murphy status = "okay"; 246d9df28baSRobin Murphy}; 247d9df28baSRobin Murphy 2483e287cf6SSudeep Holla&etm0 { 2493e287cf6SSudeep Holla cpu = <&A72_0>; 2503e287cf6SSudeep Holla}; 2513e287cf6SSudeep Holla 2523e287cf6SSudeep Holla&etm1 { 2533e287cf6SSudeep Holla cpu = <&A72_1>; 2543e287cf6SSudeep Holla}; 2553e287cf6SSudeep Holla 2563e287cf6SSudeep Holla&etm2 { 2573e287cf6SSudeep Holla cpu = <&A53_0>; 2583e287cf6SSudeep Holla}; 2593e287cf6SSudeep Holla 2603e287cf6SSudeep Holla&etm3 { 2613e287cf6SSudeep Holla cpu = <&A53_1>; 2623e287cf6SSudeep Holla}; 2633e287cf6SSudeep Holla 2643e287cf6SSudeep Holla&etm4 { 2653e287cf6SSudeep Holla cpu = <&A53_2>; 2663e287cf6SSudeep Holla}; 2673e287cf6SSudeep Holla 2683e287cf6SSudeep Holla&etm5 { 2693e287cf6SSudeep Holla cpu = <&A53_3>; 2703e287cf6SSudeep Holla}; 271f7b636a8SJavi Merino 272f7b636a8SJavi Merino&big_cluster_thermal_zone { 273f7b636a8SJavi Merino status = "okay"; 274f7b636a8SJavi Merino}; 275f7b636a8SJavi Merino 276f7b636a8SJavi Merino&little_cluster_thermal_zone { 277f7b636a8SJavi Merino status = "okay"; 278f7b636a8SJavi Merino}; 279f7b636a8SJavi Merino 280f7b636a8SJavi Merino&gpu0_thermal_zone { 281f7b636a8SJavi Merino status = "okay"; 282f7b636a8SJavi Merino}; 283f7b636a8SJavi Merino 284f7b636a8SJavi Merino&gpu1_thermal_zone { 285f7b636a8SJavi Merino status = "okay"; 286f7b636a8SJavi Merino}; 287cdc07e96SMike Leach 288cdc07e96SMike Leach&etf0_out_port { 289cdc07e96SMike Leach remote-endpoint = <&csys2_funnel_in_port0>; 290cdc07e96SMike Leach}; 291cdc07e96SMike Leach 292cdc07e96SMike Leach&replicator_in_port0 { 293cdc07e96SMike Leach remote-endpoint = <&csys2_funnel_out_port>; 294cdc07e96SMike Leach}; 295cde6f9abSMike Leach 296072495b3SRob Herring&csys1_funnel_in_port0 { 297072495b3SRob Herring remote-endpoint = <&stm_out_port>; 298072495b3SRob Herring}; 299072495b3SRob Herring 300cde6f9abSMike Leach&stm_out_port { 301cde6f9abSMike Leach remote-endpoint = <&csys1_funnel_in_port0>; 302cde6f9abSMike Leach}; 30360f01d7aSSuzuki K Poulose 30460f01d7aSSuzuki K Poulose&cpu_debug0 { 30560f01d7aSSuzuki K Poulose cpu = <&A72_0>; 30660f01d7aSSuzuki K Poulose}; 30760f01d7aSSuzuki K Poulose 30860f01d7aSSuzuki K Poulose&cpu_debug1 { 30960f01d7aSSuzuki K Poulose cpu = <&A72_1>; 31060f01d7aSSuzuki K Poulose}; 31160f01d7aSSuzuki K Poulose 31260f01d7aSSuzuki K Poulose&cpu_debug2 { 31360f01d7aSSuzuki K Poulose cpu = <&A53_0>; 31460f01d7aSSuzuki K Poulose}; 31560f01d7aSSuzuki K Poulose 31660f01d7aSSuzuki K Poulose&cpu_debug3 { 31760f01d7aSSuzuki K Poulose cpu = <&A53_1>; 31860f01d7aSSuzuki K Poulose}; 31960f01d7aSSuzuki K Poulose 32060f01d7aSSuzuki K Poulose&cpu_debug4 { 32160f01d7aSSuzuki K Poulose cpu = <&A53_2>; 32260f01d7aSSuzuki K Poulose}; 32360f01d7aSSuzuki K Poulose 32460f01d7aSSuzuki K Poulose&cpu_debug5 { 32560f01d7aSSuzuki K Poulose cpu = <&A53_3>; 32660f01d7aSSuzuki K Poulose}; 327e7676a00SMike Leach 328e7676a00SMike Leach&cti0 { 329e7676a00SMike Leach cpu = <&A72_0>; 330e7676a00SMike Leach}; 331e7676a00SMike Leach 332e7676a00SMike Leach&cti1 { 333e7676a00SMike Leach cpu = <&A72_1>; 334e7676a00SMike Leach}; 335e7676a00SMike Leach 336e7676a00SMike Leach&cti2 { 337e7676a00SMike Leach cpu = <&A53_0>; 338e7676a00SMike Leach}; 339e7676a00SMike Leach 340e7676a00SMike Leach&cti3 { 341e7676a00SMike Leach cpu = <&A53_1>; 342e7676a00SMike Leach}; 343e7676a00SMike Leach 344e7676a00SMike Leach&cti4 { 345e7676a00SMike Leach cpu = <&A53_2>; 346e7676a00SMike Leach}; 347e7676a00SMike Leach 348e7676a00SMike Leach&cti5 { 349e7676a00SMike Leach cpu = <&A53_3>; 350e7676a00SMike Leach}; 351