1/* 2 * linux/arch/arm/mm/proc-sa1100.S 3 * 4 * Copyright (C) 1997-2002 Russell King 5 * hacked for non-paged-MM by Hyok S. Choi, 2003. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * MMU functions for SA110 12 * 13 * These are the low level assembler for performing cache and TLB 14 * functions on the StrongARM-1100 and StrongARM-1110. 15 * 16 * Note that SA1100 and SA1110 share everything but their name and CPU ID. 17 * 18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl): 19 * Flush the read buffer at context switches 20 */ 21#include <linux/linkage.h> 22#include <linux/init.h> 23#include <asm/assembler.h> 24#include <asm/asm-offsets.h> 25#include <asm/procinfo.h> 26#include <asm/hardware.h> 27#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable.h> 29 30/* 31 * the cache line size of the I and D cache 32 */ 33#define DCACHELINESIZE 32 34 35 __INIT 36 37/* 38 * cpu_sa1100_proc_init() 39 */ 40ENTRY(cpu_sa1100_proc_init) 41 mov r0, #0 42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 44 mov pc, lr 45 46 .previous 47 48/* 49 * cpu_sa1100_proc_fin() 50 * 51 * Prepare the CPU for reset: 52 * - Disable interrupts 53 * - Clean and turn off caches. 54 */ 55ENTRY(cpu_sa1100_proc_fin) 56 stmfd sp!, {lr} 57 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 58 msr cpsr_c, ip 59 bl v4wb_flush_kern_cache_all 60 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 61 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 62 bic r0, r0, #0x1000 @ ...i............ 63 bic r0, r0, #0x000e @ ............wca. 64 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 ldmfd sp!, {pc} 66 67/* 68 * cpu_sa1100_reset(loc) 69 * 70 * Perform a soft reset of the system. Put the CPU into the 71 * same state as it would be if it had been reset, and branch 72 * to what would be the reset vector. 73 * 74 * loc: location to jump to for soft reset 75 */ 76 .align 5 77ENTRY(cpu_sa1100_reset) 78 mov ip, #0 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 81#ifdef CONFIG_MMU 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 83#endif 84 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 85 bic ip, ip, #0x000f @ ............wcam 86 bic ip, ip, #0x1100 @ ...i...s........ 87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 88 mov pc, r0 89 90/* 91 * cpu_sa1100_do_idle(type) 92 * 93 * Cause the processor to idle 94 * 95 * type: call type: 96 * 0 = slow idle 97 * 1 = fast idle 98 * 2 = switch to slow processor clock 99 * 3 = switch to fast processor clock 100 */ 101 .align 5 102ENTRY(cpu_sa1100_do_idle) 103 mov r0, r0 @ 4 nop padding 104 mov r0, r0 105 mov r0, r0 106 mov r0, r0 @ 4 nop padding 107 mov r0, r0 108 mov r0, r0 109 mov r0, #0 110 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address 111 @ --- aligned to a cache line 112 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 113 ldr r1, [r1, #0] @ force switch to MCLK 114 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt 115 mov r0, r0 @ safety 116 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching 117 mov pc, lr 118 119/* ================================= CACHE ================================ */ 120 121/* 122 * cpu_sa1100_dcache_clean_area(addr,sz) 123 * 124 * Clean the specified entry of any caches such that the MMU 125 * translation fetches will obtain correct data. 126 * 127 * addr: cache-unaligned virtual address 128 */ 129 .align 5 130ENTRY(cpu_sa1100_dcache_clean_area) 1311: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 132 add r0, r0, #DCACHELINESIZE 133 subs r1, r1, #DCACHELINESIZE 134 bhi 1b 135 mov pc, lr 136 137/* =============================== PageTable ============================== */ 138 139/* 140 * cpu_sa1100_switch_mm(pgd) 141 * 142 * Set the translation base pointer to be as described by pgd. 143 * 144 * pgd: new page tables 145 */ 146 .align 5 147ENTRY(cpu_sa1100_switch_mm) 148#ifdef CONFIG_MMU 149 str lr, [sp, #-4]! 150 bl v4wb_flush_kern_cache_all @ clears IP 151 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 152 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 153 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 154 ldr pc, [sp], #4 155#else 156 mov pc, lr 157#endif 158 159/* 160 * cpu_sa1100_set_pte(ptep, pte) 161 * 162 * Set a PTE and flush it out 163 */ 164 .align 5 165ENTRY(cpu_sa1100_set_pte) 166#ifdef CONFIG_MMU 167 str r1, [r0], #-2048 @ linux version 168 169 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 170 171 bic r2, r1, #PTE_SMALL_AP_MASK 172 bic r2, r2, #PTE_TYPE_MASK 173 orr r2, r2, #PTE_TYPE_SMALL 174 175 tst r1, #L_PTE_USER @ User? 176 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 177 178 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 179 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 180 181 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 182 movne r2, #0 183 184 str r2, [r0] @ hardware version 185 mov r0, r0 186 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 187 mcr p15, 0, r0, c7, c10, 4 @ drain WB 188#endif 189 mov pc, lr 190 191 __INIT 192 193 .type __sa1100_setup, #function 194__sa1100_setup: 195 mov r0, #0 196 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 197 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 198#ifdef CONFIG_MMU 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 200#endif 201 mrc p15, 0, r0, c1, c0 @ get control register v4 202 ldr r5, sa1100_cr1_clear 203 bic r0, r0, r5 204 ldr r5, sa1100_cr1_set 205 orr r0, r0, r5 206 mov pc, lr 207 .size __sa1100_setup, . - __sa1100_setup 208 209 /* 210 * R 211 * .RVI ZFRS BLDP WCAM 212 * ..11 0001 ..11 1101 213 * 214 */ 215 .type sa1100_cr1_clear, #object 216 .type sa1100_cr1_set, #object 217sa1100_cr1_clear: 218 .word 0x3f3f 219sa1100_cr1_set: 220 .word 0x313d 221 222 __INITDATA 223 224/* 225 * Purpose : Function pointers used to access above functions - all calls 226 * come through these 227 */ 228 229/* 230 * SA1100 and SA1110 share the same function calls 231 */ 232 .type sa1100_processor_functions, #object 233ENTRY(sa1100_processor_functions) 234 .word v4_early_abort 235 .word cpu_sa1100_proc_init 236 .word cpu_sa1100_proc_fin 237 .word cpu_sa1100_reset 238 .word cpu_sa1100_do_idle 239 .word cpu_sa1100_dcache_clean_area 240 .word cpu_sa1100_switch_mm 241 .word cpu_sa1100_set_pte 242 .size sa1100_processor_functions, . - sa1100_processor_functions 243 244 .section ".rodata" 245 246 .type cpu_arch_name, #object 247cpu_arch_name: 248 .asciz "armv4" 249 .size cpu_arch_name, . - cpu_arch_name 250 251 .type cpu_elf_name, #object 252cpu_elf_name: 253 .asciz "v4" 254 .size cpu_elf_name, . - cpu_elf_name 255 256 .type cpu_sa1100_name, #object 257cpu_sa1100_name: 258 .asciz "StrongARM-1100" 259 .size cpu_sa1100_name, . - cpu_sa1100_name 260 261 .type cpu_sa1110_name, #object 262cpu_sa1110_name: 263 .asciz "StrongARM-1110" 264 .size cpu_sa1110_name, . - cpu_sa1110_name 265 266 .align 267 268 .section ".proc.info.init", #alloc, #execinstr 269 270 .type __sa1100_proc_info,#object 271__sa1100_proc_info: 272 .long 0x4401a110 273 .long 0xfffffff0 274 .long PMD_TYPE_SECT | \ 275 PMD_SECT_BUFFERABLE | \ 276 PMD_SECT_CACHEABLE | \ 277 PMD_SECT_AP_WRITE | \ 278 PMD_SECT_AP_READ 279 b __sa1100_setup 280 .long cpu_arch_name 281 .long cpu_elf_name 282 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT 283 .long cpu_sa1100_name 284 .long sa1100_processor_functions 285 .long v4wb_tlb_fns 286 .long v4_mc_user_fns 287 .long v4wb_cache_fns 288 .size __sa1100_proc_info, . - __sa1100_proc_info 289 290 .type __sa1110_proc_info,#object 291__sa1110_proc_info: 292 .long 0x6901b110 293 .long 0xfffffff0 294 .long PMD_TYPE_SECT | \ 295 PMD_SECT_BUFFERABLE | \ 296 PMD_SECT_CACHEABLE | \ 297 PMD_SECT_AP_WRITE | \ 298 PMD_SECT_AP_READ 299 b __sa1100_setup 300 .long cpu_arch_name 301 .long cpu_elf_name 302 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT 303 .long cpu_sa1110_name 304 .long sa1100_processor_functions 305 .long v4wb_tlb_fns 306 .long v4_mc_user_fns 307 .long v4wb_cache_fns 308 .size __sa1110_proc_info, . - __sa1110_proc_info 309