1/* 2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020 3 * 4 * Copyright (C) 2000 ARM Limited 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * hacked for non-paged-MM by Hyok S. Choi, 2003. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * 23 * These are the low level assembler for performing cache and TLB 24 * functions on the arm1020e. 25 * 26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt 27 */ 28#include <linux/linkage.h> 29#include <linux/config.h> 30#include <linux/init.h> 31#include <asm/assembler.h> 32#include <asm/asm-offsets.h> 33#include <asm/pgtable-hwdef.h> 34#include <asm/pgtable.h> 35#include <asm/procinfo.h> 36#include <asm/ptrace.h> 37 38/* 39 * This is the maximum size of an area which will be invalidated 40 * using the single invalidate entry instructions. Anything larger 41 * than this, and we go for the whole cache. 42 * 43 * This value should be chosen such that we choose the cheapest 44 * alternative. 45 */ 46#define MAX_AREA_SIZE 32768 47 48/* 49 * The size of one data cache line. 50 */ 51#define CACHE_DLINESIZE 32 52 53/* 54 * The number of data cache segments. 55 */ 56#define CACHE_DSEGMENTS 16 57 58/* 59 * The number of lines in a cache segment. 60 */ 61#define CACHE_DENTRIES 64 62 63/* 64 * This is the size at which it becomes more efficient to 65 * clean the whole cache, rather than using the individual 66 * cache line maintainence instructions. 67 */ 68#define CACHE_DLIMIT 32768 69 70 .text 71/* 72 * cpu_arm1020e_proc_init() 73 */ 74ENTRY(cpu_arm1020e_proc_init) 75 mov pc, lr 76 77/* 78 * cpu_arm1020e_proc_fin() 79 */ 80ENTRY(cpu_arm1020e_proc_fin) 81 stmfd sp!, {lr} 82 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 83 msr cpsr_c, ip 84 bl arm1020e_flush_kern_cache_all 85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 86 bic r0, r0, #0x1000 @ ...i............ 87 bic r0, r0, #0x000e @ ............wca. 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches 89 ldmfd sp!, {pc} 90 91/* 92 * cpu_arm1020e_reset(loc) 93 * 94 * Perform a soft reset of the system. Put the CPU into the 95 * same state as it would be if it had been reset, and branch 96 * to what would be the reset vector. 97 * 98 * loc: location to jump to for soft reset 99 */ 100 .align 5 101ENTRY(cpu_arm1020e_reset) 102 mov ip, #0 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB 105#ifdef CONFIG_MMU 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107#endif 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 109 bic ip, ip, #0x000f @ ............wcam 110 bic ip, ip, #0x1100 @ ...i...s........ 111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 112 mov pc, r0 113 114/* 115 * cpu_arm1020e_do_idle() 116 */ 117 .align 5 118ENTRY(cpu_arm1020e_do_idle) 119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 120 mov pc, lr 121 122/* ================================= CACHE ================================ */ 123 124 .align 5 125/* 126 * flush_user_cache_all() 127 * 128 * Invalidate all cache entries in a particular address 129 * space. 130 */ 131ENTRY(arm1020e_flush_user_cache_all) 132 /* FALLTHROUGH */ 133/* 134 * flush_kern_cache_all() 135 * 136 * Clean and invalidate the entire cache. 137 */ 138ENTRY(arm1020e_flush_kern_cache_all) 139 mov r2, #VM_EXEC 140 mov ip, #0 141__flush_whole_cache: 142#ifndef CONFIG_CPU_DCACHE_DISABLE 143 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 1451: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1462: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 147 subs r3, r3, #1 << 26 148 bcs 2b @ entries 63 to 0 149 subs r1, r1, #1 << 5 150 bcs 1b @ segments 15 to 0 151#endif 152 tst r2, #VM_EXEC 153#ifndef CONFIG_CPU_ICACHE_DISABLE 154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155#endif 156 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 157 mov pc, lr 158 159/* 160 * flush_user_cache_range(start, end, flags) 161 * 162 * Invalidate a range of cache entries in the specified 163 * address space. 164 * 165 * - start - start address (inclusive) 166 * - end - end address (exclusive) 167 * - flags - vm_flags for this space 168 */ 169ENTRY(arm1020e_flush_user_cache_range) 170 mov ip, #0 171 sub r3, r1, r0 @ calculate total size 172 cmp r3, #CACHE_DLIMIT 173 bhs __flush_whole_cache 174 175#ifndef CONFIG_CPU_DCACHE_DISABLE 1761: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 177 add r0, r0, #CACHE_DLINESIZE 178 cmp r0, r1 179 blo 1b 180#endif 181 tst r2, #VM_EXEC 182#ifndef CONFIG_CPU_ICACHE_DISABLE 183 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 184#endif 185 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 186 mov pc, lr 187 188/* 189 * coherent_kern_range(start, end) 190 * 191 * Ensure coherency between the Icache and the Dcache in the 192 * region described by start. If you have non-snooping 193 * Harvard caches, you need to implement this function. 194 * 195 * - start - virtual start address 196 * - end - virtual end address 197 */ 198ENTRY(arm1020e_coherent_kern_range) 199 /* FALLTHROUGH */ 200/* 201 * coherent_user_range(start, end) 202 * 203 * Ensure coherency between the Icache and the Dcache in the 204 * region described by start. If you have non-snooping 205 * Harvard caches, you need to implement this function. 206 * 207 * - start - virtual start address 208 * - end - virtual end address 209 */ 210ENTRY(arm1020e_coherent_user_range) 211 mov ip, #0 212 bic r0, r0, #CACHE_DLINESIZE - 1 2131: 214#ifndef CONFIG_CPU_DCACHE_DISABLE 215 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 216#endif 217#ifndef CONFIG_CPU_ICACHE_DISABLE 218 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 219#endif 220 add r0, r0, #CACHE_DLINESIZE 221 cmp r0, r1 222 blo 1b 223 mcr p15, 0, ip, c7, c10, 4 @ drain WB 224 mov pc, lr 225 226/* 227 * flush_kern_dcache_page(void *page) 228 * 229 * Ensure no D cache aliasing occurs, either with itself or 230 * the I cache 231 * 232 * - page - page aligned address 233 */ 234ENTRY(arm1020e_flush_kern_dcache_page) 235 mov ip, #0 236#ifndef CONFIG_CPU_DCACHE_DISABLE 237 add r1, r0, #PAGE_SZ 2381: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 239 add r0, r0, #CACHE_DLINESIZE 240 cmp r0, r1 241 blo 1b 242#endif 243 mcr p15, 0, ip, c7, c10, 4 @ drain WB 244 mov pc, lr 245 246/* 247 * dma_inv_range(start, end) 248 * 249 * Invalidate (discard) the specified virtual address range. 250 * May not write back any entries. If 'start' or 'end' 251 * are not cache line aligned, those lines must be written 252 * back. 253 * 254 * - start - virtual start address 255 * - end - virtual end address 256 * 257 * (same as v4wb) 258 */ 259ENTRY(arm1020e_dma_inv_range) 260 mov ip, #0 261#ifndef CONFIG_CPU_DCACHE_DISABLE 262 tst r0, #CACHE_DLINESIZE - 1 263 bic r0, r0, #CACHE_DLINESIZE - 1 264 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 265 tst r1, #CACHE_DLINESIZE - 1 266 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 2671: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 268 add r0, r0, #CACHE_DLINESIZE 269 cmp r0, r1 270 blo 1b 271#endif 272 mcr p15, 0, ip, c7, c10, 4 @ drain WB 273 mov pc, lr 274 275/* 276 * dma_clean_range(start, end) 277 * 278 * Clean the specified virtual address range. 279 * 280 * - start - virtual start address 281 * - end - virtual end address 282 * 283 * (same as v4wb) 284 */ 285ENTRY(arm1020e_dma_clean_range) 286 mov ip, #0 287#ifndef CONFIG_CPU_DCACHE_DISABLE 288 bic r0, r0, #CACHE_DLINESIZE - 1 2891: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 290 add r0, r0, #CACHE_DLINESIZE 291 cmp r0, r1 292 blo 1b 293#endif 294 mcr p15, 0, ip, c7, c10, 4 @ drain WB 295 mov pc, lr 296 297/* 298 * dma_flush_range(start, end) 299 * 300 * Clean and invalidate the specified virtual address range. 301 * 302 * - start - virtual start address 303 * - end - virtual end address 304 */ 305ENTRY(arm1020e_dma_flush_range) 306 mov ip, #0 307#ifndef CONFIG_CPU_DCACHE_DISABLE 308 bic r0, r0, #CACHE_DLINESIZE - 1 3091: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 310 add r0, r0, #CACHE_DLINESIZE 311 cmp r0, r1 312 blo 1b 313#endif 314 mcr p15, 0, ip, c7, c10, 4 @ drain WB 315 mov pc, lr 316 317ENTRY(arm1020e_cache_fns) 318 .long arm1020e_flush_kern_cache_all 319 .long arm1020e_flush_user_cache_all 320 .long arm1020e_flush_user_cache_range 321 .long arm1020e_coherent_kern_range 322 .long arm1020e_coherent_user_range 323 .long arm1020e_flush_kern_dcache_page 324 .long arm1020e_dma_inv_range 325 .long arm1020e_dma_clean_range 326 .long arm1020e_dma_flush_range 327 328 .align 5 329ENTRY(cpu_arm1020e_dcache_clean_area) 330#ifndef CONFIG_CPU_DCACHE_DISABLE 331 mov ip, #0 3321: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 333 add r0, r0, #CACHE_DLINESIZE 334 subs r1, r1, #CACHE_DLINESIZE 335 bhi 1b 336#endif 337 mov pc, lr 338 339/* =============================== PageTable ============================== */ 340 341/* 342 * cpu_arm1020e_switch_mm(pgd) 343 * 344 * Set the translation base pointer to be as described by pgd. 345 * 346 * pgd: new page tables 347 */ 348 .align 5 349ENTRY(cpu_arm1020e_switch_mm) 350#ifdef CONFIG_MMU 351#ifndef CONFIG_CPU_DCACHE_DISABLE 352 mcr p15, 0, r3, c7, c10, 4 353 mov r1, #0xF @ 16 segments 3541: mov r3, #0x3F @ 64 entries 3552: mov ip, r3, LSL #26 @ shift up entry 356 orr ip, ip, r1, LSL #5 @ shift in/up index 357 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 358 mov ip, #0 359 subs r3, r3, #1 360 cmp r3, #0 361 bge 2b @ entries 3F to 0 362 subs r1, r1, #1 363 cmp r1, #0 364 bge 1b @ segments 15 to 0 365 366#endif 367 mov r1, #0 368#ifndef CONFIG_CPU_ICACHE_DISABLE 369 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 370#endif 371 mcr p15, 0, r1, c7, c10, 4 @ drain WB 372 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 373 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 374#endif 375 mov pc, lr 376 377/* 378 * cpu_arm1020e_set_pte(ptep, pte) 379 * 380 * Set a PTE and flush it out 381 */ 382 .align 5 383ENTRY(cpu_arm1020e_set_pte) 384#ifdef CONFIG_MMU 385 str r1, [r0], #-2048 @ linux version 386 387 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 388 389 bic r2, r1, #PTE_SMALL_AP_MASK 390 bic r2, r2, #PTE_TYPE_MASK 391 orr r2, r2, #PTE_TYPE_SMALL 392 393 tst r1, #L_PTE_USER @ User? 394 orrne r2, r2, #PTE_SMALL_AP_URO_SRW 395 396 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 397 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW 398 399 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 400 movne r2, #0 401 402#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 403 eor r3, r1, #0x0a @ C & small page? 404 tst r3, #0x0b 405 biceq r2, r2, #4 406#endif 407 str r2, [r0] @ hardware version 408 mov r0, r0 409#ifndef CONFIG_CPU_DCACHE_DISABLE 410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 411#endif 412#endif /* CONFIG_MMU */ 413 mov pc, lr 414 415 __INIT 416 417 .type __arm1020e_setup, #function 418__arm1020e_setup: 419 mov r0, #0 420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 422#ifdef CONFIG_MMU 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 424#endif 425 mrc p15, 0, r0, c1, c0 @ get control register v4 426 ldr r5, arm1020e_cr1_clear 427 bic r0, r0, r5 428 ldr r5, arm1020e_cr1_set 429 orr r0, r0, r5 430#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 431 orr r0, r0, #0x4000 @ .R.. .... .... .... 432#endif 433 mov pc, lr 434 .size __arm1020e_setup, . - __arm1020e_setup 435 436 /* 437 * R 438 * .RVI ZFRS BLDP WCAM 439 * .011 1001 ..11 0101 440 */ 441 .type arm1020e_cr1_clear, #object 442 .type arm1020e_cr1_set, #object 443arm1020e_cr1_clear: 444 .word 0x5f3f 445arm1020e_cr1_set: 446 .word 0x3935 447 448 __INITDATA 449 450/* 451 * Purpose : Function pointers used to access above functions - all calls 452 * come through these 453 */ 454 .type arm1020e_processor_functions, #object 455arm1020e_processor_functions: 456 .word v4t_early_abort 457 .word cpu_arm1020e_proc_init 458 .word cpu_arm1020e_proc_fin 459 .word cpu_arm1020e_reset 460 .word cpu_arm1020e_do_idle 461 .word cpu_arm1020e_dcache_clean_area 462 .word cpu_arm1020e_switch_mm 463 .word cpu_arm1020e_set_pte 464 .size arm1020e_processor_functions, . - arm1020e_processor_functions 465 466 .section ".rodata" 467 468 .type cpu_arch_name, #object 469cpu_arch_name: 470 .asciz "armv5te" 471 .size cpu_arch_name, . - cpu_arch_name 472 473 .type cpu_elf_name, #object 474cpu_elf_name: 475 .asciz "v5" 476 .size cpu_elf_name, . - cpu_elf_name 477 478 .type cpu_arm1020e_name, #object 479cpu_arm1020e_name: 480 .ascii "ARM1020E" 481#ifndef CONFIG_CPU_ICACHE_DISABLE 482 .ascii "i" 483#endif 484#ifndef CONFIG_CPU_DCACHE_DISABLE 485 .ascii "d" 486#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 487 .ascii "(wt)" 488#else 489 .ascii "(wb)" 490#endif 491#endif 492#ifndef CONFIG_CPU_BPREDICT_DISABLE 493 .ascii "B" 494#endif 495#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN 496 .ascii "RR" 497#endif 498 .ascii "\0" 499 .size cpu_arm1020e_name, . - cpu_arm1020e_name 500 501 .align 502 503 .section ".proc.info.init", #alloc, #execinstr 504 505 .type __arm1020e_proc_info,#object 506__arm1020e_proc_info: 507 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE) 508 .long 0xff0ffff0 509 .long PMD_TYPE_SECT | \ 510 PMD_BIT4 | \ 511 PMD_SECT_AP_WRITE | \ 512 PMD_SECT_AP_READ 513 b __arm1020e_setup 514 .long cpu_arch_name 515 .long cpu_elf_name 516 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP 517 .long cpu_arm1020e_name 518 .long arm1020e_processor_functions 519 .long v4wbi_tlb_fns 520 .long v4wb_user_fns 521 .long arm1020e_cache_fns 522 .size __arm1020e_proc_info, . - __arm1020e_proc_info 523