1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/bootmem.h> 15 #include <linux/mman.h> 16 #include <linux/nodemask.h> 17 18 #include <asm/mach-types.h> 19 #include <asm/setup.h> 20 #include <asm/sizes.h> 21 #include <asm/tlb.h> 22 23 #include <asm/mach/arch.h> 24 #include <asm/mach/map.h> 25 26 #include "mm.h" 27 28 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 29 30 extern void _stext, _etext, __data_start, _end; 31 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 32 33 /* 34 * empty_zero_page is a special page that is used for 35 * zero-initialized data and COW. 36 */ 37 struct page *empty_zero_page; 38 39 /* 40 * The pmd table for the upper-most set of pages. 41 */ 42 pmd_t *top_pmd; 43 44 #define CPOLICY_UNCACHED 0 45 #define CPOLICY_BUFFERED 1 46 #define CPOLICY_WRITETHROUGH 2 47 #define CPOLICY_WRITEBACK 3 48 #define CPOLICY_WRITEALLOC 4 49 50 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 51 static unsigned int ecc_mask __initdata = 0; 52 pgprot_t pgprot_user; 53 pgprot_t pgprot_kernel; 54 55 EXPORT_SYMBOL(pgprot_user); 56 EXPORT_SYMBOL(pgprot_kernel); 57 58 struct cachepolicy { 59 const char policy[16]; 60 unsigned int cr_mask; 61 unsigned int pmd; 62 unsigned int pte; 63 }; 64 65 static struct cachepolicy cache_policies[] __initdata = { 66 { 67 .policy = "uncached", 68 .cr_mask = CR_W|CR_C, 69 .pmd = PMD_SECT_UNCACHED, 70 .pte = 0, 71 }, { 72 .policy = "buffered", 73 .cr_mask = CR_C, 74 .pmd = PMD_SECT_BUFFERED, 75 .pte = PTE_BUFFERABLE, 76 }, { 77 .policy = "writethrough", 78 .cr_mask = 0, 79 .pmd = PMD_SECT_WT, 80 .pte = PTE_CACHEABLE, 81 }, { 82 .policy = "writeback", 83 .cr_mask = 0, 84 .pmd = PMD_SECT_WB, 85 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 86 }, { 87 .policy = "writealloc", 88 .cr_mask = 0, 89 .pmd = PMD_SECT_WBWA, 90 .pte = PTE_BUFFERABLE|PTE_CACHEABLE, 91 } 92 }; 93 94 /* 95 * These are useful for identifing cache coherency 96 * problems by allowing the cache or the cache and 97 * writebuffer to be turned off. (Note: the write 98 * buffer should not be on and the cache off). 99 */ 100 static void __init early_cachepolicy(char **p) 101 { 102 int i; 103 104 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 105 int len = strlen(cache_policies[i].policy); 106 107 if (memcmp(*p, cache_policies[i].policy, len) == 0) { 108 cachepolicy = i; 109 cr_alignment &= ~cache_policies[i].cr_mask; 110 cr_no_alignment &= ~cache_policies[i].cr_mask; 111 *p += len; 112 break; 113 } 114 } 115 if (i == ARRAY_SIZE(cache_policies)) 116 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 117 flush_cache_all(); 118 set_cr(cr_alignment); 119 } 120 __early_param("cachepolicy=", early_cachepolicy); 121 122 static void __init early_nocache(char **__unused) 123 { 124 char *p = "buffered"; 125 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 126 early_cachepolicy(&p); 127 } 128 __early_param("nocache", early_nocache); 129 130 static void __init early_nowrite(char **__unused) 131 { 132 char *p = "uncached"; 133 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 134 early_cachepolicy(&p); 135 } 136 __early_param("nowb", early_nowrite); 137 138 static void __init early_ecc(char **p) 139 { 140 if (memcmp(*p, "on", 2) == 0) { 141 ecc_mask = PMD_PROTECTION; 142 *p += 2; 143 } else if (memcmp(*p, "off", 3) == 0) { 144 ecc_mask = 0; 145 *p += 3; 146 } 147 } 148 __early_param("ecc=", early_ecc); 149 150 static int __init noalign_setup(char *__unused) 151 { 152 cr_alignment &= ~CR_A; 153 cr_no_alignment &= ~CR_A; 154 set_cr(cr_alignment); 155 return 1; 156 } 157 __setup("noalign", noalign_setup); 158 159 #ifndef CONFIG_SMP 160 void adjust_cr(unsigned long mask, unsigned long set) 161 { 162 unsigned long flags; 163 164 mask &= ~CR_A; 165 166 set &= mask; 167 168 local_irq_save(flags); 169 170 cr_no_alignment = (cr_no_alignment & ~mask) | set; 171 cr_alignment = (cr_alignment & ~mask) | set; 172 173 set_cr((get_cr() & ~mask) | set); 174 175 local_irq_restore(flags); 176 } 177 #endif 178 179 struct mem_types { 180 unsigned int prot_pte; 181 unsigned int prot_l1; 182 unsigned int prot_sect; 183 unsigned int domain; 184 }; 185 186 static struct mem_types mem_types[] __initdata = { 187 [MT_DEVICE] = { 188 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 189 L_PTE_WRITE, 190 .prot_l1 = PMD_TYPE_TABLE, 191 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED | 192 PMD_SECT_AP_WRITE, 193 .domain = DOMAIN_IO, 194 }, 195 [MT_CACHECLEAN] = { 196 .prot_sect = PMD_TYPE_SECT | PMD_BIT4, 197 .domain = DOMAIN_KERNEL, 198 }, 199 [MT_MINICLEAN] = { 200 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE, 201 .domain = DOMAIN_KERNEL, 202 }, 203 [MT_LOW_VECTORS] = { 204 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 205 L_PTE_EXEC, 206 .prot_l1 = PMD_TYPE_TABLE, 207 .domain = DOMAIN_USER, 208 }, 209 [MT_HIGH_VECTORS] = { 210 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 211 L_PTE_USER | L_PTE_EXEC, 212 .prot_l1 = PMD_TYPE_TABLE, 213 .domain = DOMAIN_USER, 214 }, 215 [MT_MEMORY] = { 216 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE, 217 .domain = DOMAIN_KERNEL, 218 }, 219 [MT_ROM] = { 220 .prot_sect = PMD_TYPE_SECT | PMD_BIT4, 221 .domain = DOMAIN_KERNEL, 222 }, 223 [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */ 224 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 225 L_PTE_WRITE, 226 .prot_l1 = PMD_TYPE_TABLE, 227 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED | 228 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | 229 PMD_SECT_TEX(1), 230 .domain = DOMAIN_IO, 231 }, 232 [MT_NONSHARED_DEVICE] = { 233 .prot_l1 = PMD_TYPE_TABLE, 234 .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV | 235 PMD_SECT_AP_WRITE, 236 .domain = DOMAIN_IO, 237 } 238 }; 239 240 /* 241 * Adjust the PMD section entries according to the CPU in use. 242 */ 243 static void __init build_mem_type_table(void) 244 { 245 struct cachepolicy *cp; 246 unsigned int cr = get_cr(); 247 unsigned int user_pgprot, kern_pgprot; 248 int cpu_arch = cpu_architecture(); 249 int i; 250 251 #if defined(CONFIG_CPU_DCACHE_DISABLE) 252 if (cachepolicy > CPOLICY_BUFFERED) 253 cachepolicy = CPOLICY_BUFFERED; 254 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 255 if (cachepolicy > CPOLICY_WRITETHROUGH) 256 cachepolicy = CPOLICY_WRITETHROUGH; 257 #endif 258 if (cpu_arch < CPU_ARCH_ARMv5) { 259 if (cachepolicy >= CPOLICY_WRITEALLOC) 260 cachepolicy = CPOLICY_WRITEBACK; 261 ecc_mask = 0; 262 } 263 264 /* 265 * Xscale must not have PMD bit 4 set for section mappings. 266 */ 267 if (cpu_is_xscale()) 268 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 269 mem_types[i].prot_sect &= ~PMD_BIT4; 270 271 /* 272 * ARMv5 and lower, excluding Xscale, bit 4 must be set for 273 * page tables. 274 */ 275 if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale()) 276 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 277 if (mem_types[i].prot_l1) 278 mem_types[i].prot_l1 |= PMD_BIT4; 279 280 cp = &cache_policies[cachepolicy]; 281 kern_pgprot = user_pgprot = cp->pte; 282 283 /* 284 * Enable CPU-specific coherency if supported. 285 * (Only available on XSC3 at the moment.) 286 */ 287 if (arch_is_coherent()) { 288 if (cpu_is_xsc3()) { 289 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 290 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 291 } 292 } 293 294 /* 295 * ARMv6 and above have extended page tables. 296 */ 297 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 298 /* 299 * bit 4 becomes XN which we must clear for the 300 * kernel memory mapping. 301 */ 302 mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN; 303 mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN; 304 305 /* 306 * Mark cache clean areas and XIP ROM read only 307 * from SVC mode and no access from userspace. 308 */ 309 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 310 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 311 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 312 313 /* 314 * Mark the device area as "shared device" 315 */ 316 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; 317 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 318 319 #ifdef CONFIG_SMP 320 /* 321 * Mark memory with the "shared" attribute for SMP systems 322 */ 323 user_pgprot |= L_PTE_SHARED; 324 kern_pgprot |= L_PTE_SHARED; 325 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 326 #endif 327 } 328 329 for (i = 0; i < 16; i++) { 330 unsigned long v = pgprot_val(protection_map[i]); 331 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot; 332 protection_map[i] = __pgprot(v); 333 } 334 335 mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot; 336 mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot; 337 338 if (cpu_arch >= CPU_ARCH_ARMv5) { 339 #ifndef CONFIG_SMP 340 /* 341 * Only use write-through for non-SMP systems 342 */ 343 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; 344 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; 345 #endif 346 } else { 347 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); 348 } 349 350 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 351 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 352 L_PTE_DIRTY | L_PTE_WRITE | 353 L_PTE_EXEC | kern_pgprot); 354 355 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 356 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 357 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 358 mem_types[MT_ROM].prot_sect |= cp->pmd; 359 360 switch (cp->pmd) { 361 case PMD_SECT_WT: 362 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 363 break; 364 case PMD_SECT_WB: 365 case PMD_SECT_WBWA: 366 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 367 break; 368 } 369 printk("Memory policy: ECC %sabled, Data cache %s\n", 370 ecc_mask ? "en" : "dis", cp->policy); 371 } 372 373 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 374 375 /* 376 * Create a SECTION PGD between VIRT and PHYS in domain 377 * DOMAIN with protection PROT. This operates on half- 378 * pgdir entry increments. 379 */ 380 static inline void 381 alloc_init_section(unsigned long virt, unsigned long phys, int prot) 382 { 383 pmd_t *pmdp = pmd_off_k(virt); 384 385 if (virt & (1 << 20)) 386 pmdp++; 387 388 *pmdp = __pmd(phys | prot); 389 flush_pmd_entry(pmdp); 390 } 391 392 /* 393 * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT 394 */ 395 static inline void 396 alloc_init_supersection(unsigned long virt, unsigned long phys, int prot) 397 { 398 int i; 399 400 for (i = 0; i < 16; i += 1) { 401 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER); 402 403 virt += (PGDIR_SIZE / 2); 404 } 405 } 406 407 /* 408 * Add a PAGE mapping between VIRT and PHYS in domain 409 * DOMAIN with protection PROT. Note that due to the 410 * way we map the PTEs, we must allocate two PTE_SIZE'd 411 * blocks - one for the Linux pte table, and one for 412 * the hardware pte table. 413 */ 414 static inline void 415 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot) 416 { 417 pmd_t *pmdp = pmd_off_k(virt); 418 pte_t *ptep; 419 420 if (pmd_none(*pmdp)) { 421 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * 422 sizeof(pte_t)); 423 424 __pmd_populate(pmdp, __pa(ptep) | prot_l1); 425 } 426 ptep = pte_offset_kernel(pmdp, virt); 427 428 set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0); 429 } 430 431 /* 432 * Create the page directory entries and any necessary 433 * page tables for the mapping specified by `md'. We 434 * are able to cope here with varying sizes and address 435 * offsets, and we take full advantage of sections and 436 * supersections. 437 */ 438 void __init create_mapping(struct map_desc *md) 439 { 440 unsigned long virt, length; 441 int prot_sect, prot_l1, domain; 442 pgprot_t prot_pte; 443 unsigned long off = (u32)__pfn_to_phys(md->pfn); 444 445 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 446 printk(KERN_WARNING "BUG: not creating mapping for " 447 "0x%08llx at 0x%08lx in user region\n", 448 __pfn_to_phys((u64)md->pfn), md->virtual); 449 return; 450 } 451 452 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 453 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { 454 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " 455 "overlaps vmalloc space\n", 456 __pfn_to_phys((u64)md->pfn), md->virtual); 457 } 458 459 domain = mem_types[md->type].domain; 460 prot_pte = __pgprot(mem_types[md->type].prot_pte); 461 prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain); 462 prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain); 463 464 /* 465 * Catch 36-bit addresses 466 */ 467 if(md->pfn >= 0x100000) { 468 if(domain) { 469 printk(KERN_ERR "MM: invalid domain in supersection " 470 "mapping for 0x%08llx at 0x%08lx\n", 471 __pfn_to_phys((u64)md->pfn), md->virtual); 472 return; 473 } 474 if((md->virtual | md->length | __pfn_to_phys(md->pfn)) 475 & ~SUPERSECTION_MASK) { 476 printk(KERN_ERR "MM: cannot create mapping for " 477 "0x%08llx at 0x%08lx invalid alignment\n", 478 __pfn_to_phys((u64)md->pfn), md->virtual); 479 return; 480 } 481 482 /* 483 * Shift bits [35:32] of address into bits [23:20] of PMD 484 * (See ARMv6 spec). 485 */ 486 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 487 } 488 489 virt = md->virtual; 490 off -= virt; 491 length = md->length; 492 493 if (mem_types[md->type].prot_l1 == 0 && 494 (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) { 495 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " 496 "be mapped using pages, ignoring.\n", 497 __pfn_to_phys(md->pfn), md->virtual); 498 return; 499 } 500 501 while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) { 502 alloc_init_page(virt, virt + off, prot_l1, prot_pte); 503 504 virt += PAGE_SIZE; 505 length -= PAGE_SIZE; 506 } 507 508 /* N.B. ARMv6 supersections are only defined to work with domain 0. 509 * Since domain assignments can in fact be arbitrary, the 510 * 'domain == 0' check below is required to insure that ARMv6 511 * supersections are only allocated for domain 0 regardless 512 * of the actual domain assignments in use. 513 */ 514 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3()) 515 && domain == 0) { 516 /* 517 * Align to supersection boundary if !high pages. 518 * High pages have already been checked for proper 519 * alignment above and they will fail the SUPSERSECTION_MASK 520 * check because of the way the address is encoded into 521 * offset. 522 */ 523 if (md->pfn <= 0x100000) { 524 while ((virt & ~SUPERSECTION_MASK || 525 (virt + off) & ~SUPERSECTION_MASK) && 526 length >= (PGDIR_SIZE / 2)) { 527 alloc_init_section(virt, virt + off, prot_sect); 528 529 virt += (PGDIR_SIZE / 2); 530 length -= (PGDIR_SIZE / 2); 531 } 532 } 533 534 while (length >= SUPERSECTION_SIZE) { 535 alloc_init_supersection(virt, virt + off, prot_sect); 536 537 virt += SUPERSECTION_SIZE; 538 length -= SUPERSECTION_SIZE; 539 } 540 } 541 542 /* 543 * A section mapping covers half a "pgdir" entry. 544 */ 545 while (length >= (PGDIR_SIZE / 2)) { 546 alloc_init_section(virt, virt + off, prot_sect); 547 548 virt += (PGDIR_SIZE / 2); 549 length -= (PGDIR_SIZE / 2); 550 } 551 552 while (length >= PAGE_SIZE) { 553 alloc_init_page(virt, virt + off, prot_l1, prot_pte); 554 555 virt += PAGE_SIZE; 556 length -= PAGE_SIZE; 557 } 558 } 559 560 /* 561 * Create the architecture specific mappings 562 */ 563 void __init iotable_init(struct map_desc *io_desc, int nr) 564 { 565 int i; 566 567 for (i = 0; i < nr; i++) 568 create_mapping(io_desc + i); 569 } 570 571 static inline void prepare_page_table(struct meminfo *mi) 572 { 573 unsigned long addr; 574 575 /* 576 * Clear out all the mappings below the kernel image. 577 */ 578 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) 579 pmd_clear(pmd_off_k(addr)); 580 581 #ifdef CONFIG_XIP_KERNEL 582 /* The XIP kernel is mapped in the module area -- skip over it */ 583 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; 584 #endif 585 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) 586 pmd_clear(pmd_off_k(addr)); 587 588 /* 589 * Clear out all the kernel space mappings, except for the first 590 * memory bank, up to the end of the vmalloc region. 591 */ 592 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); 593 addr < VMALLOC_END; addr += PGDIR_SIZE) 594 pmd_clear(pmd_off_k(addr)); 595 } 596 597 /* 598 * Reserve the various regions of node 0 599 */ 600 void __init reserve_node_zero(pg_data_t *pgdat) 601 { 602 unsigned long res_size = 0; 603 604 /* 605 * Register the kernel text and data with bootmem. 606 * Note that this can only be in node 0. 607 */ 608 #ifdef CONFIG_XIP_KERNEL 609 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start); 610 #else 611 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext); 612 #endif 613 614 /* 615 * Reserve the page tables. These are already in use, 616 * and can only be in node 0. 617 */ 618 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), 619 PTRS_PER_PGD * sizeof(pgd_t)); 620 621 /* 622 * Hmm... This should go elsewhere, but we really really need to 623 * stop things allocating the low memory; ideally we need a better 624 * implementation of GFP_DMA which does not assume that DMA-able 625 * memory starts at zero. 626 */ 627 if (machine_is_integrator() || machine_is_cintegrator()) 628 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 629 630 /* 631 * These should likewise go elsewhere. They pre-reserve the 632 * screen memory region at the start of main system memory. 633 */ 634 if (machine_is_edb7211()) 635 res_size = 0x00020000; 636 if (machine_is_p720t()) 637 res_size = 0x00014000; 638 639 /* H1940 and RX3715 need to reserve this for suspend */ 640 641 if (machine_is_h1940() || machine_is_rx3715()) { 642 reserve_bootmem_node(pgdat, 0x30003000, 0x1000); 643 reserve_bootmem_node(pgdat, 0x30081000, 0x1000); 644 } 645 646 #ifdef CONFIG_SA1111 647 /* 648 * Because of the SA1111 DMA bug, we want to preserve our 649 * precious DMA-able memory... 650 */ 651 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 652 #endif 653 if (res_size) 654 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size); 655 } 656 657 /* 658 * Set up device the mappings. Since we clear out the page tables for all 659 * mappings above VMALLOC_END, we will remove any debug device mappings. 660 * This means you have to be careful how you debug this function, or any 661 * called function. This means you can't use any function or debugging 662 * method which may touch any device, otherwise the kernel _will_ crash. 663 */ 664 static void __init devicemaps_init(struct machine_desc *mdesc) 665 { 666 struct map_desc map; 667 unsigned long addr; 668 void *vectors; 669 670 /* 671 * Allocate the vector page early. 672 */ 673 vectors = alloc_bootmem_low_pages(PAGE_SIZE); 674 BUG_ON(!vectors); 675 676 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) 677 pmd_clear(pmd_off_k(addr)); 678 679 /* 680 * Map the kernel if it is XIP. 681 * It is always first in the modulearea. 682 */ 683 #ifdef CONFIG_XIP_KERNEL 684 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 685 map.virtual = MODULE_START; 686 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 687 map.type = MT_ROM; 688 create_mapping(&map); 689 #endif 690 691 /* 692 * Map the cache flushing regions. 693 */ 694 #ifdef FLUSH_BASE 695 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 696 map.virtual = FLUSH_BASE; 697 map.length = SZ_1M; 698 map.type = MT_CACHECLEAN; 699 create_mapping(&map); 700 #endif 701 #ifdef FLUSH_BASE_MINICACHE 702 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 703 map.virtual = FLUSH_BASE_MINICACHE; 704 map.length = SZ_1M; 705 map.type = MT_MINICLEAN; 706 create_mapping(&map); 707 #endif 708 709 /* 710 * Create a mapping for the machine vectors at the high-vectors 711 * location (0xffff0000). If we aren't using high-vectors, also 712 * create a mapping at the low-vectors virtual address. 713 */ 714 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 715 map.virtual = 0xffff0000; 716 map.length = PAGE_SIZE; 717 map.type = MT_HIGH_VECTORS; 718 create_mapping(&map); 719 720 if (!vectors_high()) { 721 map.virtual = 0; 722 map.type = MT_LOW_VECTORS; 723 create_mapping(&map); 724 } 725 726 /* 727 * Ask the machine support to map in the statically mapped devices. 728 */ 729 if (mdesc->map_io) 730 mdesc->map_io(); 731 732 /* 733 * Finally flush the caches and tlb to ensure that we're in a 734 * consistent state wrt the writebuffer. This also ensures that 735 * any write-allocated cache lines in the vector page are written 736 * back. After this point, we can start to touch devices again. 737 */ 738 local_flush_tlb_all(); 739 flush_cache_all(); 740 } 741 742 /* 743 * paging_init() sets up the page tables, initialises the zone memory 744 * maps, and sets up the zero page, bad page and bad page tables. 745 */ 746 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) 747 { 748 void *zero_page; 749 750 build_mem_type_table(); 751 prepare_page_table(mi); 752 bootmem_init(mi); 753 devicemaps_init(mdesc); 754 755 top_pmd = pmd_off_k(0xffff0000); 756 757 /* 758 * allocate the zero page. Note that we count on this going ok. 759 */ 760 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 761 memzero(zero_page, PAGE_SIZE); 762 empty_zero_page = virt_to_page(zero_page); 763 flush_dcache_page(empty_zero_page); 764 } 765 766 /* 767 * In order to soft-boot, we need to insert a 1:1 mapping in place of 768 * the user-mode pages. This will then ensure that we have predictable 769 * results when turning the mmu off 770 */ 771 void setup_mm_for_reboot(char mode) 772 { 773 unsigned long base_pmdval; 774 pgd_t *pgd; 775 int i; 776 777 if (current->mm && current->mm->pgd) 778 pgd = current->mm->pgd; 779 else 780 pgd = init_mm.pgd; 781 782 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; 783 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) 784 base_pmdval |= PMD_BIT4; 785 786 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { 787 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; 788 pmd_t *pmd; 789 790 pmd = pmd_off(pgd, i << PGDIR_SHIFT); 791 pmd[0] = __pmd(pmdval); 792 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); 793 flush_pmd_entry(pmd); 794 } 795 } 796