1bbe88886SCatalin Marinas/* 2bbe88886SCatalin Marinas * linux/arch/arm/mm/cache-v7.S 3bbe88886SCatalin Marinas * 4bbe88886SCatalin Marinas * Copyright (C) 2001 Deep Blue Solutions Ltd. 5bbe88886SCatalin Marinas * Copyright (C) 2005 ARM Ltd. 6bbe88886SCatalin Marinas * 7bbe88886SCatalin Marinas * This program is free software; you can redistribute it and/or modify 8bbe88886SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 9bbe88886SCatalin Marinas * published by the Free Software Foundation. 10bbe88886SCatalin Marinas * 11bbe88886SCatalin Marinas * This is the "shell" of the ARMv7 processor support. 12bbe88886SCatalin Marinas */ 13bbe88886SCatalin Marinas#include <linux/linkage.h> 14bbe88886SCatalin Marinas#include <linux/init.h> 15bbe88886SCatalin Marinas#include <asm/assembler.h> 16c5102f59SWill Deacon#include <asm/errno.h> 1732cfb1b1SCatalin Marinas#include <asm/unwind.h> 18bbe88886SCatalin Marinas 19bbe88886SCatalin Marinas#include "proc-macros.S" 20bbe88886SCatalin Marinas 21bbe88886SCatalin Marinas/* 2281d11955STony Lindgren * v7_flush_icache_all() 2381d11955STony Lindgren * 2481d11955STony Lindgren * Flush the whole I-cache. 2581d11955STony Lindgren * 2681d11955STony Lindgren * Registers: 2781d11955STony Lindgren * r0 - set to 0 2881d11955STony Lindgren */ 2981d11955STony LindgrenENTRY(v7_flush_icache_all) 3081d11955STony Lindgren mov r0, #0 3181d11955STony Lindgren ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 3281d11955STony Lindgren ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 3381d11955STony Lindgren mov pc, lr 3481d11955STony LindgrenENDPROC(v7_flush_icache_all) 3581d11955STony Lindgren 3681d11955STony Lindgren /* 37031bd879SLorenzo Pieralisi * v7_flush_dcache_louis() 38031bd879SLorenzo Pieralisi * 39031bd879SLorenzo Pieralisi * Flush the D-cache up to the Level of Unification Inner Shareable 40031bd879SLorenzo Pieralisi * 41031bd879SLorenzo Pieralisi * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 42031bd879SLorenzo Pieralisi */ 43031bd879SLorenzo Pieralisi 44031bd879SLorenzo PieralisiENTRY(v7_flush_dcache_louis) 45031bd879SLorenzo Pieralisi dmb @ ensure ordering with previous memory accesses 46031bd879SLorenzo Pieralisi mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 47031bd879SLorenzo Pieralisi ands r3, r0, #0xe00000 @ extract LoUIS from clidr 48031bd879SLorenzo Pieralisi mov r3, r3, lsr #20 @ r3 = LoUIS * 2 49031bd879SLorenzo Pieralisi moveq pc, lr @ return if level == 0 50031bd879SLorenzo Pieralisi mov r10, #0 @ r10 (starting level) = 0 51*3287be8cSLorenzo Pieralisi b flush_levels @ start flushing cache levels 52031bd879SLorenzo PieralisiENDPROC(v7_flush_dcache_louis) 53031bd879SLorenzo Pieralisi 54031bd879SLorenzo Pieralisi/* 55bbe88886SCatalin Marinas * v7_flush_dcache_all() 56bbe88886SCatalin Marinas * 57bbe88886SCatalin Marinas * Flush the whole D-cache. 58bbe88886SCatalin Marinas * 59347c8b70SCatalin Marinas * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) 60bbe88886SCatalin Marinas * 61bbe88886SCatalin Marinas * - mm - mm_struct describing address space 62bbe88886SCatalin Marinas */ 63bbe88886SCatalin MarinasENTRY(v7_flush_dcache_all) 64c30c2f99SCatalin Marinas dmb @ ensure ordering with previous memory accesses 65bbe88886SCatalin Marinas mrc p15, 1, r0, c0, c0, 1 @ read clidr 66bbe88886SCatalin Marinas ands r3, r0, #0x7000000 @ extract loc from clidr 67bbe88886SCatalin Marinas mov r3, r3, lsr #23 @ left align loc bit field 68bbe88886SCatalin Marinas beq finished @ if loc is 0, then no need to clean 69bbe88886SCatalin Marinas mov r10, #0 @ start clean at cache level 0 70*3287be8cSLorenzo Pieralisiflush_levels: 71bbe88886SCatalin Marinas add r2, r10, r10, lsr #1 @ work out 3x current cache level 72bbe88886SCatalin Marinas mov r1, r0, lsr r2 @ extract cache type bits from clidr 73bbe88886SCatalin Marinas and r1, r1, #7 @ mask of the bits for current cache only 74bbe88886SCatalin Marinas cmp r1, #2 @ see what cache we have at this level 75bbe88886SCatalin Marinas blt skip @ skip if no cache, or just i-cache 76b46c0f74SStephen Boyd#ifdef CONFIG_PREEMPT 778e43a905SRabin Vincent save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic 78b46c0f74SStephen Boyd#endif 79bbe88886SCatalin Marinas mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 80bbe88886SCatalin Marinas isb @ isb to sych the new cssr&csidr 81bbe88886SCatalin Marinas mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 82b46c0f74SStephen Boyd#ifdef CONFIG_PREEMPT 83b46c0f74SStephen Boyd restore_irqs_notrace r9 84b46c0f74SStephen Boyd#endif 85bbe88886SCatalin Marinas and r2, r1, #7 @ extract the length of the cache lines 86bbe88886SCatalin Marinas add r2, r2, #4 @ add 4 (line length offset) 87bbe88886SCatalin Marinas ldr r4, =0x3ff 88bbe88886SCatalin Marinas ands r4, r4, r1, lsr #3 @ find maximum number on the way size 89bbe88886SCatalin Marinas clz r5, r4 @ find bit position of way size increment 90bbe88886SCatalin Marinas ldr r7, =0x7fff 91bbe88886SCatalin Marinas ands r7, r7, r1, lsr #13 @ extract max number of the index size 92*3287be8cSLorenzo Pieralisiloop1: 93bbe88886SCatalin Marinas mov r9, r4 @ create working copy of max way size 94*3287be8cSLorenzo Pieralisiloop2: 95347c8b70SCatalin Marinas ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 96347c8b70SCatalin Marinas THUMB( lsl r6, r9, r5 ) 97347c8b70SCatalin Marinas THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 98347c8b70SCatalin Marinas ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 99347c8b70SCatalin Marinas THUMB( lsl r6, r7, r2 ) 100347c8b70SCatalin Marinas THUMB( orr r11, r11, r6 ) @ factor index number into r11 101bbe88886SCatalin Marinas mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 102bbe88886SCatalin Marinas subs r9, r9, #1 @ decrement the way 103bbe88886SCatalin Marinas bge loop2 104*3287be8cSLorenzo Pieralisi subs r7, r7, #1 @ decrement the index 105*3287be8cSLorenzo Pieralisi bge loop1 106bbe88886SCatalin Marinasskip: 107bbe88886SCatalin Marinas add r10, r10, #2 @ increment cache number 108bbe88886SCatalin Marinas cmp r3, r10 109*3287be8cSLorenzo Pieralisi bgt flush_levels 110bbe88886SCatalin Marinasfinished: 111bbe88886SCatalin Marinas mov r10, #0 @ swith back to cache level 0 112bbe88886SCatalin Marinas mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 113c30c2f99SCatalin Marinas dsb 114bbe88886SCatalin Marinas isb 115bbe88886SCatalin Marinas mov pc, lr 11693ed3970SCatalin MarinasENDPROC(v7_flush_dcache_all) 117bbe88886SCatalin Marinas 118bbe88886SCatalin Marinas/* 119bbe88886SCatalin Marinas * v7_flush_cache_all() 120bbe88886SCatalin Marinas * 121bbe88886SCatalin Marinas * Flush the entire cache system. 122bbe88886SCatalin Marinas * The data cache flush is now achieved using atomic clean / invalidates 123bbe88886SCatalin Marinas * working outwards from L1 cache. This is done using Set/Way based cache 12425985edcSLucas De Marchi * maintenance instructions. 125bbe88886SCatalin Marinas * The instruction cache can still be invalidated back to the point of 126bbe88886SCatalin Marinas * unification in a single instruction. 127bbe88886SCatalin Marinas * 128bbe88886SCatalin Marinas */ 129bbe88886SCatalin MarinasENTRY(v7_flush_kern_cache_all) 130347c8b70SCatalin Marinas ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 131347c8b70SCatalin Marinas THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 132bbe88886SCatalin Marinas bl v7_flush_dcache_all 133bbe88886SCatalin Marinas mov r0, #0 134f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 135f00ec48fSRussell King ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 136347c8b70SCatalin Marinas ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 137347c8b70SCatalin Marinas THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 138bbe88886SCatalin Marinas mov pc, lr 13993ed3970SCatalin MarinasENDPROC(v7_flush_kern_cache_all) 140bbe88886SCatalin Marinas 141bbe88886SCatalin Marinas /* 142031bd879SLorenzo Pieralisi * v7_flush_kern_cache_louis(void) 143031bd879SLorenzo Pieralisi * 144031bd879SLorenzo Pieralisi * Flush the data cache up to Level of Unification Inner Shareable. 145031bd879SLorenzo Pieralisi * Invalidate the I-cache to the point of unification. 146031bd879SLorenzo Pieralisi */ 147031bd879SLorenzo PieralisiENTRY(v7_flush_kern_cache_louis) 148031bd879SLorenzo Pieralisi ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) 149031bd879SLorenzo Pieralisi THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 150031bd879SLorenzo Pieralisi bl v7_flush_dcache_louis 151031bd879SLorenzo Pieralisi mov r0, #0 152031bd879SLorenzo Pieralisi ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 153031bd879SLorenzo Pieralisi ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 154031bd879SLorenzo Pieralisi ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 155031bd879SLorenzo Pieralisi THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 156031bd879SLorenzo Pieralisi mov pc, lr 157031bd879SLorenzo PieralisiENDPROC(v7_flush_kern_cache_louis) 158031bd879SLorenzo Pieralisi 159031bd879SLorenzo Pieralisi/* 160bbe88886SCatalin Marinas * v7_flush_cache_all() 161bbe88886SCatalin Marinas * 162bbe88886SCatalin Marinas * Flush all TLB entries in a particular address space 163bbe88886SCatalin Marinas * 164bbe88886SCatalin Marinas * - mm - mm_struct describing address space 165bbe88886SCatalin Marinas */ 166bbe88886SCatalin MarinasENTRY(v7_flush_user_cache_all) 167bbe88886SCatalin Marinas /*FALLTHROUGH*/ 168bbe88886SCatalin Marinas 169bbe88886SCatalin Marinas/* 170bbe88886SCatalin Marinas * v7_flush_cache_range(start, end, flags) 171bbe88886SCatalin Marinas * 172bbe88886SCatalin Marinas * Flush a range of TLB entries in the specified address space. 173bbe88886SCatalin Marinas * 174bbe88886SCatalin Marinas * - start - start address (may not be aligned) 175bbe88886SCatalin Marinas * - end - end address (exclusive, may not be aligned) 176bbe88886SCatalin Marinas * - flags - vm_area_struct flags describing address space 177bbe88886SCatalin Marinas * 178bbe88886SCatalin Marinas * It is assumed that: 179bbe88886SCatalin Marinas * - we have a VIPT cache. 180bbe88886SCatalin Marinas */ 181bbe88886SCatalin MarinasENTRY(v7_flush_user_cache_range) 182bbe88886SCatalin Marinas mov pc, lr 18393ed3970SCatalin MarinasENDPROC(v7_flush_user_cache_all) 18493ed3970SCatalin MarinasENDPROC(v7_flush_user_cache_range) 185bbe88886SCatalin Marinas 186bbe88886SCatalin Marinas/* 187bbe88886SCatalin Marinas * v7_coherent_kern_range(start,end) 188bbe88886SCatalin Marinas * 189bbe88886SCatalin Marinas * Ensure that the I and D caches are coherent within specified 190bbe88886SCatalin Marinas * region. This is typically used when code has been written to 191bbe88886SCatalin Marinas * a memory region, and will be executed. 192bbe88886SCatalin Marinas * 193bbe88886SCatalin Marinas * - start - virtual start address of region 194bbe88886SCatalin Marinas * - end - virtual end address of region 195bbe88886SCatalin Marinas * 196bbe88886SCatalin Marinas * It is assumed that: 197bbe88886SCatalin Marinas * - the Icache does not read data from the write buffer 198bbe88886SCatalin Marinas */ 199bbe88886SCatalin MarinasENTRY(v7_coherent_kern_range) 200bbe88886SCatalin Marinas /* FALLTHROUGH */ 201bbe88886SCatalin Marinas 202bbe88886SCatalin Marinas/* 203bbe88886SCatalin Marinas * v7_coherent_user_range(start,end) 204bbe88886SCatalin Marinas * 205bbe88886SCatalin Marinas * Ensure that the I and D caches are coherent within specified 206bbe88886SCatalin Marinas * region. This is typically used when code has been written to 207bbe88886SCatalin Marinas * a memory region, and will be executed. 208bbe88886SCatalin Marinas * 209bbe88886SCatalin Marinas * - start - virtual start address of region 210bbe88886SCatalin Marinas * - end - virtual end address of region 211bbe88886SCatalin Marinas * 212bbe88886SCatalin Marinas * It is assumed that: 213bbe88886SCatalin Marinas * - the Icache does not read data from the write buffer 214bbe88886SCatalin Marinas */ 215bbe88886SCatalin MarinasENTRY(v7_coherent_user_range) 21632cfb1b1SCatalin Marinas UNWIND(.fnstart ) 217bbe88886SCatalin Marinas dcache_line_size r2, r3 218bbe88886SCatalin Marinas sub r3, r2, #1 219da30e0acSCatalin Marinas bic r12, r0, r3 220f630c1bdSWill Deacon#ifdef CONFIG_ARM_ERRATA_764369 221f630c1bdSWill Deacon ALT_SMP(W(dsb)) 222f630c1bdSWill Deacon ALT_UP(W(nop)) 223f630c1bdSWill Deacon#endif 22432cfb1b1SCatalin Marinas1: 225da30e0acSCatalin Marinas USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 226da30e0acSCatalin Marinas add r12, r12, r2 227da30e0acSCatalin Marinas cmp r12, r1 228bbe88886SCatalin Marinas blo 1b 229da30e0acSCatalin Marinas dsb 230da30e0acSCatalin Marinas icache_line_size r2, r3 231da30e0acSCatalin Marinas sub r3, r2, #1 232da30e0acSCatalin Marinas bic r12, r0, r3 233da30e0acSCatalin Marinas2: 234da30e0acSCatalin Marinas USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 235da30e0acSCatalin Marinas add r12, r12, r2 236da30e0acSCatalin Marinas cmp r12, r1 237da30e0acSCatalin Marinas blo 2b 238bbe88886SCatalin Marinas mov r0, #0 239f00ec48fSRussell King ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 240f00ec48fSRussell King ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 241bbe88886SCatalin Marinas dsb 242bbe88886SCatalin Marinas isb 243bbe88886SCatalin Marinas mov pc, lr 24432cfb1b1SCatalin Marinas 24532cfb1b1SCatalin Marinas/* 24632cfb1b1SCatalin Marinas * Fault handling for the cache operation above. If the virtual address in r0 247c5102f59SWill Deacon * isn't mapped, fail with -EFAULT. 24832cfb1b1SCatalin Marinas */ 24932cfb1b1SCatalin Marinas9001: 250c5102f59SWill Deacon mov r0, #-EFAULT 251c5102f59SWill Deacon mov pc, lr 25232cfb1b1SCatalin Marinas UNWIND(.fnend ) 25393ed3970SCatalin MarinasENDPROC(v7_coherent_kern_range) 25493ed3970SCatalin MarinasENDPROC(v7_coherent_user_range) 255bbe88886SCatalin Marinas 256bbe88886SCatalin Marinas/* 2572c9b9c84SRussell King * v7_flush_kern_dcache_area(void *addr, size_t size) 258bbe88886SCatalin Marinas * 259bbe88886SCatalin Marinas * Ensure that the data held in the page kaddr is written back 260bbe88886SCatalin Marinas * to the page in question. 261bbe88886SCatalin Marinas * 2622c9b9c84SRussell King * - addr - kernel address 2632c9b9c84SRussell King * - size - region size 264bbe88886SCatalin Marinas */ 2652c9b9c84SRussell KingENTRY(v7_flush_kern_dcache_area) 266bbe88886SCatalin Marinas dcache_line_size r2, r3 2672c9b9c84SRussell King add r1, r0, r1 268a248b13bSWill Deacon sub r3, r2, #1 269a248b13bSWill Deacon bic r0, r0, r3 270f630c1bdSWill Deacon#ifdef CONFIG_ARM_ERRATA_764369 271f630c1bdSWill Deacon ALT_SMP(W(dsb)) 272f630c1bdSWill Deacon ALT_UP(W(nop)) 273f630c1bdSWill Deacon#endif 274bbe88886SCatalin Marinas1: 275bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 276bbe88886SCatalin Marinas add r0, r0, r2 277bbe88886SCatalin Marinas cmp r0, r1 278bbe88886SCatalin Marinas blo 1b 279bbe88886SCatalin Marinas dsb 280bbe88886SCatalin Marinas mov pc, lr 2812c9b9c84SRussell KingENDPROC(v7_flush_kern_dcache_area) 282bbe88886SCatalin Marinas 283bbe88886SCatalin Marinas/* 284bbe88886SCatalin Marinas * v7_dma_inv_range(start,end) 285bbe88886SCatalin Marinas * 286bbe88886SCatalin Marinas * Invalidate the data cache within the specified region; we will 287bbe88886SCatalin Marinas * be performing a DMA operation in this region and we want to 288bbe88886SCatalin Marinas * purge old data in the cache. 289bbe88886SCatalin Marinas * 290bbe88886SCatalin Marinas * - start - virtual start address of region 291bbe88886SCatalin Marinas * - end - virtual end address of region 292bbe88886SCatalin Marinas */ 293702b94bfSRussell Kingv7_dma_inv_range: 294bbe88886SCatalin Marinas dcache_line_size r2, r3 295bbe88886SCatalin Marinas sub r3, r2, #1 296bbe88886SCatalin Marinas tst r0, r3 297bbe88886SCatalin Marinas bic r0, r0, r3 298f630c1bdSWill Deacon#ifdef CONFIG_ARM_ERRATA_764369 299f630c1bdSWill Deacon ALT_SMP(W(dsb)) 300f630c1bdSWill Deacon ALT_UP(W(nop)) 301f630c1bdSWill Deacon#endif 302bbe88886SCatalin Marinas mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 303bbe88886SCatalin Marinas 304bbe88886SCatalin Marinas tst r1, r3 305bbe88886SCatalin Marinas bic r1, r1, r3 306bbe88886SCatalin Marinas mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 307bbe88886SCatalin Marinas1: 308bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 309bbe88886SCatalin Marinas add r0, r0, r2 310bbe88886SCatalin Marinas cmp r0, r1 311bbe88886SCatalin Marinas blo 1b 312bbe88886SCatalin Marinas dsb 313bbe88886SCatalin Marinas mov pc, lr 31493ed3970SCatalin MarinasENDPROC(v7_dma_inv_range) 315bbe88886SCatalin Marinas 316bbe88886SCatalin Marinas/* 317bbe88886SCatalin Marinas * v7_dma_clean_range(start,end) 318bbe88886SCatalin Marinas * - start - virtual start address of region 319bbe88886SCatalin Marinas * - end - virtual end address of region 320bbe88886SCatalin Marinas */ 321702b94bfSRussell Kingv7_dma_clean_range: 322bbe88886SCatalin Marinas dcache_line_size r2, r3 323bbe88886SCatalin Marinas sub r3, r2, #1 324bbe88886SCatalin Marinas bic r0, r0, r3 325f630c1bdSWill Deacon#ifdef CONFIG_ARM_ERRATA_764369 326f630c1bdSWill Deacon ALT_SMP(W(dsb)) 327f630c1bdSWill Deacon ALT_UP(W(nop)) 328f630c1bdSWill Deacon#endif 329bbe88886SCatalin Marinas1: 330bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 331bbe88886SCatalin Marinas add r0, r0, r2 332bbe88886SCatalin Marinas cmp r0, r1 333bbe88886SCatalin Marinas blo 1b 334bbe88886SCatalin Marinas dsb 335bbe88886SCatalin Marinas mov pc, lr 33693ed3970SCatalin MarinasENDPROC(v7_dma_clean_range) 337bbe88886SCatalin Marinas 338bbe88886SCatalin Marinas/* 339bbe88886SCatalin Marinas * v7_dma_flush_range(start,end) 340bbe88886SCatalin Marinas * - start - virtual start address of region 341bbe88886SCatalin Marinas * - end - virtual end address of region 342bbe88886SCatalin Marinas */ 343bbe88886SCatalin MarinasENTRY(v7_dma_flush_range) 344bbe88886SCatalin Marinas dcache_line_size r2, r3 345bbe88886SCatalin Marinas sub r3, r2, #1 346bbe88886SCatalin Marinas bic r0, r0, r3 347f630c1bdSWill Deacon#ifdef CONFIG_ARM_ERRATA_764369 348f630c1bdSWill Deacon ALT_SMP(W(dsb)) 349f630c1bdSWill Deacon ALT_UP(W(nop)) 350f630c1bdSWill Deacon#endif 351bbe88886SCatalin Marinas1: 352bbe88886SCatalin Marinas mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 353bbe88886SCatalin Marinas add r0, r0, r2 354bbe88886SCatalin Marinas cmp r0, r1 355bbe88886SCatalin Marinas blo 1b 356bbe88886SCatalin Marinas dsb 357bbe88886SCatalin Marinas mov pc, lr 35893ed3970SCatalin MarinasENDPROC(v7_dma_flush_range) 359bbe88886SCatalin Marinas 360a9c9147eSRussell King/* 361a9c9147eSRussell King * dma_map_area(start, size, dir) 362a9c9147eSRussell King * - start - kernel virtual start address 363a9c9147eSRussell King * - size - size of region 364a9c9147eSRussell King * - dir - DMA direction 365a9c9147eSRussell King */ 366a9c9147eSRussell KingENTRY(v7_dma_map_area) 367a9c9147eSRussell King add r1, r1, r0 3682ffe2da3SRussell King teq r2, #DMA_FROM_DEVICE 3692ffe2da3SRussell King beq v7_dma_inv_range 3702ffe2da3SRussell King b v7_dma_clean_range 371a9c9147eSRussell KingENDPROC(v7_dma_map_area) 372a9c9147eSRussell King 373a9c9147eSRussell King/* 374a9c9147eSRussell King * dma_unmap_area(start, size, dir) 375a9c9147eSRussell King * - start - kernel virtual start address 376a9c9147eSRussell King * - size - size of region 377a9c9147eSRussell King * - dir - DMA direction 378a9c9147eSRussell King */ 379a9c9147eSRussell KingENTRY(v7_dma_unmap_area) 3802ffe2da3SRussell King add r1, r1, r0 3812ffe2da3SRussell King teq r2, #DMA_TO_DEVICE 3822ffe2da3SRussell King bne v7_dma_inv_range 383a9c9147eSRussell King mov pc, lr 384a9c9147eSRussell KingENDPROC(v7_dma_unmap_area) 385a9c9147eSRussell King 386bbe88886SCatalin Marinas __INITDATA 387bbe88886SCatalin Marinas 388455a01ecSDave Martin @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) 389455a01ecSDave Martin define_cache_functions v7 390