1comment "Processor Type" 2 3config CPU_32 4 bool 5 default y 6 7# Select CPU types depending on the architecture selected. This selects 8# which CPUs we support in the kernel image, and the compiler instruction 9# optimiser behaviour. 10 11# ARM610 12config CPU_ARM610 13 bool "Support ARM610 processor" if ARCH_RPC 14 select CPU_32v3 15 select CPU_CACHE_V3 16 select CPU_CACHE_VIVT 17 select CPU_CP15_MMU 18 select CPU_COPY_V3 if MMU 19 select CPU_TLB_V3 if MMU 20 select CPU_PABRT_NOIFAR 21 help 22 The ARM610 is the successor to the ARM3 processor 23 and was produced by VLSI Technology Inc. 24 25 Say Y if you want support for the ARM610 processor. 26 Otherwise, say N. 27 28# ARM7TDMI 29config CPU_ARM7TDMI 30 bool "Support ARM7TDMI processor" 31 depends on !MMU 32 select CPU_32v4T 33 select CPU_ABRT_LV4T 34 select CPU_PABRT_NOIFAR 35 select CPU_CACHE_V4 36 help 37 A 32-bit RISC microprocessor based on the ARM7 processor core 38 which has no memory control unit and cache. 39 40 Say Y if you want support for the ARM7TDMI processor. 41 Otherwise, say N. 42 43# ARM710 44config CPU_ARM710 45 bool "Support ARM710 processor" if ARCH_RPC 46 select CPU_32v3 47 select CPU_CACHE_V3 48 select CPU_CACHE_VIVT 49 select CPU_CP15_MMU 50 select CPU_COPY_V3 if MMU 51 select CPU_TLB_V3 if MMU 52 select CPU_PABRT_NOIFAR 53 help 54 A 32-bit RISC microprocessor based on the ARM7 processor core 55 designed by Advanced RISC Machines Ltd. The ARM710 is the 56 successor to the ARM610 processor. It was released in 57 July 1994 by VLSI Technology Inc. 58 59 Say Y if you want support for the ARM710 processor. 60 Otherwise, say N. 61 62# ARM720T 63config CPU_ARM720T 64 bool "Support ARM720T processor" if ARCH_INTEGRATOR 65 select CPU_32v4T 66 select CPU_ABRT_LV4T 67 select CPU_PABRT_NOIFAR 68 select CPU_CACHE_V4 69 select CPU_CACHE_VIVT 70 select CPU_CP15_MMU 71 select CPU_COPY_V4WT if MMU 72 select CPU_TLB_V4WT if MMU 73 help 74 A 32-bit RISC processor with 8kByte Cache, Write Buffer and 75 MMU built around an ARM7TDMI core. 76 77 Say Y if you want support for the ARM720T processor. 78 Otherwise, say N. 79 80# ARM740T 81config CPU_ARM740T 82 bool "Support ARM740T processor" if ARCH_INTEGRATOR 83 depends on !MMU 84 select CPU_32v4T 85 select CPU_ABRT_LV4T 86 select CPU_PABRT_NOIFAR 87 select CPU_CACHE_V3 # although the core is v4t 88 select CPU_CP15_MPU 89 help 90 A 32-bit RISC processor with 8KB cache or 4KB variants, 91 write buffer and MPU(Protection Unit) built around 92 an ARM7TDMI core. 93 94 Say Y if you want support for the ARM740T processor. 95 Otherwise, say N. 96 97# ARM9TDMI 98config CPU_ARM9TDMI 99 bool "Support ARM9TDMI processor" 100 depends on !MMU 101 select CPU_32v4T 102 select CPU_ABRT_NOMMU 103 select CPU_PABRT_NOIFAR 104 select CPU_CACHE_V4 105 help 106 A 32-bit RISC microprocessor based on the ARM9 processor core 107 which has no memory control unit and cache. 108 109 Say Y if you want support for the ARM9TDMI processor. 110 Otherwise, say N. 111 112# ARM920T 113config CPU_ARM920T 114 bool "Support ARM920T processor" if ARCH_INTEGRATOR 115 select CPU_32v4T 116 select CPU_ABRT_EV4T 117 select CPU_PABRT_NOIFAR 118 select CPU_CACHE_V4WT 119 select CPU_CACHE_VIVT 120 select CPU_CP15_MMU 121 select CPU_COPY_V4WB if MMU 122 select CPU_TLB_V4WBI if MMU 123 help 124 The ARM920T is licensed to be produced by numerous vendors, 125 and is used in the Maverick EP9312 and the Samsung S3C2410. 126 127 More information on the Maverick EP9312 at 128 <http://linuxdevices.com/products/PD2382866068.html>. 129 130 Say Y if you want support for the ARM920T processor. 131 Otherwise, say N. 132 133# ARM922T 134config CPU_ARM922T 135 bool "Support ARM922T processor" if ARCH_INTEGRATOR 136 select CPU_32v4T 137 select CPU_ABRT_EV4T 138 select CPU_PABRT_NOIFAR 139 select CPU_CACHE_V4WT 140 select CPU_CACHE_VIVT 141 select CPU_CP15_MMU 142 select CPU_COPY_V4WB if MMU 143 select CPU_TLB_V4WBI if MMU 144 help 145 The ARM922T is a version of the ARM920T, but with smaller 146 instruction and data caches. It is used in Altera's 147 Excalibur XA device family and Micrel's KS8695 Centaur. 148 149 Say Y if you want support for the ARM922T processor. 150 Otherwise, say N. 151 152# ARM925T 153config CPU_ARM925T 154 bool "Support ARM925T processor" if ARCH_OMAP1 155 select CPU_32v4T 156 select CPU_ABRT_EV4T 157 select CPU_PABRT_NOIFAR 158 select CPU_CACHE_V4WT 159 select CPU_CACHE_VIVT 160 select CPU_CP15_MMU 161 select CPU_COPY_V4WB if MMU 162 select CPU_TLB_V4WBI if MMU 163 help 164 The ARM925T is a mix between the ARM920T and ARM926T, but with 165 different instruction and data caches. It is used in TI's OMAP 166 device family. 167 168 Say Y if you want support for the ARM925T processor. 169 Otherwise, say N. 170 171# ARM926T 172config CPU_ARM926T 173 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 174 select CPU_32v5 175 select CPU_ABRT_EV5TJ 176 select CPU_PABRT_NOIFAR 177 select CPU_CACHE_VIVT 178 select CPU_CP15_MMU 179 select CPU_COPY_V4WB if MMU 180 select CPU_TLB_V4WBI if MMU 181 help 182 This is a variant of the ARM920. It has slightly different 183 instruction sequences for cache and TLB operations. Curiously, 184 there is no documentation on it at the ARM corporate website. 185 186 Say Y if you want support for the ARM926T processor. 187 Otherwise, say N. 188 189# ARM940T 190config CPU_ARM940T 191 bool "Support ARM940T processor" if ARCH_INTEGRATOR 192 depends on !MMU 193 select CPU_32v4T 194 select CPU_ABRT_NOMMU 195 select CPU_PABRT_NOIFAR 196 select CPU_CACHE_VIVT 197 select CPU_CP15_MPU 198 help 199 ARM940T is a member of the ARM9TDMI family of general- 200 purpose microprocessors with MPU and separate 4KB 201 instruction and 4KB data cases, each with a 4-word line 202 length. 203 204 Say Y if you want support for the ARM940T processor. 205 Otherwise, say N. 206 207# ARM946E-S 208config CPU_ARM946E 209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR 210 depends on !MMU 211 select CPU_32v5 212 select CPU_ABRT_NOMMU 213 select CPU_PABRT_NOIFAR 214 select CPU_CACHE_VIVT 215 select CPU_CP15_MPU 216 help 217 ARM946E-S is a member of the ARM9E-S family of high- 218 performance, 32-bit system-on-chip processor solutions. 219 The TCM and ARMv5TE 32-bit instruction set is supported. 220 221 Say Y if you want support for the ARM946E-S processor. 222 Otherwise, say N. 223 224# ARM1020 - needs validating 225config CPU_ARM1020 226 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR 227 select CPU_32v5 228 select CPU_ABRT_EV4T 229 select CPU_PABRT_NOIFAR 230 select CPU_CACHE_V4WT 231 select CPU_CACHE_VIVT 232 select CPU_CP15_MMU 233 select CPU_COPY_V4WB if MMU 234 select CPU_TLB_V4WBI if MMU 235 help 236 The ARM1020 is the 32K cached version of the ARM10 processor, 237 with an addition of a floating-point unit. 238 239 Say Y if you want support for the ARM1020 processor. 240 Otherwise, say N. 241 242# ARM1020E - needs validating 243config CPU_ARM1020E 244 bool "Support ARM1020E processor" if ARCH_INTEGRATOR 245 select CPU_32v5 246 select CPU_ABRT_EV4T 247 select CPU_PABRT_NOIFAR 248 select CPU_CACHE_V4WT 249 select CPU_CACHE_VIVT 250 select CPU_CP15_MMU 251 select CPU_COPY_V4WB if MMU 252 select CPU_TLB_V4WBI if MMU 253 depends on n 254 255# ARM1022E 256config CPU_ARM1022 257 bool "Support ARM1022E processor" if ARCH_INTEGRATOR 258 select CPU_32v5 259 select CPU_ABRT_EV4T 260 select CPU_PABRT_NOIFAR 261 select CPU_CACHE_VIVT 262 select CPU_CP15_MMU 263 select CPU_COPY_V4WB if MMU # can probably do better 264 select CPU_TLB_V4WBI if MMU 265 help 266 The ARM1022E is an implementation of the ARMv5TE architecture 267 based upon the ARM10 integer core with a 16KiB L1 Harvard cache, 268 embedded trace macrocell, and a floating-point unit. 269 270 Say Y if you want support for the ARM1022E processor. 271 Otherwise, say N. 272 273# ARM1026EJ-S 274config CPU_ARM1026 275 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR 276 select CPU_32v5 277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 278 select CPU_PABRT_NOIFAR 279 select CPU_CACHE_VIVT 280 select CPU_CP15_MMU 281 select CPU_COPY_V4WB if MMU # can probably do better 282 select CPU_TLB_V4WBI if MMU 283 help 284 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture 285 based upon the ARM10 integer core. 286 287 Say Y if you want support for the ARM1026EJ-S processor. 288 Otherwise, say N. 289 290# SA110 291config CPU_SA110 292 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC 293 select CPU_32v3 if ARCH_RPC 294 select CPU_32v4 if !ARCH_RPC 295 select CPU_ABRT_EV4 296 select CPU_PABRT_NOIFAR 297 select CPU_CACHE_V4WB 298 select CPU_CACHE_VIVT 299 select CPU_CP15_MMU 300 select CPU_COPY_V4WB if MMU 301 select CPU_TLB_V4WB if MMU 302 help 303 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and 304 is available at five speeds ranging from 100 MHz to 233 MHz. 305 More information is available at 306 <http://developer.intel.com/design/strong/sa110.htm>. 307 308 Say Y if you want support for the SA-110 processor. 309 Otherwise, say N. 310 311# SA1100 312config CPU_SA1100 313 bool 314 select CPU_32v4 315 select CPU_ABRT_EV4 316 select CPU_PABRT_NOIFAR 317 select CPU_CACHE_V4WB 318 select CPU_CACHE_VIVT 319 select CPU_CP15_MMU 320 select CPU_TLB_V4WB if MMU 321 322# XScale 323config CPU_XSCALE 324 bool 325 select CPU_32v5 326 select CPU_ABRT_EV5T 327 select CPU_PABRT_NOIFAR 328 select CPU_CACHE_VIVT 329 select CPU_CP15_MMU 330 select CPU_TLB_V4WBI if MMU 331 332# XScale Core Version 3 333config CPU_XSC3 334 bool 335 select CPU_32v5 336 select CPU_ABRT_EV5T 337 select CPU_PABRT_NOIFAR 338 select CPU_CACHE_VIVT 339 select CPU_CP15_MMU 340 select CPU_TLB_V4WBI if MMU 341 select IO_36 342 343# Marvell PJ1 (Mohawk) 344config CPU_MOHAWK 345 bool 346 select CPU_32v5 347 select CPU_ABRT_EV5T 348 select CPU_PABRT_NOIFAR 349 select CPU_CACHE_VIVT 350 select CPU_CP15_MMU 351 select CPU_TLB_V4WBI if MMU 352 select CPU_COPY_V4WB if MMU 353 354# Feroceon 355config CPU_FEROCEON 356 bool 357 select CPU_32v5 358 select CPU_ABRT_EV5T 359 select CPU_PABRT_NOIFAR 360 select CPU_CACHE_VIVT 361 select CPU_CP15_MMU 362 select CPU_COPY_FEROCEON if MMU 363 select CPU_TLB_FEROCEON if MMU 364 365config CPU_FEROCEON_OLD_ID 366 bool "Accept early Feroceon cores with an ARM926 ID" 367 depends on CPU_FEROCEON && !CPU_ARM926T 368 default y 369 help 370 This enables the usage of some old Feroceon cores 371 for which the CPU ID is equal to the ARM926 ID. 372 Relevant for Feroceon-1850 and early Feroceon-2850. 373 374# ARMv6 375config CPU_V6 376 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 377 select CPU_32v6 378 select CPU_ABRT_EV6 379 select CPU_PABRT_NOIFAR 380 select CPU_CACHE_V6 381 select CPU_CACHE_VIPT 382 select CPU_CP15_MMU 383 select CPU_HAS_ASID if MMU 384 select CPU_COPY_V6 if MMU 385 select CPU_TLB_V6 if MMU 386 387# ARMv6k 388config CPU_32v6K 389 bool "Support ARM V6K processor extensions" if !SMP 390 depends on CPU_V6 391 default y if SMP && !ARCH_MX3 392 help 393 Say Y here if your ARMv6 processor supports the 'K' extension. 394 This enables the kernel to use some instructions not present 395 on previous processors, and as such a kernel build with this 396 enabled will not boot on processors with do not support these 397 instructions. 398 399# ARMv7 400config CPU_V7 401 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB 402 select CPU_32v6K 403 select CPU_32v7 404 select CPU_ABRT_EV7 405 select CPU_PABRT_IFAR 406 select CPU_CACHE_V7 407 select CPU_CACHE_VIPT 408 select CPU_CP15_MMU 409 select CPU_HAS_ASID if MMU 410 select CPU_COPY_V6 if MMU 411 select CPU_TLB_V7 if MMU 412 413# Figure out what processor architecture version we should be using. 414# This defines the compiler instruction set which depends on the machine type. 415config CPU_32v3 416 bool 417 select TLS_REG_EMUL if SMP || !MMU 418 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 419 420config CPU_32v4 421 bool 422 select TLS_REG_EMUL if SMP || !MMU 423 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 424 425config CPU_32v4T 426 bool 427 select TLS_REG_EMUL if SMP || !MMU 428 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 429 430config CPU_32v5 431 bool 432 select TLS_REG_EMUL if SMP || !MMU 433 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP 434 435config CPU_32v6 436 bool 437 select TLS_REG_EMUL if !CPU_32v6K && !MMU 438 439config CPU_32v7 440 bool 441 442# The abort model 443config CPU_ABRT_NOMMU 444 bool 445 446config CPU_ABRT_EV4 447 bool 448 449config CPU_ABRT_EV4T 450 bool 451 452config CPU_ABRT_LV4T 453 bool 454 455config CPU_ABRT_EV5T 456 bool 457 458config CPU_ABRT_EV5TJ 459 bool 460 461config CPU_ABRT_EV6 462 bool 463 464config CPU_ABRT_EV7 465 bool 466 467config CPU_PABRT_IFAR 468 bool 469 470config CPU_PABRT_NOIFAR 471 bool 472 473# The cache model 474config CPU_CACHE_V3 475 bool 476 477config CPU_CACHE_V4 478 bool 479 480config CPU_CACHE_V4WT 481 bool 482 483config CPU_CACHE_V4WB 484 bool 485 486config CPU_CACHE_V6 487 bool 488 489config CPU_CACHE_V7 490 bool 491 492config CPU_CACHE_VIVT 493 bool 494 495config CPU_CACHE_VIPT 496 bool 497 498if MMU 499# The copy-page model 500config CPU_COPY_V3 501 bool 502 503config CPU_COPY_V4WT 504 bool 505 506config CPU_COPY_V4WB 507 bool 508 509config CPU_COPY_FEROCEON 510 bool 511 512config CPU_COPY_V6 513 bool 514 515# This selects the TLB model 516config CPU_TLB_V3 517 bool 518 help 519 ARM Architecture Version 3 TLB. 520 521config CPU_TLB_V4WT 522 bool 523 help 524 ARM Architecture Version 4 TLB with writethrough cache. 525 526config CPU_TLB_V4WB 527 bool 528 help 529 ARM Architecture Version 4 TLB with writeback cache. 530 531config CPU_TLB_V4WBI 532 bool 533 help 534 ARM Architecture Version 4 TLB with writeback cache and invalidate 535 instruction cache entry. 536 537config CPU_TLB_FEROCEON 538 bool 539 help 540 Feroceon TLB (v4wbi with non-outer-cachable page table walks). 541 542config CPU_TLB_V6 543 bool 544 545config CPU_TLB_V7 546 bool 547 548endif 549 550config CPU_HAS_ASID 551 bool 552 help 553 This indicates whether the CPU has the ASID register; used to 554 tag TLB and possibly cache entries. 555 556config CPU_CP15 557 bool 558 help 559 Processor has the CP15 register. 560 561config CPU_CP15_MMU 562 bool 563 select CPU_CP15 564 help 565 Processor has the CP15 register, which has MMU related registers. 566 567config CPU_CP15_MPU 568 bool 569 select CPU_CP15 570 help 571 Processor has the CP15 register, which has MPU related registers. 572 573# 574# CPU supports 36-bit I/O 575# 576config IO_36 577 bool 578 579comment "Processor Features" 580 581config ARM_THUMB 582 bool "Support Thumb user binaries" 583 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON 584 default y 585 help 586 Say Y if you want to include kernel support for running user space 587 Thumb binaries. 588 589 The Thumb instruction set is a compressed form of the standard ARM 590 instruction set resulting in smaller binaries at the expense of 591 slightly less efficient code. 592 593 If you don't know what this all is, saying Y is a safe choice. 594 595config ARM_THUMBEE 596 bool "Enable ThumbEE CPU extension" 597 depends on CPU_V7 598 help 599 Say Y here if you have a CPU with the ThumbEE extension and code to 600 make use of it. Say N for code that can run on CPUs without ThumbEE. 601 602config CPU_BIG_ENDIAN 603 bool "Build big-endian kernel" 604 depends on ARCH_SUPPORTS_BIG_ENDIAN 605 help 606 Say Y if you plan on running a kernel in big-endian mode. 607 Note that your board must be properly built and your board 608 port must properly enable any big-endian related features 609 of your chipset/board/processor. 610 611config CPU_HIGH_VECTOR 612 depends on !MMU && CPU_CP15 && !CPU_ARM740T 613 bool "Select the High exception vector" 614 default n 615 help 616 Say Y here to select high exception vector(0xFFFF0000~). 617 The exception vector can be vary depending on the platform 618 design in nommu mode. If your platform needs to select 619 high exception vector, say Y. 620 Otherwise or if you are unsure, say N, and the low exception 621 vector (0x00000000~) will be used. 622 623config CPU_ICACHE_DISABLE 624 bool "Disable I-Cache (I-bit)" 625 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 626 help 627 Say Y here to disable the processor instruction cache. Unless 628 you have a reason not to or are unsure, say N. 629 630config CPU_DCACHE_DISABLE 631 bool "Disable D-Cache (C-bit)" 632 depends on CPU_CP15 633 help 634 Say Y here to disable the processor data cache. Unless 635 you have a reason not to or are unsure, say N. 636 637config CPU_DCACHE_SIZE 638 hex 639 depends on CPU_ARM740T || CPU_ARM946E 640 default 0x00001000 if CPU_ARM740T 641 default 0x00002000 # default size for ARM946E-S 642 help 643 Some cores are synthesizable to have various sized cache. For 644 ARM946E-S case, it can vary from 0KB to 1MB. 645 To support such cache operations, it is efficient to know the size 646 before compile time. 647 If your SoC is configured to have a different size, define the value 648 here with proper conditions. 649 650config CPU_DCACHE_WRITETHROUGH 651 bool "Force write through D-cache" 652 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE 653 default y if CPU_ARM925T 654 help 655 Say Y here to use the data cache in writethrough mode. Unless you 656 specifically require this or are unsure, say N. 657 658config CPU_CACHE_ROUND_ROBIN 659 bool "Round robin I and D cache replacement algorithm" 660 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) 661 help 662 Say Y here to use the predictable round-robin cache replacement 663 policy. Unless you specifically require this or are unsure, say N. 664 665config CPU_BPREDICT_DISABLE 666 bool "Disable branch prediction" 667 depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 668 help 669 Say Y here to disable branch prediction. If unsure, say N. 670 671config TLS_REG_EMUL 672 bool 673 help 674 An SMP system using a pre-ARMv6 processor (there are apparently 675 a few prototypes like that in existence) and therefore access to 676 that required register must be emulated. 677 678config HAS_TLS_REG 679 bool 680 depends on !TLS_REG_EMUL 681 default y if SMP || CPU_32v7 682 help 683 This selects support for the CP15 thread register. 684 It is defined to be available on some ARMv6 processors (including 685 all SMP capable ARMv6's) or later processors. User space may 686 assume directly accessing that register and always obtain the 687 expected value only on ARMv7 and above. 688 689config NEEDS_SYSCALL_FOR_CMPXCHG 690 bool 691 help 692 SMP on a pre-ARMv6 processor? Well OK then. 693 Forget about fast user space cmpxchg support. 694 It is just not possible. 695 696config OUTER_CACHE 697 bool 698 default n 699 700config CACHE_FEROCEON_L2 701 bool "Enable the Feroceon L2 cache controller" 702 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 703 default y 704 select OUTER_CACHE 705 help 706 This option enables the Feroceon L2 cache controller. 707 708config CACHE_FEROCEON_L2_WRITETHROUGH 709 bool "Force Feroceon L2 cache write through" 710 depends on CACHE_FEROCEON_L2 711 default n 712 help 713 Say Y here to use the Feroceon L2 cache in writethrough mode. 714 Unless you specifically require this, say N for writeback mode. 715 716config CACHE_L2X0 717 bool "Enable the L2x0 outer cache controller" 718 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 719 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 720 default y 721 select OUTER_CACHE 722 help 723 This option enables the L2x0 PrimeCell. 724 725config CACHE_XSC3L2 726 bool "Enable the L2 cache on XScale3" 727 depends on CPU_XSC3 728 default y 729 select OUTER_CACHE 730 help 731 This option enables the L2 cache on XScale3. 732