1/* 2 * Low-level PXA250/210 sleep/wakeUp support 3 * 4 * Initial SA1110 code: 5 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 6 * 7 * Adapted for PXA by Nicolas Pitre: 8 * Copyright (c) 2002 Monta Vista Software, Inc. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License. 12 */ 13 14#include <linux/config.h> 15#include <linux/linkage.h> 16#include <asm/assembler.h> 17#include <asm/hardware.h> 18 19#include <asm/arch/pxa-regs.h> 20 21#ifdef CONFIG_PXA27x // workaround for Errata 50 22#define MDREFR_KDIV 0x200a4000 // all banks 23#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 24#endif 25 26 .text 27 28/* 29 * pxa_cpu_suspend() 30 * 31 * Forces CPU into sleep state 32 */ 33 34ENTRY(pxa_cpu_suspend) 35 36#ifndef CONFIG_IWMMXT 37 mra r2, r3, acc0 38#endif 39 stmfd sp!, {r2 - r12, lr} @ save registers on stack 40 41 @ get coprocessor registers 42 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode 43 mrc p15, 0, r4, c15, c1, 0 @ CP access reg 44 mrc p15, 0, r5, c13, c0, 0 @ PID 45 mrc p15, 0, r6, c3, c0, 0 @ domain ID 46 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr 47 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg 48 mrc p15, 0, r9, c1, c0, 0 @ control reg 49 50 bic r3, r3, #2 @ clear frequency change bit 51 52 @ store them plus current virtual stack ptr on stack 53 mov r10, sp 54 stmfd sp!, {r3 - r10} 55 56 @ preserve phys address of stack 57 mov r0, sp 58 bl sleep_phys_sp 59 ldr r1, =sleep_save_sp 60 str r0, [r1] 61 62 @ clean data cache 63 bl xscale_flush_kern_cache_all 64 65 @ Put the processor to sleep 66 @ (also workaround for sighting 28071) 67 68 @ prepare value for sleep mode 69 mov r1, #3 @ sleep mode 70 71 @ prepare pointer to physical address 0 (virtual mapping in generic.c) 72 mov r2, #UNCACHED_PHYS_0 73 74 @ prepare SDRAM refresh settings 75 ldr r4, =MDREFR 76 ldr r5, [r4] 77 78 @ enable SDRAM self-refresh mode 79 orr r5, r5, #MDREFR_SLFRSH 80 81#ifdef CONFIG_PXA27x 82 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50) 83 ldr r6, =MDREFR_KDIV 84 orr r5, r5, r6 85#endif 86 87#ifdef CONFIG_PXA25x 88 @ Intel PXA255 Specification Update notes problems 89 @ about suspending with PXBus operating above 133MHz 90 @ (see Errata 31, GPIO output signals, ... unpredictable in sleep 91 @ 92 @ We keep the change-down close to the actual suspend on SDRAM 93 @ as possible to eliminate messing about with the refresh clock 94 @ as the system will restore with the original speed settings 95 @ 96 @ Ben Dooks, 13-Sep-2004 97 98 ldr r6, =CCCR 99 ldr r8, [r6] @ keep original value for resume 100 101 @ ensure x1 for run and turbo mode with memory clock 102 bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK 103 orr r7, r7, #(1<<5) | (2<<7) 104 105 @ check that the memory frequency is within limits 106 and r14, r7, #CCCR_L_MASK 107 teq r14, #1 108 bicne r7, r7, #CCCR_L_MASK 109 orrne r7, r7, #1 @@ 99.53MHz 110 111 @ get ready for the change 112 113 @ note, turbo is not preserved over sleep so there is no 114 @ point in preserving it here. we save it on the stack with the 115 @ other CP registers instead. 116 mov r0, #0 117 mcr p14, 0, r0, c6, c0, 0 118 orr r0, r0, #2 @ initiate change bit 119#endif 120#ifdef CONFIG_PXA27x 121 @ Intel PXA270 Specification Update notes problems sleeping 122 @ with core operating above 91 MHz 123 @ (see Errata 50, ...processor does not exit from sleep...) 124 125 ldr r6, =CCCR 126 ldr r8, [r6] @ keep original value for resume 127 128 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value 129 mov r0, #0x2 @ prepare value for CLKCFG 130#endif 131 132 @ align execution to a cache line 133 b 1f 134 135 .ltorg 136 .align 5 1371: 138 139 @ All needed values are now in registers. 140 @ These last instructions should be in cache 141 142#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) 143 @ initiate the frequency change... 144 str r7, [r6] 145 mcr p14, 0, r0, c6, c0, 0 146 147 @ restore the original cpu speed value for resume 148 str r8, [r6] 149 150 @ need 6 13-MHz cycles before changing PWRMODE 151 @ just set frequency to 91-MHz... 6*91/13 = 42 152 153 mov r0, #42 15410: subs r0, r0, #1 155 bne 10b 156#endif 157 158 @ Do not reorder... 159 @ Intel PXA270 Specification Update notes problems performing 160 @ external accesses after SDRAM is put in self-refresh mode 161 @ (see Errata 39 ...hangs when entering self-refresh mode) 162 163 @ force address lines low by reading at physical address 0 164 ldr r3, [r2] 165 166 @ put SDRAM into self-refresh 167 str r5, [r4] 168 169 @ enter sleep mode 170 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE 171 17220: b 20b @ loop waiting for sleep 173 174/* 175 * cpu_pxa_resume() 176 * 177 * entry point from bootloader into kernel during resume 178 * 179 * Note: Yes, part of the following code is located into the .data section. 180 * This is to allow sleep_save_sp to be accessed with a relative load 181 * while we can't rely on any MMU translation. We could have put 182 * sleep_save_sp in the .text section as well, but some setups might 183 * insist on it to be truly read-only. 184 */ 185 186 .data 187 .align 5 188ENTRY(pxa_cpu_resume) 189 mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC @ set SVC, irqs off 190 msr cpsr_c, r0 191 192 ldr r0, sleep_save_sp @ stack phys addr 193 ldr r2, =resume_after_mmu @ its absolute virtual address 194 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr 195 196 mov r1, #0 197 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 198 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB 199 200#ifdef CONFIG_XSCALE_CACHE_ERRATA 201 bic r9, r9, #0x0004 @ see cpu_xscale_proc_init 202#endif 203 204 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode. 205 mcr p15, 0, r4, c15, c1, 0 @ CP access reg 206 mcr p15, 0, r5, c13, c0, 0 @ PID 207 mcr p15, 0, r6, c3, c0, 0 @ domain ID 208 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr 209 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg 210 b resume_turn_on_mmu @ cache align execution 211 212 .align 5 213resume_turn_on_mmu: 214 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc. 215 216 @ Let us ensure we jump to resume_after_mmu only when the mcr above 217 @ actually took effect. They call it the "cpwait" operation. 218 mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15 219 sub pc, r2, r1, lsr #32 @ jump to virtual addr 220 nop 221 nop 222 nop 223 224sleep_save_sp: 225 .word 0 @ preserve stack phys ptr here 226 227 .text 228resume_after_mmu: 229#ifdef CONFIG_XSCALE_CACHE_ERRATA 230 bl cpu_xscale_proc_init 231#endif 232 ldmfd sp!, {r2, r3} 233#ifndef CONFIG_IWMMXT 234 mar acc0, r2, r3 235#endif 236 ldmfd sp!, {r4 - r12, pc} @ return to caller 237 238 239