1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * The data in this file should be completely autogeneratable from 12 * the TI hardware database or other technical documentation. 13 * 14 * XXX these should be marked initdata for multi-OMAP kernels 15 */ 16 #include <plat/omap_hwmod.h> 17 #include <mach/irqs.h> 18 #include <plat/cpu.h> 19 #include <plat/dma.h> 20 #include <plat/serial.h> 21 #include <plat/l3_3xxx.h> 22 #include <plat/l4_3xxx.h> 23 #include <plat/i2c.h> 24 #include <plat/gpio.h> 25 #include <plat/mmc.h> 26 #include <plat/mcbsp.h> 27 #include <plat/mcspi.h> 28 #include <plat/dmtimer.h> 29 30 #include "omap_hwmod_common_data.h" 31 32 #include "prm-regbits-34xx.h" 33 #include "cm-regbits-34xx.h" 34 #include "wd_timer.h" 35 #include <mach/am35xx.h> 36 37 /* 38 * OMAP3xxx hardware module integration data 39 * 40 * ALl of the data in this section should be autogeneratable from the 41 * TI hardware database or other technical documentation. Data that 42 * is driver-specific or driver-kernel integration-specific belongs 43 * elsewhere. 44 */ 45 46 static struct omap_hwmod omap3xxx_mpu_hwmod; 47 static struct omap_hwmod omap3xxx_iva_hwmod; 48 static struct omap_hwmod omap3xxx_l3_main_hwmod; 49 static struct omap_hwmod omap3xxx_l4_core_hwmod; 50 static struct omap_hwmod omap3xxx_l4_per_hwmod; 51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod; 52 static struct omap_hwmod omap3430es1_dss_core_hwmod; 53 static struct omap_hwmod omap3xxx_dss_core_hwmod; 54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod; 55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; 56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; 57 static struct omap_hwmod omap3xxx_dss_venc_hwmod; 58 static struct omap_hwmod omap3xxx_i2c1_hwmod; 59 static struct omap_hwmod omap3xxx_i2c2_hwmod; 60 static struct omap_hwmod omap3xxx_i2c3_hwmod; 61 static struct omap_hwmod omap3xxx_gpio1_hwmod; 62 static struct omap_hwmod omap3xxx_gpio2_hwmod; 63 static struct omap_hwmod omap3xxx_gpio3_hwmod; 64 static struct omap_hwmod omap3xxx_gpio4_hwmod; 65 static struct omap_hwmod omap3xxx_gpio5_hwmod; 66 static struct omap_hwmod omap3xxx_gpio6_hwmod; 67 static struct omap_hwmod omap34xx_sr1_hwmod; 68 static struct omap_hwmod omap34xx_sr2_hwmod; 69 static struct omap_hwmod omap34xx_mcspi1; 70 static struct omap_hwmod omap34xx_mcspi2; 71 static struct omap_hwmod omap34xx_mcspi3; 72 static struct omap_hwmod omap34xx_mcspi4; 73 static struct omap_hwmod omap3xxx_mmc1_hwmod; 74 static struct omap_hwmod omap3xxx_mmc2_hwmod; 75 static struct omap_hwmod omap3xxx_mmc3_hwmod; 76 static struct omap_hwmod am35xx_usbhsotg_hwmod; 77 78 static struct omap_hwmod omap3xxx_dma_system_hwmod; 79 80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod; 81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod; 82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod; 83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod; 84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod; 85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; 86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; 87 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; 88 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; 89 90 /* L3 -> L4_CORE interface */ 91 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 92 .master = &omap3xxx_l3_main_hwmod, 93 .slave = &omap3xxx_l4_core_hwmod, 94 .user = OCP_USER_MPU | OCP_USER_SDMA, 95 }; 96 97 /* L3 -> L4_PER interface */ 98 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 99 .master = &omap3xxx_l3_main_hwmod, 100 .slave = &omap3xxx_l4_per_hwmod, 101 .user = OCP_USER_MPU | OCP_USER_SDMA, 102 }; 103 104 /* L3 taret configuration and error log registers */ 105 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 106 { .irq = INT_34XX_L3_DBG_IRQ }, 107 { .irq = INT_34XX_L3_APP_IRQ }, 108 { .irq = -1 } 109 }; 110 111 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 112 { 113 .pa_start = 0x68000000, 114 .pa_end = 0x6800ffff, 115 .flags = ADDR_TYPE_RT, 116 }, 117 { } 118 }; 119 120 /* MPU -> L3 interface */ 121 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 122 .master = &omap3xxx_mpu_hwmod, 123 .slave = &omap3xxx_l3_main_hwmod, 124 .addr = omap3xxx_l3_main_addrs, 125 .user = OCP_USER_MPU, 126 }; 127 128 /* Slave interfaces on the L3 interconnect */ 129 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { 130 &omap3xxx_mpu__l3_main, 131 }; 132 133 /* DSS -> l3 */ 134 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 135 .master = &omap3xxx_dss_core_hwmod, 136 .slave = &omap3xxx_l3_main_hwmod, 137 .fw = { 138 .omap2 = { 139 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 140 .flags = OMAP_FIREWALL_L3, 141 } 142 }, 143 .user = OCP_USER_MPU | OCP_USER_SDMA, 144 }; 145 146 /* Master interfaces on the L3 interconnect */ 147 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { 148 &omap3xxx_l3_main__l4_core, 149 &omap3xxx_l3_main__l4_per, 150 }; 151 152 /* L3 */ 153 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 154 .name = "l3_main", 155 .class = &l3_hwmod_class, 156 .mpu_irqs = omap3xxx_l3_main_irqs, 157 .masters = omap3xxx_l3_main_masters, 158 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 159 .slaves = omap3xxx_l3_main_slaves, 160 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), 161 .flags = HWMOD_NO_IDLEST, 162 }; 163 164 static struct omap_hwmod omap3xxx_l4_wkup_hwmod; 165 static struct omap_hwmod omap3xxx_uart1_hwmod; 166 static struct omap_hwmod omap3xxx_uart2_hwmod; 167 static struct omap_hwmod omap3xxx_uart3_hwmod; 168 static struct omap_hwmod omap3xxx_uart4_hwmod; 169 static struct omap_hwmod am35xx_uart4_hwmod; 170 static struct omap_hwmod omap3xxx_usbhsotg_hwmod; 171 172 /* l3_core -> usbhsotg interface */ 173 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 174 .master = &omap3xxx_usbhsotg_hwmod, 175 .slave = &omap3xxx_l3_main_hwmod, 176 .clk = "core_l3_ick", 177 .user = OCP_USER_MPU, 178 }; 179 180 /* l3_core -> am35xx_usbhsotg interface */ 181 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 182 .master = &am35xx_usbhsotg_hwmod, 183 .slave = &omap3xxx_l3_main_hwmod, 184 .clk = "core_l3_ick", 185 .user = OCP_USER_MPU, 186 }; 187 /* L4_CORE -> L4_WKUP interface */ 188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 189 .master = &omap3xxx_l4_core_hwmod, 190 .slave = &omap3xxx_l4_wkup_hwmod, 191 .user = OCP_USER_MPU | OCP_USER_SDMA, 192 }; 193 194 /* L4 CORE -> MMC1 interface */ 195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { 196 .master = &omap3xxx_l4_core_hwmod, 197 .slave = &omap3xxx_mmc1_hwmod, 198 .clk = "mmchs1_ick", 199 .addr = omap2430_mmc1_addr_space, 200 .user = OCP_USER_MPU | OCP_USER_SDMA, 201 .flags = OMAP_FIREWALL_L4 202 }; 203 204 /* L4 CORE -> MMC2 interface */ 205 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { 206 .master = &omap3xxx_l4_core_hwmod, 207 .slave = &omap3xxx_mmc2_hwmod, 208 .clk = "mmchs2_ick", 209 .addr = omap2430_mmc2_addr_space, 210 .user = OCP_USER_MPU | OCP_USER_SDMA, 211 .flags = OMAP_FIREWALL_L4 212 }; 213 214 /* L4 CORE -> MMC3 interface */ 215 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { 216 { 217 .pa_start = 0x480ad000, 218 .pa_end = 0x480ad1ff, 219 .flags = ADDR_TYPE_RT, 220 }, 221 { } 222 }; 223 224 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 225 .master = &omap3xxx_l4_core_hwmod, 226 .slave = &omap3xxx_mmc3_hwmod, 227 .clk = "mmchs3_ick", 228 .addr = omap3xxx_mmc3_addr_space, 229 .user = OCP_USER_MPU | OCP_USER_SDMA, 230 .flags = OMAP_FIREWALL_L4 231 }; 232 233 /* L4 CORE -> UART1 interface */ 234 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 235 { 236 .pa_start = OMAP3_UART1_BASE, 237 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 238 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 239 }, 240 { } 241 }; 242 243 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 244 .master = &omap3xxx_l4_core_hwmod, 245 .slave = &omap3xxx_uart1_hwmod, 246 .clk = "uart1_ick", 247 .addr = omap3xxx_uart1_addr_space, 248 .user = OCP_USER_MPU | OCP_USER_SDMA, 249 }; 250 251 /* L4 CORE -> UART2 interface */ 252 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { 253 { 254 .pa_start = OMAP3_UART2_BASE, 255 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 256 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 257 }, 258 { } 259 }; 260 261 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 262 .master = &omap3xxx_l4_core_hwmod, 263 .slave = &omap3xxx_uart2_hwmod, 264 .clk = "uart2_ick", 265 .addr = omap3xxx_uart2_addr_space, 266 .user = OCP_USER_MPU | OCP_USER_SDMA, 267 }; 268 269 /* L4 PER -> UART3 interface */ 270 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { 271 { 272 .pa_start = OMAP3_UART3_BASE, 273 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 274 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 275 }, 276 { } 277 }; 278 279 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 280 .master = &omap3xxx_l4_per_hwmod, 281 .slave = &omap3xxx_uart3_hwmod, 282 .clk = "uart3_ick", 283 .addr = omap3xxx_uart3_addr_space, 284 .user = OCP_USER_MPU | OCP_USER_SDMA, 285 }; 286 287 /* L4 PER -> UART4 interface */ 288 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { 289 { 290 .pa_start = OMAP3_UART4_BASE, 291 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 292 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 293 }, 294 { } 295 }; 296 297 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 298 .master = &omap3xxx_l4_per_hwmod, 299 .slave = &omap3xxx_uart4_hwmod, 300 .clk = "uart4_ick", 301 .addr = omap3xxx_uart4_addr_space, 302 .user = OCP_USER_MPU | OCP_USER_SDMA, 303 }; 304 305 /* AM35xx: L4 CORE -> UART4 interface */ 306 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { 307 { 308 .pa_start = OMAP3_UART4_AM35XX_BASE, 309 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, 310 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 311 }, 312 }; 313 314 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 315 .master = &omap3xxx_l4_core_hwmod, 316 .slave = &am35xx_uart4_hwmod, 317 .clk = "uart4_ick", 318 .addr = am35xx_uart4_addr_space, 319 .user = OCP_USER_MPU | OCP_USER_SDMA, 320 }; 321 322 /* L4 CORE -> I2C1 interface */ 323 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 324 .master = &omap3xxx_l4_core_hwmod, 325 .slave = &omap3xxx_i2c1_hwmod, 326 .clk = "i2c1_ick", 327 .addr = omap2_i2c1_addr_space, 328 .fw = { 329 .omap2 = { 330 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 331 .l4_prot_group = 7, 332 .flags = OMAP_FIREWALL_L4, 333 } 334 }, 335 .user = OCP_USER_MPU | OCP_USER_SDMA, 336 }; 337 338 /* L4 CORE -> I2C2 interface */ 339 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 340 .master = &omap3xxx_l4_core_hwmod, 341 .slave = &omap3xxx_i2c2_hwmod, 342 .clk = "i2c2_ick", 343 .addr = omap2_i2c2_addr_space, 344 .fw = { 345 .omap2 = { 346 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 347 .l4_prot_group = 7, 348 .flags = OMAP_FIREWALL_L4, 349 } 350 }, 351 .user = OCP_USER_MPU | OCP_USER_SDMA, 352 }; 353 354 /* L4 CORE -> I2C3 interface */ 355 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 356 { 357 .pa_start = 0x48060000, 358 .pa_end = 0x48060000 + SZ_128 - 1, 359 .flags = ADDR_TYPE_RT, 360 }, 361 { } 362 }; 363 364 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 365 .master = &omap3xxx_l4_core_hwmod, 366 .slave = &omap3xxx_i2c3_hwmod, 367 .clk = "i2c3_ick", 368 .addr = omap3xxx_i2c3_addr_space, 369 .fw = { 370 .omap2 = { 371 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 372 .l4_prot_group = 7, 373 .flags = OMAP_FIREWALL_L4, 374 } 375 }, 376 .user = OCP_USER_MPU | OCP_USER_SDMA, 377 }; 378 379 /* L4 CORE -> SR1 interface */ 380 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { 381 { 382 .pa_start = OMAP34XX_SR1_BASE, 383 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 384 .flags = ADDR_TYPE_RT, 385 }, 386 { } 387 }; 388 389 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { 390 .master = &omap3xxx_l4_core_hwmod, 391 .slave = &omap34xx_sr1_hwmod, 392 .clk = "sr_l4_ick", 393 .addr = omap3_sr1_addr_space, 394 .user = OCP_USER_MPU, 395 }; 396 397 /* L4 CORE -> SR1 interface */ 398 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { 399 { 400 .pa_start = OMAP34XX_SR2_BASE, 401 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 402 .flags = ADDR_TYPE_RT, 403 }, 404 { } 405 }; 406 407 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { 408 .master = &omap3xxx_l4_core_hwmod, 409 .slave = &omap34xx_sr2_hwmod, 410 .clk = "sr_l4_ick", 411 .addr = omap3_sr2_addr_space, 412 .user = OCP_USER_MPU, 413 }; 414 415 /* 416 * usbhsotg interface data 417 */ 418 419 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { 420 { 421 .pa_start = OMAP34XX_HSUSB_OTG_BASE, 422 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 423 .flags = ADDR_TYPE_RT 424 }, 425 { } 426 }; 427 428 /* l4_core -> usbhsotg */ 429 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 430 .master = &omap3xxx_l4_core_hwmod, 431 .slave = &omap3xxx_usbhsotg_hwmod, 432 .clk = "l4_ick", 433 .addr = omap3xxx_usbhsotg_addrs, 434 .user = OCP_USER_MPU, 435 }; 436 437 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { 438 &omap3xxx_usbhsotg__l3, 439 }; 440 441 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { 442 &omap3xxx_l4_core__usbhsotg, 443 }; 444 445 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { 446 { 447 .pa_start = AM35XX_IPSS_USBOTGSS_BASE, 448 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 449 .flags = ADDR_TYPE_RT 450 }, 451 { } 452 }; 453 454 /* l4_core -> usbhsotg */ 455 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 456 .master = &omap3xxx_l4_core_hwmod, 457 .slave = &am35xx_usbhsotg_hwmod, 458 .clk = "l4_ick", 459 .addr = am35xx_usbhsotg_addrs, 460 .user = OCP_USER_MPU, 461 }; 462 463 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { 464 &am35xx_usbhsotg__l3, 465 }; 466 467 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { 468 &am35xx_l4_core__usbhsotg, 469 }; 470 /* Slave interfaces on the L4_CORE interconnect */ 471 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 472 &omap3xxx_l3_main__l4_core, 473 }; 474 475 /* L4 CORE */ 476 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 477 .name = "l4_core", 478 .class = &l4_hwmod_class, 479 .slaves = omap3xxx_l4_core_slaves, 480 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), 481 .flags = HWMOD_NO_IDLEST, 482 }; 483 484 /* Slave interfaces on the L4_PER interconnect */ 485 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { 486 &omap3xxx_l3_main__l4_per, 487 }; 488 489 /* L4 PER */ 490 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 491 .name = "l4_per", 492 .class = &l4_hwmod_class, 493 .slaves = omap3xxx_l4_per_slaves, 494 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), 495 .flags = HWMOD_NO_IDLEST, 496 }; 497 498 /* Slave interfaces on the L4_WKUP interconnect */ 499 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { 500 &omap3xxx_l4_core__l4_wkup, 501 }; 502 503 /* L4 WKUP */ 504 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 505 .name = "l4_wkup", 506 .class = &l4_hwmod_class, 507 .slaves = omap3xxx_l4_wkup_slaves, 508 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), 509 .flags = HWMOD_NO_IDLEST, 510 }; 511 512 /* Master interfaces on the MPU device */ 513 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { 514 &omap3xxx_mpu__l3_main, 515 }; 516 517 /* MPU */ 518 static struct omap_hwmod omap3xxx_mpu_hwmod = { 519 .name = "mpu", 520 .class = &mpu_hwmod_class, 521 .main_clk = "arm_fck", 522 .masters = omap3xxx_mpu_masters, 523 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), 524 }; 525 526 /* 527 * IVA2_2 interface data 528 */ 529 530 /* IVA2 <- L3 interface */ 531 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 532 .master = &omap3xxx_l3_main_hwmod, 533 .slave = &omap3xxx_iva_hwmod, 534 .clk = "iva2_ck", 535 .user = OCP_USER_MPU | OCP_USER_SDMA, 536 }; 537 538 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { 539 &omap3xxx_l3__iva, 540 }; 541 542 /* 543 * IVA2 (IVA2) 544 */ 545 546 static struct omap_hwmod omap3xxx_iva_hwmod = { 547 .name = "iva", 548 .class = &iva_hwmod_class, 549 .masters = omap3xxx_iva_masters, 550 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), 551 }; 552 553 /* timer class */ 554 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { 555 .rev_offs = 0x0000, 556 .sysc_offs = 0x0010, 557 .syss_offs = 0x0014, 558 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 559 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 560 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), 561 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 562 .sysc_fields = &omap_hwmod_sysc_type1, 563 }; 564 565 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { 566 .name = "timer", 567 .sysc = &omap3xxx_timer_1ms_sysc, 568 .rev = OMAP_TIMER_IP_VERSION_1, 569 }; 570 571 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 572 .rev_offs = 0x0000, 573 .sysc_offs = 0x0010, 574 .syss_offs = 0x0014, 575 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 576 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 578 .sysc_fields = &omap_hwmod_sysc_type1, 579 }; 580 581 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 582 .name = "timer", 583 .sysc = &omap3xxx_timer_sysc, 584 .rev = OMAP_TIMER_IP_VERSION_1, 585 }; 586 587 /* secure timers dev attribute */ 588 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 589 .timer_capability = OMAP_TIMER_SECURE, 590 }; 591 592 /* always-on timers dev attribute */ 593 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 594 .timer_capability = OMAP_TIMER_ALWON, 595 }; 596 597 /* pwm timers dev attribute */ 598 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 599 .timer_capability = OMAP_TIMER_HAS_PWM, 600 }; 601 602 /* timer1 */ 603 static struct omap_hwmod omap3xxx_timer1_hwmod; 604 605 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 606 { 607 .pa_start = 0x48318000, 608 .pa_end = 0x48318000 + SZ_1K - 1, 609 .flags = ADDR_TYPE_RT 610 }, 611 { } 612 }; 613 614 /* l4_wkup -> timer1 */ 615 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 616 .master = &omap3xxx_l4_wkup_hwmod, 617 .slave = &omap3xxx_timer1_hwmod, 618 .clk = "gpt1_ick", 619 .addr = omap3xxx_timer1_addrs, 620 .user = OCP_USER_MPU | OCP_USER_SDMA, 621 }; 622 623 /* timer1 slave port */ 624 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { 625 &omap3xxx_l4_wkup__timer1, 626 }; 627 628 /* timer1 hwmod */ 629 static struct omap_hwmod omap3xxx_timer1_hwmod = { 630 .name = "timer1", 631 .mpu_irqs = omap2_timer1_mpu_irqs, 632 .main_clk = "gpt1_fck", 633 .prcm = { 634 .omap2 = { 635 .prcm_reg_id = 1, 636 .module_bit = OMAP3430_EN_GPT1_SHIFT, 637 .module_offs = WKUP_MOD, 638 .idlest_reg_id = 1, 639 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 640 }, 641 }, 642 .dev_attr = &capability_alwon_dev_attr, 643 .slaves = omap3xxx_timer1_slaves, 644 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), 645 .class = &omap3xxx_timer_1ms_hwmod_class, 646 }; 647 648 /* timer2 */ 649 static struct omap_hwmod omap3xxx_timer2_hwmod; 650 651 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 652 { 653 .pa_start = 0x49032000, 654 .pa_end = 0x49032000 + SZ_1K - 1, 655 .flags = ADDR_TYPE_RT 656 }, 657 { } 658 }; 659 660 /* l4_per -> timer2 */ 661 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 662 .master = &omap3xxx_l4_per_hwmod, 663 .slave = &omap3xxx_timer2_hwmod, 664 .clk = "gpt2_ick", 665 .addr = omap3xxx_timer2_addrs, 666 .user = OCP_USER_MPU | OCP_USER_SDMA, 667 }; 668 669 /* timer2 slave port */ 670 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { 671 &omap3xxx_l4_per__timer2, 672 }; 673 674 /* timer2 hwmod */ 675 static struct omap_hwmod omap3xxx_timer2_hwmod = { 676 .name = "timer2", 677 .mpu_irqs = omap2_timer2_mpu_irqs, 678 .main_clk = "gpt2_fck", 679 .prcm = { 680 .omap2 = { 681 .prcm_reg_id = 1, 682 .module_bit = OMAP3430_EN_GPT2_SHIFT, 683 .module_offs = OMAP3430_PER_MOD, 684 .idlest_reg_id = 1, 685 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 686 }, 687 }, 688 .dev_attr = &capability_alwon_dev_attr, 689 .slaves = omap3xxx_timer2_slaves, 690 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), 691 .class = &omap3xxx_timer_1ms_hwmod_class, 692 }; 693 694 /* timer3 */ 695 static struct omap_hwmod omap3xxx_timer3_hwmod; 696 697 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 698 { 699 .pa_start = 0x49034000, 700 .pa_end = 0x49034000 + SZ_1K - 1, 701 .flags = ADDR_TYPE_RT 702 }, 703 { } 704 }; 705 706 /* l4_per -> timer3 */ 707 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 708 .master = &omap3xxx_l4_per_hwmod, 709 .slave = &omap3xxx_timer3_hwmod, 710 .clk = "gpt3_ick", 711 .addr = omap3xxx_timer3_addrs, 712 .user = OCP_USER_MPU | OCP_USER_SDMA, 713 }; 714 715 /* timer3 slave port */ 716 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { 717 &omap3xxx_l4_per__timer3, 718 }; 719 720 /* timer3 hwmod */ 721 static struct omap_hwmod omap3xxx_timer3_hwmod = { 722 .name = "timer3", 723 .mpu_irqs = omap2_timer3_mpu_irqs, 724 .main_clk = "gpt3_fck", 725 .prcm = { 726 .omap2 = { 727 .prcm_reg_id = 1, 728 .module_bit = OMAP3430_EN_GPT3_SHIFT, 729 .module_offs = OMAP3430_PER_MOD, 730 .idlest_reg_id = 1, 731 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 732 }, 733 }, 734 .dev_attr = &capability_alwon_dev_attr, 735 .slaves = omap3xxx_timer3_slaves, 736 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), 737 .class = &omap3xxx_timer_hwmod_class, 738 }; 739 740 /* timer4 */ 741 static struct omap_hwmod omap3xxx_timer4_hwmod; 742 743 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 744 { 745 .pa_start = 0x49036000, 746 .pa_end = 0x49036000 + SZ_1K - 1, 747 .flags = ADDR_TYPE_RT 748 }, 749 { } 750 }; 751 752 /* l4_per -> timer4 */ 753 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 754 .master = &omap3xxx_l4_per_hwmod, 755 .slave = &omap3xxx_timer4_hwmod, 756 .clk = "gpt4_ick", 757 .addr = omap3xxx_timer4_addrs, 758 .user = OCP_USER_MPU | OCP_USER_SDMA, 759 }; 760 761 /* timer4 slave port */ 762 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { 763 &omap3xxx_l4_per__timer4, 764 }; 765 766 /* timer4 hwmod */ 767 static struct omap_hwmod omap3xxx_timer4_hwmod = { 768 .name = "timer4", 769 .mpu_irqs = omap2_timer4_mpu_irqs, 770 .main_clk = "gpt4_fck", 771 .prcm = { 772 .omap2 = { 773 .prcm_reg_id = 1, 774 .module_bit = OMAP3430_EN_GPT4_SHIFT, 775 .module_offs = OMAP3430_PER_MOD, 776 .idlest_reg_id = 1, 777 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 778 }, 779 }, 780 .dev_attr = &capability_alwon_dev_attr, 781 .slaves = omap3xxx_timer4_slaves, 782 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), 783 .class = &omap3xxx_timer_hwmod_class, 784 }; 785 786 /* timer5 */ 787 static struct omap_hwmod omap3xxx_timer5_hwmod; 788 789 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 790 { 791 .pa_start = 0x49038000, 792 .pa_end = 0x49038000 + SZ_1K - 1, 793 .flags = ADDR_TYPE_RT 794 }, 795 { } 796 }; 797 798 /* l4_per -> timer5 */ 799 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 800 .master = &omap3xxx_l4_per_hwmod, 801 .slave = &omap3xxx_timer5_hwmod, 802 .clk = "gpt5_ick", 803 .addr = omap3xxx_timer5_addrs, 804 .user = OCP_USER_MPU | OCP_USER_SDMA, 805 }; 806 807 /* timer5 slave port */ 808 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { 809 &omap3xxx_l4_per__timer5, 810 }; 811 812 /* timer5 hwmod */ 813 static struct omap_hwmod omap3xxx_timer5_hwmod = { 814 .name = "timer5", 815 .mpu_irqs = omap2_timer5_mpu_irqs, 816 .main_clk = "gpt5_fck", 817 .prcm = { 818 .omap2 = { 819 .prcm_reg_id = 1, 820 .module_bit = OMAP3430_EN_GPT5_SHIFT, 821 .module_offs = OMAP3430_PER_MOD, 822 .idlest_reg_id = 1, 823 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 824 }, 825 }, 826 .dev_attr = &capability_alwon_dev_attr, 827 .slaves = omap3xxx_timer5_slaves, 828 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), 829 .class = &omap3xxx_timer_hwmod_class, 830 }; 831 832 /* timer6 */ 833 static struct omap_hwmod omap3xxx_timer6_hwmod; 834 835 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 836 { 837 .pa_start = 0x4903A000, 838 .pa_end = 0x4903A000 + SZ_1K - 1, 839 .flags = ADDR_TYPE_RT 840 }, 841 { } 842 }; 843 844 /* l4_per -> timer6 */ 845 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 846 .master = &omap3xxx_l4_per_hwmod, 847 .slave = &omap3xxx_timer6_hwmod, 848 .clk = "gpt6_ick", 849 .addr = omap3xxx_timer6_addrs, 850 .user = OCP_USER_MPU | OCP_USER_SDMA, 851 }; 852 853 /* timer6 slave port */ 854 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { 855 &omap3xxx_l4_per__timer6, 856 }; 857 858 /* timer6 hwmod */ 859 static struct omap_hwmod omap3xxx_timer6_hwmod = { 860 .name = "timer6", 861 .mpu_irqs = omap2_timer6_mpu_irqs, 862 .main_clk = "gpt6_fck", 863 .prcm = { 864 .omap2 = { 865 .prcm_reg_id = 1, 866 .module_bit = OMAP3430_EN_GPT6_SHIFT, 867 .module_offs = OMAP3430_PER_MOD, 868 .idlest_reg_id = 1, 869 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 870 }, 871 }, 872 .dev_attr = &capability_alwon_dev_attr, 873 .slaves = omap3xxx_timer6_slaves, 874 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), 875 .class = &omap3xxx_timer_hwmod_class, 876 }; 877 878 /* timer7 */ 879 static struct omap_hwmod omap3xxx_timer7_hwmod; 880 881 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 882 { 883 .pa_start = 0x4903C000, 884 .pa_end = 0x4903C000 + SZ_1K - 1, 885 .flags = ADDR_TYPE_RT 886 }, 887 { } 888 }; 889 890 /* l4_per -> timer7 */ 891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 892 .master = &omap3xxx_l4_per_hwmod, 893 .slave = &omap3xxx_timer7_hwmod, 894 .clk = "gpt7_ick", 895 .addr = omap3xxx_timer7_addrs, 896 .user = OCP_USER_MPU | OCP_USER_SDMA, 897 }; 898 899 /* timer7 slave port */ 900 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { 901 &omap3xxx_l4_per__timer7, 902 }; 903 904 /* timer7 hwmod */ 905 static struct omap_hwmod omap3xxx_timer7_hwmod = { 906 .name = "timer7", 907 .mpu_irqs = omap2_timer7_mpu_irqs, 908 .main_clk = "gpt7_fck", 909 .prcm = { 910 .omap2 = { 911 .prcm_reg_id = 1, 912 .module_bit = OMAP3430_EN_GPT7_SHIFT, 913 .module_offs = OMAP3430_PER_MOD, 914 .idlest_reg_id = 1, 915 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 916 }, 917 }, 918 .dev_attr = &capability_alwon_dev_attr, 919 .slaves = omap3xxx_timer7_slaves, 920 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), 921 .class = &omap3xxx_timer_hwmod_class, 922 }; 923 924 /* timer8 */ 925 static struct omap_hwmod omap3xxx_timer8_hwmod; 926 927 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 928 { 929 .pa_start = 0x4903E000, 930 .pa_end = 0x4903E000 + SZ_1K - 1, 931 .flags = ADDR_TYPE_RT 932 }, 933 { } 934 }; 935 936 /* l4_per -> timer8 */ 937 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 938 .master = &omap3xxx_l4_per_hwmod, 939 .slave = &omap3xxx_timer8_hwmod, 940 .clk = "gpt8_ick", 941 .addr = omap3xxx_timer8_addrs, 942 .user = OCP_USER_MPU | OCP_USER_SDMA, 943 }; 944 945 /* timer8 slave port */ 946 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { 947 &omap3xxx_l4_per__timer8, 948 }; 949 950 /* timer8 hwmod */ 951 static struct omap_hwmod omap3xxx_timer8_hwmod = { 952 .name = "timer8", 953 .mpu_irqs = omap2_timer8_mpu_irqs, 954 .main_clk = "gpt8_fck", 955 .prcm = { 956 .omap2 = { 957 .prcm_reg_id = 1, 958 .module_bit = OMAP3430_EN_GPT8_SHIFT, 959 .module_offs = OMAP3430_PER_MOD, 960 .idlest_reg_id = 1, 961 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 962 }, 963 }, 964 .dev_attr = &capability_pwm_dev_attr, 965 .slaves = omap3xxx_timer8_slaves, 966 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), 967 .class = &omap3xxx_timer_hwmod_class, 968 }; 969 970 /* timer9 */ 971 static struct omap_hwmod omap3xxx_timer9_hwmod; 972 973 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 974 { 975 .pa_start = 0x49040000, 976 .pa_end = 0x49040000 + SZ_1K - 1, 977 .flags = ADDR_TYPE_RT 978 }, 979 { } 980 }; 981 982 /* l4_per -> timer9 */ 983 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 984 .master = &omap3xxx_l4_per_hwmod, 985 .slave = &omap3xxx_timer9_hwmod, 986 .clk = "gpt9_ick", 987 .addr = omap3xxx_timer9_addrs, 988 .user = OCP_USER_MPU | OCP_USER_SDMA, 989 }; 990 991 /* timer9 slave port */ 992 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { 993 &omap3xxx_l4_per__timer9, 994 }; 995 996 /* timer9 hwmod */ 997 static struct omap_hwmod omap3xxx_timer9_hwmod = { 998 .name = "timer9", 999 .mpu_irqs = omap2_timer9_mpu_irqs, 1000 .main_clk = "gpt9_fck", 1001 .prcm = { 1002 .omap2 = { 1003 .prcm_reg_id = 1, 1004 .module_bit = OMAP3430_EN_GPT9_SHIFT, 1005 .module_offs = OMAP3430_PER_MOD, 1006 .idlest_reg_id = 1, 1007 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 1008 }, 1009 }, 1010 .dev_attr = &capability_pwm_dev_attr, 1011 .slaves = omap3xxx_timer9_slaves, 1012 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), 1013 .class = &omap3xxx_timer_hwmod_class, 1014 }; 1015 1016 /* timer10 */ 1017 static struct omap_hwmod omap3xxx_timer10_hwmod; 1018 1019 /* l4_core -> timer10 */ 1020 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 1021 .master = &omap3xxx_l4_core_hwmod, 1022 .slave = &omap3xxx_timer10_hwmod, 1023 .clk = "gpt10_ick", 1024 .addr = omap2_timer10_addrs, 1025 .user = OCP_USER_MPU | OCP_USER_SDMA, 1026 }; 1027 1028 /* timer10 slave port */ 1029 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { 1030 &omap3xxx_l4_core__timer10, 1031 }; 1032 1033 /* timer10 hwmod */ 1034 static struct omap_hwmod omap3xxx_timer10_hwmod = { 1035 .name = "timer10", 1036 .mpu_irqs = omap2_timer10_mpu_irqs, 1037 .main_clk = "gpt10_fck", 1038 .prcm = { 1039 .omap2 = { 1040 .prcm_reg_id = 1, 1041 .module_bit = OMAP3430_EN_GPT10_SHIFT, 1042 .module_offs = CORE_MOD, 1043 .idlest_reg_id = 1, 1044 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 1045 }, 1046 }, 1047 .dev_attr = &capability_pwm_dev_attr, 1048 .slaves = omap3xxx_timer10_slaves, 1049 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), 1050 .class = &omap3xxx_timer_1ms_hwmod_class, 1051 }; 1052 1053 /* timer11 */ 1054 static struct omap_hwmod omap3xxx_timer11_hwmod; 1055 1056 /* l4_core -> timer11 */ 1057 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 1058 .master = &omap3xxx_l4_core_hwmod, 1059 .slave = &omap3xxx_timer11_hwmod, 1060 .clk = "gpt11_ick", 1061 .addr = omap2_timer11_addrs, 1062 .user = OCP_USER_MPU | OCP_USER_SDMA, 1063 }; 1064 1065 /* timer11 slave port */ 1066 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { 1067 &omap3xxx_l4_core__timer11, 1068 }; 1069 1070 /* timer11 hwmod */ 1071 static struct omap_hwmod omap3xxx_timer11_hwmod = { 1072 .name = "timer11", 1073 .mpu_irqs = omap2_timer11_mpu_irqs, 1074 .main_clk = "gpt11_fck", 1075 .prcm = { 1076 .omap2 = { 1077 .prcm_reg_id = 1, 1078 .module_bit = OMAP3430_EN_GPT11_SHIFT, 1079 .module_offs = CORE_MOD, 1080 .idlest_reg_id = 1, 1081 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 1082 }, 1083 }, 1084 .dev_attr = &capability_pwm_dev_attr, 1085 .slaves = omap3xxx_timer11_slaves, 1086 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), 1087 .class = &omap3xxx_timer_hwmod_class, 1088 }; 1089 1090 /* timer12*/ 1091 static struct omap_hwmod omap3xxx_timer12_hwmod; 1092 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 1093 { .irq = 95, }, 1094 { .irq = -1 } 1095 }; 1096 1097 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 1098 { 1099 .pa_start = 0x48304000, 1100 .pa_end = 0x48304000 + SZ_1K - 1, 1101 .flags = ADDR_TYPE_RT 1102 }, 1103 { } 1104 }; 1105 1106 /* l4_core -> timer12 */ 1107 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { 1108 .master = &omap3xxx_l4_core_hwmod, 1109 .slave = &omap3xxx_timer12_hwmod, 1110 .clk = "gpt12_ick", 1111 .addr = omap3xxx_timer12_addrs, 1112 .user = OCP_USER_MPU | OCP_USER_SDMA, 1113 }; 1114 1115 /* timer12 slave port */ 1116 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { 1117 &omap3xxx_l4_core__timer12, 1118 }; 1119 1120 /* timer12 hwmod */ 1121 static struct omap_hwmod omap3xxx_timer12_hwmod = { 1122 .name = "timer12", 1123 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 1124 .main_clk = "gpt12_fck", 1125 .prcm = { 1126 .omap2 = { 1127 .prcm_reg_id = 1, 1128 .module_bit = OMAP3430_EN_GPT12_SHIFT, 1129 .module_offs = WKUP_MOD, 1130 .idlest_reg_id = 1, 1131 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 1132 }, 1133 }, 1134 .dev_attr = &capability_secure_dev_attr, 1135 .slaves = omap3xxx_timer12_slaves, 1136 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), 1137 .class = &omap3xxx_timer_hwmod_class, 1138 }; 1139 1140 /* l4_wkup -> wd_timer2 */ 1141 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 1142 { 1143 .pa_start = 0x48314000, 1144 .pa_end = 0x4831407f, 1145 .flags = ADDR_TYPE_RT 1146 }, 1147 { } 1148 }; 1149 1150 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 1151 .master = &omap3xxx_l4_wkup_hwmod, 1152 .slave = &omap3xxx_wd_timer2_hwmod, 1153 .clk = "wdt2_ick", 1154 .addr = omap3xxx_wd_timer2_addrs, 1155 .user = OCP_USER_MPU | OCP_USER_SDMA, 1156 }; 1157 1158 /* 1159 * 'wd_timer' class 1160 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 1161 * overflow condition 1162 */ 1163 1164 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 1165 .rev_offs = 0x0000, 1166 .sysc_offs = 0x0010, 1167 .syss_offs = 0x0014, 1168 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 1169 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1170 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1171 SYSS_HAS_RESET_STATUS), 1172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1173 .sysc_fields = &omap_hwmod_sysc_type1, 1174 }; 1175 1176 /* I2C common */ 1177 static struct omap_hwmod_class_sysconfig i2c_sysc = { 1178 .rev_offs = 0x00, 1179 .sysc_offs = 0x20, 1180 .syss_offs = 0x10, 1181 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1182 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1183 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1185 .clockact = CLOCKACT_TEST_ICLK, 1186 .sysc_fields = &omap_hwmod_sysc_type1, 1187 }; 1188 1189 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 1190 .name = "wd_timer", 1191 .sysc = &omap3xxx_wd_timer_sysc, 1192 .pre_shutdown = &omap2_wd_timer_disable 1193 }; 1194 1195 /* wd_timer2 */ 1196 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { 1197 &omap3xxx_l4_wkup__wd_timer2, 1198 }; 1199 1200 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 1201 .name = "wd_timer2", 1202 .class = &omap3xxx_wd_timer_hwmod_class, 1203 .main_clk = "wdt2_fck", 1204 .prcm = { 1205 .omap2 = { 1206 .prcm_reg_id = 1, 1207 .module_bit = OMAP3430_EN_WDT2_SHIFT, 1208 .module_offs = WKUP_MOD, 1209 .idlest_reg_id = 1, 1210 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 1211 }, 1212 }, 1213 .slaves = omap3xxx_wd_timer2_slaves, 1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), 1215 /* 1216 * XXX: Use software supervised mode, HW supervised smartidle seems to 1217 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 1218 */ 1219 .flags = HWMOD_SWSUP_SIDLE, 1220 }; 1221 1222 /* UART1 */ 1223 1224 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 1225 &omap3_l4_core__uart1, 1226 }; 1227 1228 static struct omap_hwmod omap3xxx_uart1_hwmod = { 1229 .name = "uart1", 1230 .mpu_irqs = omap2_uart1_mpu_irqs, 1231 .sdma_reqs = omap2_uart1_sdma_reqs, 1232 .main_clk = "uart1_fck", 1233 .prcm = { 1234 .omap2 = { 1235 .module_offs = CORE_MOD, 1236 .prcm_reg_id = 1, 1237 .module_bit = OMAP3430_EN_UART1_SHIFT, 1238 .idlest_reg_id = 1, 1239 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 1240 }, 1241 }, 1242 .slaves = omap3xxx_uart1_slaves, 1243 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 1244 .class = &omap2_uart_class, 1245 }; 1246 1247 /* UART2 */ 1248 1249 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { 1250 &omap3_l4_core__uart2, 1251 }; 1252 1253 static struct omap_hwmod omap3xxx_uart2_hwmod = { 1254 .name = "uart2", 1255 .mpu_irqs = omap2_uart2_mpu_irqs, 1256 .sdma_reqs = omap2_uart2_sdma_reqs, 1257 .main_clk = "uart2_fck", 1258 .prcm = { 1259 .omap2 = { 1260 .module_offs = CORE_MOD, 1261 .prcm_reg_id = 1, 1262 .module_bit = OMAP3430_EN_UART2_SHIFT, 1263 .idlest_reg_id = 1, 1264 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 1265 }, 1266 }, 1267 .slaves = omap3xxx_uart2_slaves, 1268 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 1269 .class = &omap2_uart_class, 1270 }; 1271 1272 /* UART3 */ 1273 1274 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { 1275 &omap3_l4_per__uart3, 1276 }; 1277 1278 static struct omap_hwmod omap3xxx_uart3_hwmod = { 1279 .name = "uart3", 1280 .mpu_irqs = omap2_uart3_mpu_irqs, 1281 .sdma_reqs = omap2_uart3_sdma_reqs, 1282 .main_clk = "uart3_fck", 1283 .prcm = { 1284 .omap2 = { 1285 .module_offs = OMAP3430_PER_MOD, 1286 .prcm_reg_id = 1, 1287 .module_bit = OMAP3430_EN_UART3_SHIFT, 1288 .idlest_reg_id = 1, 1289 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 1290 }, 1291 }, 1292 .slaves = omap3xxx_uart3_slaves, 1293 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 1294 .class = &omap2_uart_class, 1295 }; 1296 1297 /* UART4 */ 1298 1299 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 1300 { .irq = INT_36XX_UART4_IRQ, }, 1301 { .irq = -1 } 1302 }; 1303 1304 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 1305 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 1306 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 1307 { .dma_req = -1 } 1308 }; 1309 1310 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 1311 &omap3_l4_per__uart4, 1312 }; 1313 1314 static struct omap_hwmod omap3xxx_uart4_hwmod = { 1315 .name = "uart4", 1316 .mpu_irqs = uart4_mpu_irqs, 1317 .sdma_reqs = uart4_sdma_reqs, 1318 .main_clk = "uart4_fck", 1319 .prcm = { 1320 .omap2 = { 1321 .module_offs = OMAP3430_PER_MOD, 1322 .prcm_reg_id = 1, 1323 .module_bit = OMAP3630_EN_UART4_SHIFT, 1324 .idlest_reg_id = 1, 1325 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 1326 }, 1327 }, 1328 .slaves = omap3xxx_uart4_slaves, 1329 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 1330 .class = &omap2_uart_class, 1331 }; 1332 1333 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 1334 { .irq = INT_35XX_UART4_IRQ, }, 1335 }; 1336 1337 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 1338 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, 1339 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 1340 }; 1341 1342 static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { 1343 &am35xx_l4_core__uart4, 1344 }; 1345 1346 static struct omap_hwmod am35xx_uart4_hwmod = { 1347 .name = "uart4", 1348 .mpu_irqs = am35xx_uart4_mpu_irqs, 1349 .sdma_reqs = am35xx_uart4_sdma_reqs, 1350 .main_clk = "uart4_fck", 1351 .prcm = { 1352 .omap2 = { 1353 .module_offs = CORE_MOD, 1354 .prcm_reg_id = 1, 1355 .module_bit = OMAP3430_EN_UART4_SHIFT, 1356 .idlest_reg_id = 1, 1357 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, 1358 }, 1359 }, 1360 .slaves = am35xx_uart4_slaves, 1361 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), 1362 .class = &omap2_uart_class, 1363 }; 1364 1365 1366 static struct omap_hwmod_class i2c_class = { 1367 .name = "i2c", 1368 .sysc = &i2c_sysc, 1369 .rev = OMAP_I2C_IP_VERSION_1, 1370 .reset = &omap_i2c_reset, 1371 }; 1372 1373 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 1374 { .name = "dispc", .dma_req = 5 }, 1375 { .name = "dsi1", .dma_req = 74 }, 1376 { .dma_req = -1 } 1377 }; 1378 1379 /* dss */ 1380 /* dss master ports */ 1381 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { 1382 &omap3xxx_dss__l3, 1383 }; 1384 1385 /* l4_core -> dss */ 1386 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 1387 .master = &omap3xxx_l4_core_hwmod, 1388 .slave = &omap3430es1_dss_core_hwmod, 1389 .clk = "dss_ick", 1390 .addr = omap2_dss_addrs, 1391 .fw = { 1392 .omap2 = { 1393 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 1394 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1395 .flags = OMAP_FIREWALL_L4, 1396 } 1397 }, 1398 .user = OCP_USER_MPU | OCP_USER_SDMA, 1399 }; 1400 1401 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 1402 .master = &omap3xxx_l4_core_hwmod, 1403 .slave = &omap3xxx_dss_core_hwmod, 1404 .clk = "dss_ick", 1405 .addr = omap2_dss_addrs, 1406 .fw = { 1407 .omap2 = { 1408 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 1409 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1410 .flags = OMAP_FIREWALL_L4, 1411 } 1412 }, 1413 .user = OCP_USER_MPU | OCP_USER_SDMA, 1414 }; 1415 1416 /* dss slave ports */ 1417 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { 1418 &omap3430es1_l4_core__dss, 1419 }; 1420 1421 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { 1422 &omap3xxx_l4_core__dss, 1423 }; 1424 1425 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1426 /* 1427 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 1428 * driver does not use these clocks. 1429 */ 1430 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 1431 { .role = "tv_clk", .clk = "dss_tv_fck" }, 1432 /* required only on OMAP3430 */ 1433 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 1434 }; 1435 1436 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1437 .name = "dss_core", 1438 .class = &omap2_dss_hwmod_class, 1439 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1440 .sdma_reqs = omap3xxx_dss_sdma_chs, 1441 .prcm = { 1442 .omap2 = { 1443 .prcm_reg_id = 1, 1444 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1445 .module_offs = OMAP3430_DSS_MOD, 1446 .idlest_reg_id = 1, 1447 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 1448 }, 1449 }, 1450 .opt_clks = dss_opt_clks, 1451 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 1452 .slaves = omap3430es1_dss_slaves, 1453 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), 1454 .masters = omap3xxx_dss_masters, 1455 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), 1456 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1457 }; 1458 1459 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1460 .name = "dss_core", 1461 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1462 .class = &omap2_dss_hwmod_class, 1463 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1464 .sdma_reqs = omap3xxx_dss_sdma_chs, 1465 .prcm = { 1466 .omap2 = { 1467 .prcm_reg_id = 1, 1468 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1469 .module_offs = OMAP3430_DSS_MOD, 1470 .idlest_reg_id = 1, 1471 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 1472 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 1473 }, 1474 }, 1475 .opt_clks = dss_opt_clks, 1476 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 1477 .slaves = omap3xxx_dss_slaves, 1478 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), 1479 .masters = omap3xxx_dss_masters, 1480 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), 1481 }; 1482 1483 /* 1484 * 'dispc' class 1485 * display controller 1486 */ 1487 1488 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 1489 .rev_offs = 0x0000, 1490 .sysc_offs = 0x0010, 1491 .syss_offs = 0x0014, 1492 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 1493 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1494 SYSC_HAS_ENAWAKEUP), 1495 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1496 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1497 .sysc_fields = &omap_hwmod_sysc_type1, 1498 }; 1499 1500 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 1501 .name = "dispc", 1502 .sysc = &omap3_dispc_sysc, 1503 }; 1504 1505 /* l4_core -> dss_dispc */ 1506 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1507 .master = &omap3xxx_l4_core_hwmod, 1508 .slave = &omap3xxx_dss_dispc_hwmod, 1509 .clk = "dss_ick", 1510 .addr = omap2_dss_dispc_addrs, 1511 .fw = { 1512 .omap2 = { 1513 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 1514 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1515 .flags = OMAP_FIREWALL_L4, 1516 } 1517 }, 1518 .user = OCP_USER_MPU | OCP_USER_SDMA, 1519 }; 1520 1521 /* dss_dispc slave ports */ 1522 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { 1523 &omap3xxx_l4_core__dss_dispc, 1524 }; 1525 1526 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1527 .name = "dss_dispc", 1528 .class = &omap3_dispc_hwmod_class, 1529 .mpu_irqs = omap2_dispc_irqs, 1530 .main_clk = "dss1_alwon_fck", 1531 .prcm = { 1532 .omap2 = { 1533 .prcm_reg_id = 1, 1534 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1535 .module_offs = OMAP3430_DSS_MOD, 1536 }, 1537 }, 1538 .slaves = omap3xxx_dss_dispc_slaves, 1539 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), 1540 .flags = HWMOD_NO_IDLEST, 1541 .dev_attr = &omap2_3_dss_dispc_dev_attr 1542 }; 1543 1544 /* 1545 * 'dsi' class 1546 * display serial interface controller 1547 */ 1548 1549 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 1550 .name = "dsi", 1551 }; 1552 1553 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 1554 { .irq = 25 }, 1555 { .irq = -1 } 1556 }; 1557 1558 /* dss_dsi1 */ 1559 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { 1560 { 1561 .pa_start = 0x4804FC00, 1562 .pa_end = 0x4804FFFF, 1563 .flags = ADDR_TYPE_RT 1564 }, 1565 { } 1566 }; 1567 1568 /* l4_core -> dss_dsi1 */ 1569 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 1570 .master = &omap3xxx_l4_core_hwmod, 1571 .slave = &omap3xxx_dss_dsi1_hwmod, 1572 .clk = "dss_ick", 1573 .addr = omap3xxx_dss_dsi1_addrs, 1574 .fw = { 1575 .omap2 = { 1576 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 1577 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1578 .flags = OMAP_FIREWALL_L4, 1579 } 1580 }, 1581 .user = OCP_USER_MPU | OCP_USER_SDMA, 1582 }; 1583 1584 /* dss_dsi1 slave ports */ 1585 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { 1586 &omap3xxx_l4_core__dss_dsi1, 1587 }; 1588 1589 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 1590 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 1591 }; 1592 1593 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 1594 .name = "dss_dsi1", 1595 .class = &omap3xxx_dsi_hwmod_class, 1596 .mpu_irqs = omap3xxx_dsi1_irqs, 1597 .main_clk = "dss1_alwon_fck", 1598 .prcm = { 1599 .omap2 = { 1600 .prcm_reg_id = 1, 1601 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1602 .module_offs = OMAP3430_DSS_MOD, 1603 }, 1604 }, 1605 .opt_clks = dss_dsi1_opt_clks, 1606 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 1607 .slaves = omap3xxx_dss_dsi1_slaves, 1608 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), 1609 .flags = HWMOD_NO_IDLEST, 1610 }; 1611 1612 /* l4_core -> dss_rfbi */ 1613 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1614 .master = &omap3xxx_l4_core_hwmod, 1615 .slave = &omap3xxx_dss_rfbi_hwmod, 1616 .clk = "dss_ick", 1617 .addr = omap2_dss_rfbi_addrs, 1618 .fw = { 1619 .omap2 = { 1620 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 1621 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 1622 .flags = OMAP_FIREWALL_L4, 1623 } 1624 }, 1625 .user = OCP_USER_MPU | OCP_USER_SDMA, 1626 }; 1627 1628 /* dss_rfbi slave ports */ 1629 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { 1630 &omap3xxx_l4_core__dss_rfbi, 1631 }; 1632 1633 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 1634 { .role = "ick", .clk = "dss_ick" }, 1635 }; 1636 1637 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1638 .name = "dss_rfbi", 1639 .class = &omap2_rfbi_hwmod_class, 1640 .main_clk = "dss1_alwon_fck", 1641 .prcm = { 1642 .omap2 = { 1643 .prcm_reg_id = 1, 1644 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1645 .module_offs = OMAP3430_DSS_MOD, 1646 }, 1647 }, 1648 .opt_clks = dss_rfbi_opt_clks, 1649 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 1650 .slaves = omap3xxx_dss_rfbi_slaves, 1651 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), 1652 .flags = HWMOD_NO_IDLEST, 1653 }; 1654 1655 /* l4_core -> dss_venc */ 1656 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1657 .master = &omap3xxx_l4_core_hwmod, 1658 .slave = &omap3xxx_dss_venc_hwmod, 1659 .clk = "dss_ick", 1660 .addr = omap2_dss_venc_addrs, 1661 .fw = { 1662 .omap2 = { 1663 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 1664 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 1665 .flags = OMAP_FIREWALL_L4, 1666 } 1667 }, 1668 .flags = OCPIF_SWSUP_IDLE, 1669 .user = OCP_USER_MPU | OCP_USER_SDMA, 1670 }; 1671 1672 /* dss_venc slave ports */ 1673 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { 1674 &omap3xxx_l4_core__dss_venc, 1675 }; 1676 1677 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 1678 /* required only on OMAP3430 */ 1679 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 1680 }; 1681 1682 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1683 .name = "dss_venc", 1684 .class = &omap2_venc_hwmod_class, 1685 .main_clk = "dss_tv_fck", 1686 .prcm = { 1687 .omap2 = { 1688 .prcm_reg_id = 1, 1689 .module_bit = OMAP3430_EN_DSS1_SHIFT, 1690 .module_offs = OMAP3430_DSS_MOD, 1691 }, 1692 }, 1693 .opt_clks = dss_venc_opt_clks, 1694 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 1695 .slaves = omap3xxx_dss_venc_slaves, 1696 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), 1697 .flags = HWMOD_NO_IDLEST, 1698 }; 1699 1700 /* I2C1 */ 1701 1702 static struct omap_i2c_dev_attr i2c1_dev_attr = { 1703 .fifo_depth = 8, /* bytes */ 1704 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1705 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 1706 OMAP_I2C_FLAG_BUS_SHIFT_2, 1707 }; 1708 1709 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { 1710 &omap3_l4_core__i2c1, 1711 }; 1712 1713 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 1714 .name = "i2c1", 1715 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1716 .mpu_irqs = omap2_i2c1_mpu_irqs, 1717 .sdma_reqs = omap2_i2c1_sdma_reqs, 1718 .main_clk = "i2c1_fck", 1719 .prcm = { 1720 .omap2 = { 1721 .module_offs = CORE_MOD, 1722 .prcm_reg_id = 1, 1723 .module_bit = OMAP3430_EN_I2C1_SHIFT, 1724 .idlest_reg_id = 1, 1725 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 1726 }, 1727 }, 1728 .slaves = omap3xxx_i2c1_slaves, 1729 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), 1730 .class = &i2c_class, 1731 .dev_attr = &i2c1_dev_attr, 1732 }; 1733 1734 /* I2C2 */ 1735 1736 static struct omap_i2c_dev_attr i2c2_dev_attr = { 1737 .fifo_depth = 8, /* bytes */ 1738 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1739 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 1740 OMAP_I2C_FLAG_BUS_SHIFT_2, 1741 }; 1742 1743 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { 1744 &omap3_l4_core__i2c2, 1745 }; 1746 1747 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 1748 .name = "i2c2", 1749 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1750 .mpu_irqs = omap2_i2c2_mpu_irqs, 1751 .sdma_reqs = omap2_i2c2_sdma_reqs, 1752 .main_clk = "i2c2_fck", 1753 .prcm = { 1754 .omap2 = { 1755 .module_offs = CORE_MOD, 1756 .prcm_reg_id = 1, 1757 .module_bit = OMAP3430_EN_I2C2_SHIFT, 1758 .idlest_reg_id = 1, 1759 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 1760 }, 1761 }, 1762 .slaves = omap3xxx_i2c2_slaves, 1763 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), 1764 .class = &i2c_class, 1765 .dev_attr = &i2c2_dev_attr, 1766 }; 1767 1768 /* I2C3 */ 1769 1770 static struct omap_i2c_dev_attr i2c3_dev_attr = { 1771 .fifo_depth = 64, /* bytes */ 1772 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1773 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | 1774 OMAP_I2C_FLAG_BUS_SHIFT_2, 1775 }; 1776 1777 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 1778 { .irq = INT_34XX_I2C3_IRQ, }, 1779 { .irq = -1 } 1780 }; 1781 1782 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 1783 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 1784 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 1785 { .dma_req = -1 } 1786 }; 1787 1788 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { 1789 &omap3_l4_core__i2c3, 1790 }; 1791 1792 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 1793 .name = "i2c3", 1794 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1795 .mpu_irqs = i2c3_mpu_irqs, 1796 .sdma_reqs = i2c3_sdma_reqs, 1797 .main_clk = "i2c3_fck", 1798 .prcm = { 1799 .omap2 = { 1800 .module_offs = CORE_MOD, 1801 .prcm_reg_id = 1, 1802 .module_bit = OMAP3430_EN_I2C3_SHIFT, 1803 .idlest_reg_id = 1, 1804 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 1805 }, 1806 }, 1807 .slaves = omap3xxx_i2c3_slaves, 1808 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), 1809 .class = &i2c_class, 1810 .dev_attr = &i2c3_dev_attr, 1811 }; 1812 1813 /* l4_wkup -> gpio1 */ 1814 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { 1815 { 1816 .pa_start = 0x48310000, 1817 .pa_end = 0x483101ff, 1818 .flags = ADDR_TYPE_RT 1819 }, 1820 { } 1821 }; 1822 1823 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 1824 .master = &omap3xxx_l4_wkup_hwmod, 1825 .slave = &omap3xxx_gpio1_hwmod, 1826 .addr = omap3xxx_gpio1_addrs, 1827 .user = OCP_USER_MPU | OCP_USER_SDMA, 1828 }; 1829 1830 /* l4_per -> gpio2 */ 1831 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { 1832 { 1833 .pa_start = 0x49050000, 1834 .pa_end = 0x490501ff, 1835 .flags = ADDR_TYPE_RT 1836 }, 1837 { } 1838 }; 1839 1840 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 1841 .master = &omap3xxx_l4_per_hwmod, 1842 .slave = &omap3xxx_gpio2_hwmod, 1843 .addr = omap3xxx_gpio2_addrs, 1844 .user = OCP_USER_MPU | OCP_USER_SDMA, 1845 }; 1846 1847 /* l4_per -> gpio3 */ 1848 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { 1849 { 1850 .pa_start = 0x49052000, 1851 .pa_end = 0x490521ff, 1852 .flags = ADDR_TYPE_RT 1853 }, 1854 { } 1855 }; 1856 1857 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 1858 .master = &omap3xxx_l4_per_hwmod, 1859 .slave = &omap3xxx_gpio3_hwmod, 1860 .addr = omap3xxx_gpio3_addrs, 1861 .user = OCP_USER_MPU | OCP_USER_SDMA, 1862 }; 1863 1864 /* l4_per -> gpio4 */ 1865 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { 1866 { 1867 .pa_start = 0x49054000, 1868 .pa_end = 0x490541ff, 1869 .flags = ADDR_TYPE_RT 1870 }, 1871 { } 1872 }; 1873 1874 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 1875 .master = &omap3xxx_l4_per_hwmod, 1876 .slave = &omap3xxx_gpio4_hwmod, 1877 .addr = omap3xxx_gpio4_addrs, 1878 .user = OCP_USER_MPU | OCP_USER_SDMA, 1879 }; 1880 1881 /* l4_per -> gpio5 */ 1882 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { 1883 { 1884 .pa_start = 0x49056000, 1885 .pa_end = 0x490561ff, 1886 .flags = ADDR_TYPE_RT 1887 }, 1888 { } 1889 }; 1890 1891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 1892 .master = &omap3xxx_l4_per_hwmod, 1893 .slave = &omap3xxx_gpio5_hwmod, 1894 .addr = omap3xxx_gpio5_addrs, 1895 .user = OCP_USER_MPU | OCP_USER_SDMA, 1896 }; 1897 1898 /* l4_per -> gpio6 */ 1899 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { 1900 { 1901 .pa_start = 0x49058000, 1902 .pa_end = 0x490581ff, 1903 .flags = ADDR_TYPE_RT 1904 }, 1905 { } 1906 }; 1907 1908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 1909 .master = &omap3xxx_l4_per_hwmod, 1910 .slave = &omap3xxx_gpio6_hwmod, 1911 .addr = omap3xxx_gpio6_addrs, 1912 .user = OCP_USER_MPU | OCP_USER_SDMA, 1913 }; 1914 1915 /* 1916 * 'gpio' class 1917 * general purpose io module 1918 */ 1919 1920 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 1921 .rev_offs = 0x0000, 1922 .sysc_offs = 0x0010, 1923 .syss_offs = 0x0014, 1924 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1925 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1926 SYSS_HAS_RESET_STATUS), 1927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1928 .sysc_fields = &omap_hwmod_sysc_type1, 1929 }; 1930 1931 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 1932 .name = "gpio", 1933 .sysc = &omap3xxx_gpio_sysc, 1934 .rev = 1, 1935 }; 1936 1937 /* gpio_dev_attr*/ 1938 static struct omap_gpio_dev_attr gpio_dev_attr = { 1939 .bank_width = 32, 1940 .dbck_flag = true, 1941 }; 1942 1943 /* gpio1 */ 1944 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1945 { .role = "dbclk", .clk = "gpio1_dbck", }, 1946 }; 1947 1948 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { 1949 &omap3xxx_l4_wkup__gpio1, 1950 }; 1951 1952 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 1953 .name = "gpio1", 1954 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1955 .mpu_irqs = omap2_gpio1_irqs, 1956 .main_clk = "gpio1_ick", 1957 .opt_clks = gpio1_opt_clks, 1958 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1959 .prcm = { 1960 .omap2 = { 1961 .prcm_reg_id = 1, 1962 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 1963 .module_offs = WKUP_MOD, 1964 .idlest_reg_id = 1, 1965 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 1966 }, 1967 }, 1968 .slaves = omap3xxx_gpio1_slaves, 1969 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), 1970 .class = &omap3xxx_gpio_hwmod_class, 1971 .dev_attr = &gpio_dev_attr, 1972 }; 1973 1974 /* gpio2 */ 1975 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1976 { .role = "dbclk", .clk = "gpio2_dbck", }, 1977 }; 1978 1979 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { 1980 &omap3xxx_l4_per__gpio2, 1981 }; 1982 1983 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 1984 .name = "gpio2", 1985 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1986 .mpu_irqs = omap2_gpio2_irqs, 1987 .main_clk = "gpio2_ick", 1988 .opt_clks = gpio2_opt_clks, 1989 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1990 .prcm = { 1991 .omap2 = { 1992 .prcm_reg_id = 1, 1993 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 1994 .module_offs = OMAP3430_PER_MOD, 1995 .idlest_reg_id = 1, 1996 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 1997 }, 1998 }, 1999 .slaves = omap3xxx_gpio2_slaves, 2000 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), 2001 .class = &omap3xxx_gpio_hwmod_class, 2002 .dev_attr = &gpio_dev_attr, 2003 }; 2004 2005 /* gpio3 */ 2006 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 2007 { .role = "dbclk", .clk = "gpio3_dbck", }, 2008 }; 2009 2010 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { 2011 &omap3xxx_l4_per__gpio3, 2012 }; 2013 2014 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 2015 .name = "gpio3", 2016 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2017 .mpu_irqs = omap2_gpio3_irqs, 2018 .main_clk = "gpio3_ick", 2019 .opt_clks = gpio3_opt_clks, 2020 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 2021 .prcm = { 2022 .omap2 = { 2023 .prcm_reg_id = 1, 2024 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 2025 .module_offs = OMAP3430_PER_MOD, 2026 .idlest_reg_id = 1, 2027 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 2028 }, 2029 }, 2030 .slaves = omap3xxx_gpio3_slaves, 2031 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), 2032 .class = &omap3xxx_gpio_hwmod_class, 2033 .dev_attr = &gpio_dev_attr, 2034 }; 2035 2036 /* gpio4 */ 2037 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 2038 { .role = "dbclk", .clk = "gpio4_dbck", }, 2039 }; 2040 2041 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { 2042 &omap3xxx_l4_per__gpio4, 2043 }; 2044 2045 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 2046 .name = "gpio4", 2047 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2048 .mpu_irqs = omap2_gpio4_irqs, 2049 .main_clk = "gpio4_ick", 2050 .opt_clks = gpio4_opt_clks, 2051 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 2052 .prcm = { 2053 .omap2 = { 2054 .prcm_reg_id = 1, 2055 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 2056 .module_offs = OMAP3430_PER_MOD, 2057 .idlest_reg_id = 1, 2058 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 2059 }, 2060 }, 2061 .slaves = omap3xxx_gpio4_slaves, 2062 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), 2063 .class = &omap3xxx_gpio_hwmod_class, 2064 .dev_attr = &gpio_dev_attr, 2065 }; 2066 2067 /* gpio5 */ 2068 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 2069 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ 2070 { .irq = -1 } 2071 }; 2072 2073 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 2074 { .role = "dbclk", .clk = "gpio5_dbck", }, 2075 }; 2076 2077 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { 2078 &omap3xxx_l4_per__gpio5, 2079 }; 2080 2081 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 2082 .name = "gpio5", 2083 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2084 .mpu_irqs = omap3xxx_gpio5_irqs, 2085 .main_clk = "gpio5_ick", 2086 .opt_clks = gpio5_opt_clks, 2087 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 2088 .prcm = { 2089 .omap2 = { 2090 .prcm_reg_id = 1, 2091 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 2092 .module_offs = OMAP3430_PER_MOD, 2093 .idlest_reg_id = 1, 2094 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 2095 }, 2096 }, 2097 .slaves = omap3xxx_gpio5_slaves, 2098 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), 2099 .class = &omap3xxx_gpio_hwmod_class, 2100 .dev_attr = &gpio_dev_attr, 2101 }; 2102 2103 /* gpio6 */ 2104 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 2105 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ 2106 { .irq = -1 } 2107 }; 2108 2109 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 2110 { .role = "dbclk", .clk = "gpio6_dbck", }, 2111 }; 2112 2113 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { 2114 &omap3xxx_l4_per__gpio6, 2115 }; 2116 2117 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 2118 .name = "gpio6", 2119 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2120 .mpu_irqs = omap3xxx_gpio6_irqs, 2121 .main_clk = "gpio6_ick", 2122 .opt_clks = gpio6_opt_clks, 2123 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 2124 .prcm = { 2125 .omap2 = { 2126 .prcm_reg_id = 1, 2127 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 2128 .module_offs = OMAP3430_PER_MOD, 2129 .idlest_reg_id = 1, 2130 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 2131 }, 2132 }, 2133 .slaves = omap3xxx_gpio6_slaves, 2134 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), 2135 .class = &omap3xxx_gpio_hwmod_class, 2136 .dev_attr = &gpio_dev_attr, 2137 }; 2138 2139 /* dma_system -> L3 */ 2140 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 2141 .master = &omap3xxx_dma_system_hwmod, 2142 .slave = &omap3xxx_l3_main_hwmod, 2143 .clk = "core_l3_ick", 2144 .user = OCP_USER_MPU | OCP_USER_SDMA, 2145 }; 2146 2147 /* dma attributes */ 2148 static struct omap_dma_dev_attr dma_dev_attr = { 2149 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 2150 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 2151 .lch_count = 32, 2152 }; 2153 2154 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 2155 .rev_offs = 0x0000, 2156 .sysc_offs = 0x002c, 2157 .syss_offs = 0x0028, 2158 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2159 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 2160 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 2161 SYSS_HAS_RESET_STATUS), 2162 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2163 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 2164 .sysc_fields = &omap_hwmod_sysc_type1, 2165 }; 2166 2167 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 2168 .name = "dma", 2169 .sysc = &omap3xxx_dma_sysc, 2170 }; 2171 2172 /* dma_system */ 2173 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 2174 { 2175 .pa_start = 0x48056000, 2176 .pa_end = 0x48056fff, 2177 .flags = ADDR_TYPE_RT 2178 }, 2179 { } 2180 }; 2181 2182 /* dma_system master ports */ 2183 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { 2184 &omap3xxx_dma_system__l3, 2185 }; 2186 2187 /* l4_cfg -> dma_system */ 2188 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 2189 .master = &omap3xxx_l4_core_hwmod, 2190 .slave = &omap3xxx_dma_system_hwmod, 2191 .clk = "core_l4_ick", 2192 .addr = omap3xxx_dma_system_addrs, 2193 .user = OCP_USER_MPU | OCP_USER_SDMA, 2194 }; 2195 2196 /* dma_system slave ports */ 2197 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { 2198 &omap3xxx_l4_core__dma_system, 2199 }; 2200 2201 static struct omap_hwmod omap3xxx_dma_system_hwmod = { 2202 .name = "dma", 2203 .class = &omap3xxx_dma_hwmod_class, 2204 .mpu_irqs = omap2_dma_system_irqs, 2205 .main_clk = "core_l3_ick", 2206 .prcm = { 2207 .omap2 = { 2208 .module_offs = CORE_MOD, 2209 .prcm_reg_id = 1, 2210 .module_bit = OMAP3430_ST_SDMA_SHIFT, 2211 .idlest_reg_id = 1, 2212 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 2213 }, 2214 }, 2215 .slaves = omap3xxx_dma_system_slaves, 2216 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), 2217 .masters = omap3xxx_dma_system_masters, 2218 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), 2219 .dev_attr = &dma_dev_attr, 2220 .flags = HWMOD_NO_IDLEST, 2221 }; 2222 2223 /* 2224 * 'mcbsp' class 2225 * multi channel buffered serial port controller 2226 */ 2227 2228 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 2229 .sysc_offs = 0x008c, 2230 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 2231 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2232 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2233 .sysc_fields = &omap_hwmod_sysc_type1, 2234 .clockact = 0x2, 2235 }; 2236 2237 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 2238 .name = "mcbsp", 2239 .sysc = &omap3xxx_mcbsp_sysc, 2240 .rev = MCBSP_CONFIG_TYPE3, 2241 }; 2242 2243 /* mcbsp1 */ 2244 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 2245 { .name = "irq", .irq = 16 }, 2246 { .name = "tx", .irq = 59 }, 2247 { .name = "rx", .irq = 60 }, 2248 { .irq = -1 } 2249 }; 2250 2251 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 2252 { 2253 .name = "mpu", 2254 .pa_start = 0x48074000, 2255 .pa_end = 0x480740ff, 2256 .flags = ADDR_TYPE_RT 2257 }, 2258 { } 2259 }; 2260 2261 /* l4_core -> mcbsp1 */ 2262 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 2263 .master = &omap3xxx_l4_core_hwmod, 2264 .slave = &omap3xxx_mcbsp1_hwmod, 2265 .clk = "mcbsp1_ick", 2266 .addr = omap3xxx_mcbsp1_addrs, 2267 .user = OCP_USER_MPU | OCP_USER_SDMA, 2268 }; 2269 2270 /* mcbsp1 slave ports */ 2271 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { 2272 &omap3xxx_l4_core__mcbsp1, 2273 }; 2274 2275 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 2276 .name = "mcbsp1", 2277 .class = &omap3xxx_mcbsp_hwmod_class, 2278 .mpu_irqs = omap3xxx_mcbsp1_irqs, 2279 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 2280 .main_clk = "mcbsp1_fck", 2281 .prcm = { 2282 .omap2 = { 2283 .prcm_reg_id = 1, 2284 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 2285 .module_offs = CORE_MOD, 2286 .idlest_reg_id = 1, 2287 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 2288 }, 2289 }, 2290 .slaves = omap3xxx_mcbsp1_slaves, 2291 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), 2292 }; 2293 2294 /* mcbsp2 */ 2295 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 2296 { .name = "irq", .irq = 17 }, 2297 { .name = "tx", .irq = 62 }, 2298 { .name = "rx", .irq = 63 }, 2299 { .irq = -1 } 2300 }; 2301 2302 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 2303 { 2304 .name = "mpu", 2305 .pa_start = 0x49022000, 2306 .pa_end = 0x490220ff, 2307 .flags = ADDR_TYPE_RT 2308 }, 2309 { } 2310 }; 2311 2312 /* l4_per -> mcbsp2 */ 2313 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2314 .master = &omap3xxx_l4_per_hwmod, 2315 .slave = &omap3xxx_mcbsp2_hwmod, 2316 .clk = "mcbsp2_ick", 2317 .addr = omap3xxx_mcbsp2_addrs, 2318 .user = OCP_USER_MPU | OCP_USER_SDMA, 2319 }; 2320 2321 /* mcbsp2 slave ports */ 2322 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { 2323 &omap3xxx_l4_per__mcbsp2, 2324 }; 2325 2326 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 2327 .sidetone = "mcbsp2_sidetone", 2328 }; 2329 2330 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 2331 .name = "mcbsp2", 2332 .class = &omap3xxx_mcbsp_hwmod_class, 2333 .mpu_irqs = omap3xxx_mcbsp2_irqs, 2334 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 2335 .main_clk = "mcbsp2_fck", 2336 .prcm = { 2337 .omap2 = { 2338 .prcm_reg_id = 1, 2339 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 2340 .module_offs = OMAP3430_PER_MOD, 2341 .idlest_reg_id = 1, 2342 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 2343 }, 2344 }, 2345 .slaves = omap3xxx_mcbsp2_slaves, 2346 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), 2347 .dev_attr = &omap34xx_mcbsp2_dev_attr, 2348 }; 2349 2350 /* mcbsp3 */ 2351 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 2352 { .name = "irq", .irq = 22 }, 2353 { .name = "tx", .irq = 89 }, 2354 { .name = "rx", .irq = 90 }, 2355 { .irq = -1 } 2356 }; 2357 2358 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 2359 { 2360 .name = "mpu", 2361 .pa_start = 0x49024000, 2362 .pa_end = 0x490240ff, 2363 .flags = ADDR_TYPE_RT 2364 }, 2365 { } 2366 }; 2367 2368 /* l4_per -> mcbsp3 */ 2369 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2370 .master = &omap3xxx_l4_per_hwmod, 2371 .slave = &omap3xxx_mcbsp3_hwmod, 2372 .clk = "mcbsp3_ick", 2373 .addr = omap3xxx_mcbsp3_addrs, 2374 .user = OCP_USER_MPU | OCP_USER_SDMA, 2375 }; 2376 2377 /* mcbsp3 slave ports */ 2378 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { 2379 &omap3xxx_l4_per__mcbsp3, 2380 }; 2381 2382 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 2383 .sidetone = "mcbsp3_sidetone", 2384 }; 2385 2386 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 2387 .name = "mcbsp3", 2388 .class = &omap3xxx_mcbsp_hwmod_class, 2389 .mpu_irqs = omap3xxx_mcbsp3_irqs, 2390 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 2391 .main_clk = "mcbsp3_fck", 2392 .prcm = { 2393 .omap2 = { 2394 .prcm_reg_id = 1, 2395 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 2396 .module_offs = OMAP3430_PER_MOD, 2397 .idlest_reg_id = 1, 2398 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 2399 }, 2400 }, 2401 .slaves = omap3xxx_mcbsp3_slaves, 2402 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), 2403 .dev_attr = &omap34xx_mcbsp3_dev_attr, 2404 }; 2405 2406 /* mcbsp4 */ 2407 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 2408 { .name = "irq", .irq = 23 }, 2409 { .name = "tx", .irq = 54 }, 2410 { .name = "rx", .irq = 55 }, 2411 { .irq = -1 } 2412 }; 2413 2414 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 2415 { .name = "rx", .dma_req = 20 }, 2416 { .name = "tx", .dma_req = 19 }, 2417 { .dma_req = -1 } 2418 }; 2419 2420 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 2421 { 2422 .name = "mpu", 2423 .pa_start = 0x49026000, 2424 .pa_end = 0x490260ff, 2425 .flags = ADDR_TYPE_RT 2426 }, 2427 { } 2428 }; 2429 2430 /* l4_per -> mcbsp4 */ 2431 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2432 .master = &omap3xxx_l4_per_hwmod, 2433 .slave = &omap3xxx_mcbsp4_hwmod, 2434 .clk = "mcbsp4_ick", 2435 .addr = omap3xxx_mcbsp4_addrs, 2436 .user = OCP_USER_MPU | OCP_USER_SDMA, 2437 }; 2438 2439 /* mcbsp4 slave ports */ 2440 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { 2441 &omap3xxx_l4_per__mcbsp4, 2442 }; 2443 2444 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 2445 .name = "mcbsp4", 2446 .class = &omap3xxx_mcbsp_hwmod_class, 2447 .mpu_irqs = omap3xxx_mcbsp4_irqs, 2448 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 2449 .main_clk = "mcbsp4_fck", 2450 .prcm = { 2451 .omap2 = { 2452 .prcm_reg_id = 1, 2453 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 2454 .module_offs = OMAP3430_PER_MOD, 2455 .idlest_reg_id = 1, 2456 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 2457 }, 2458 }, 2459 .slaves = omap3xxx_mcbsp4_slaves, 2460 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), 2461 }; 2462 2463 /* mcbsp5 */ 2464 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 2465 { .name = "irq", .irq = 27 }, 2466 { .name = "tx", .irq = 81 }, 2467 { .name = "rx", .irq = 82 }, 2468 { .irq = -1 } 2469 }; 2470 2471 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 2472 { .name = "rx", .dma_req = 22 }, 2473 { .name = "tx", .dma_req = 21 }, 2474 { .dma_req = -1 } 2475 }; 2476 2477 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 2478 { 2479 .name = "mpu", 2480 .pa_start = 0x48096000, 2481 .pa_end = 0x480960ff, 2482 .flags = ADDR_TYPE_RT 2483 }, 2484 { } 2485 }; 2486 2487 /* l4_core -> mcbsp5 */ 2488 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2489 .master = &omap3xxx_l4_core_hwmod, 2490 .slave = &omap3xxx_mcbsp5_hwmod, 2491 .clk = "mcbsp5_ick", 2492 .addr = omap3xxx_mcbsp5_addrs, 2493 .user = OCP_USER_MPU | OCP_USER_SDMA, 2494 }; 2495 2496 /* mcbsp5 slave ports */ 2497 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { 2498 &omap3xxx_l4_core__mcbsp5, 2499 }; 2500 2501 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 2502 .name = "mcbsp5", 2503 .class = &omap3xxx_mcbsp_hwmod_class, 2504 .mpu_irqs = omap3xxx_mcbsp5_irqs, 2505 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 2506 .main_clk = "mcbsp5_fck", 2507 .prcm = { 2508 .omap2 = { 2509 .prcm_reg_id = 1, 2510 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 2511 .module_offs = CORE_MOD, 2512 .idlest_reg_id = 1, 2513 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 2514 }, 2515 }, 2516 .slaves = omap3xxx_mcbsp5_slaves, 2517 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), 2518 }; 2519 /* 'mcbsp sidetone' class */ 2520 2521 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 2522 .sysc_offs = 0x0010, 2523 .sysc_flags = SYSC_HAS_AUTOIDLE, 2524 .sysc_fields = &omap_hwmod_sysc_type1, 2525 }; 2526 2527 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 2528 .name = "mcbsp_sidetone", 2529 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 2530 }; 2531 2532 /* mcbsp2_sidetone */ 2533 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 2534 { .name = "irq", .irq = 4 }, 2535 { .irq = -1 } 2536 }; 2537 2538 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 2539 { 2540 .name = "sidetone", 2541 .pa_start = 0x49028000, 2542 .pa_end = 0x490280ff, 2543 .flags = ADDR_TYPE_RT 2544 }, 2545 { } 2546 }; 2547 2548 /* l4_per -> mcbsp2_sidetone */ 2549 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2550 .master = &omap3xxx_l4_per_hwmod, 2551 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2552 .clk = "mcbsp2_ick", 2553 .addr = omap3xxx_mcbsp2_sidetone_addrs, 2554 .user = OCP_USER_MPU, 2555 }; 2556 2557 /* mcbsp2_sidetone slave ports */ 2558 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { 2559 &omap3xxx_l4_per__mcbsp2_sidetone, 2560 }; 2561 2562 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 2563 .name = "mcbsp2_sidetone", 2564 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2565 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 2566 .main_clk = "mcbsp2_fck", 2567 .prcm = { 2568 .omap2 = { 2569 .prcm_reg_id = 1, 2570 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 2571 .module_offs = OMAP3430_PER_MOD, 2572 .idlest_reg_id = 1, 2573 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 2574 }, 2575 }, 2576 .slaves = omap3xxx_mcbsp2_sidetone_slaves, 2577 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), 2578 }; 2579 2580 /* mcbsp3_sidetone */ 2581 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 2582 { .name = "irq", .irq = 5 }, 2583 { .irq = -1 } 2584 }; 2585 2586 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 2587 { 2588 .name = "sidetone", 2589 .pa_start = 0x4902A000, 2590 .pa_end = 0x4902A0ff, 2591 .flags = ADDR_TYPE_RT 2592 }, 2593 { } 2594 }; 2595 2596 /* l4_per -> mcbsp3_sidetone */ 2597 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2598 .master = &omap3xxx_l4_per_hwmod, 2599 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2600 .clk = "mcbsp3_ick", 2601 .addr = omap3xxx_mcbsp3_sidetone_addrs, 2602 .user = OCP_USER_MPU, 2603 }; 2604 2605 /* mcbsp3_sidetone slave ports */ 2606 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { 2607 &omap3xxx_l4_per__mcbsp3_sidetone, 2608 }; 2609 2610 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 2611 .name = "mcbsp3_sidetone", 2612 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2613 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 2614 .main_clk = "mcbsp3_fck", 2615 .prcm = { 2616 .omap2 = { 2617 .prcm_reg_id = 1, 2618 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 2619 .module_offs = OMAP3430_PER_MOD, 2620 .idlest_reg_id = 1, 2621 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 2622 }, 2623 }, 2624 .slaves = omap3xxx_mcbsp3_sidetone_slaves, 2625 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), 2626 }; 2627 2628 2629 /* SR common */ 2630 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 2631 .clkact_shift = 20, 2632 }; 2633 2634 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 2635 .sysc_offs = 0x24, 2636 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 2637 .clockact = CLOCKACT_TEST_ICLK, 2638 .sysc_fields = &omap34xx_sr_sysc_fields, 2639 }; 2640 2641 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 2642 .name = "smartreflex", 2643 .sysc = &omap34xx_sr_sysc, 2644 .rev = 1, 2645 }; 2646 2647 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 2648 .sidle_shift = 24, 2649 .enwkup_shift = 26 2650 }; 2651 2652 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 2653 .sysc_offs = 0x38, 2654 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2655 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 2656 SYSC_NO_CACHE), 2657 .sysc_fields = &omap36xx_sr_sysc_fields, 2658 }; 2659 2660 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 2661 .name = "smartreflex", 2662 .sysc = &omap36xx_sr_sysc, 2663 .rev = 2, 2664 }; 2665 2666 /* SR1 */ 2667 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { 2668 &omap3_l4_core__sr1, 2669 }; 2670 2671 static struct omap_hwmod omap34xx_sr1_hwmod = { 2672 .name = "sr1_hwmod", 2673 .class = &omap34xx_smartreflex_hwmod_class, 2674 .main_clk = "sr1_fck", 2675 .vdd_name = "mpu_iva", 2676 .prcm = { 2677 .omap2 = { 2678 .prcm_reg_id = 1, 2679 .module_bit = OMAP3430_EN_SR1_SHIFT, 2680 .module_offs = WKUP_MOD, 2681 .idlest_reg_id = 1, 2682 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 2683 }, 2684 }, 2685 .slaves = omap3_sr1_slaves, 2686 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), 2687 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 2688 }; 2689 2690 static struct omap_hwmod omap36xx_sr1_hwmod = { 2691 .name = "sr1_hwmod", 2692 .class = &omap36xx_smartreflex_hwmod_class, 2693 .main_clk = "sr1_fck", 2694 .vdd_name = "mpu_iva", 2695 .prcm = { 2696 .omap2 = { 2697 .prcm_reg_id = 1, 2698 .module_bit = OMAP3430_EN_SR1_SHIFT, 2699 .module_offs = WKUP_MOD, 2700 .idlest_reg_id = 1, 2701 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 2702 }, 2703 }, 2704 .slaves = omap3_sr1_slaves, 2705 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), 2706 }; 2707 2708 /* SR2 */ 2709 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { 2710 &omap3_l4_core__sr2, 2711 }; 2712 2713 static struct omap_hwmod omap34xx_sr2_hwmod = { 2714 .name = "sr2_hwmod", 2715 .class = &omap34xx_smartreflex_hwmod_class, 2716 .main_clk = "sr2_fck", 2717 .vdd_name = "core", 2718 .prcm = { 2719 .omap2 = { 2720 .prcm_reg_id = 1, 2721 .module_bit = OMAP3430_EN_SR2_SHIFT, 2722 .module_offs = WKUP_MOD, 2723 .idlest_reg_id = 1, 2724 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 2725 }, 2726 }, 2727 .slaves = omap3_sr2_slaves, 2728 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), 2729 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 2730 }; 2731 2732 static struct omap_hwmod omap36xx_sr2_hwmod = { 2733 .name = "sr2_hwmod", 2734 .class = &omap36xx_smartreflex_hwmod_class, 2735 .main_clk = "sr2_fck", 2736 .vdd_name = "core", 2737 .prcm = { 2738 .omap2 = { 2739 .prcm_reg_id = 1, 2740 .module_bit = OMAP3430_EN_SR2_SHIFT, 2741 .module_offs = WKUP_MOD, 2742 .idlest_reg_id = 1, 2743 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 2744 }, 2745 }, 2746 .slaves = omap3_sr2_slaves, 2747 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), 2748 }; 2749 2750 /* 2751 * 'mailbox' class 2752 * mailbox module allowing communication between the on-chip processors 2753 * using a queued mailbox-interrupt mechanism. 2754 */ 2755 2756 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 2757 .rev_offs = 0x000, 2758 .sysc_offs = 0x010, 2759 .syss_offs = 0x014, 2760 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2761 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2762 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2763 .sysc_fields = &omap_hwmod_sysc_type1, 2764 }; 2765 2766 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 2767 .name = "mailbox", 2768 .sysc = &omap3xxx_mailbox_sysc, 2769 }; 2770 2771 static struct omap_hwmod omap3xxx_mailbox_hwmod; 2772 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 2773 { .irq = 26 }, 2774 { .irq = -1 } 2775 }; 2776 2777 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 2778 { 2779 .pa_start = 0x48094000, 2780 .pa_end = 0x480941ff, 2781 .flags = ADDR_TYPE_RT, 2782 }, 2783 { } 2784 }; 2785 2786 /* l4_core -> mailbox */ 2787 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 2788 .master = &omap3xxx_l4_core_hwmod, 2789 .slave = &omap3xxx_mailbox_hwmod, 2790 .addr = omap3xxx_mailbox_addrs, 2791 .user = OCP_USER_MPU | OCP_USER_SDMA, 2792 }; 2793 2794 /* mailbox slave ports */ 2795 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { 2796 &omap3xxx_l4_core__mailbox, 2797 }; 2798 2799 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 2800 .name = "mailbox", 2801 .class = &omap3xxx_mailbox_hwmod_class, 2802 .mpu_irqs = omap3xxx_mailbox_irqs, 2803 .main_clk = "mailboxes_ick", 2804 .prcm = { 2805 .omap2 = { 2806 .prcm_reg_id = 1, 2807 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 2808 .module_offs = CORE_MOD, 2809 .idlest_reg_id = 1, 2810 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 2811 }, 2812 }, 2813 .slaves = omap3xxx_mailbox_slaves, 2814 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), 2815 }; 2816 2817 /* l4 core -> mcspi1 interface */ 2818 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2819 .master = &omap3xxx_l4_core_hwmod, 2820 .slave = &omap34xx_mcspi1, 2821 .clk = "mcspi1_ick", 2822 .addr = omap2_mcspi1_addr_space, 2823 .user = OCP_USER_MPU | OCP_USER_SDMA, 2824 }; 2825 2826 /* l4 core -> mcspi2 interface */ 2827 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2828 .master = &omap3xxx_l4_core_hwmod, 2829 .slave = &omap34xx_mcspi2, 2830 .clk = "mcspi2_ick", 2831 .addr = omap2_mcspi2_addr_space, 2832 .user = OCP_USER_MPU | OCP_USER_SDMA, 2833 }; 2834 2835 /* l4 core -> mcspi3 interface */ 2836 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2837 .master = &omap3xxx_l4_core_hwmod, 2838 .slave = &omap34xx_mcspi3, 2839 .clk = "mcspi3_ick", 2840 .addr = omap2430_mcspi3_addr_space, 2841 .user = OCP_USER_MPU | OCP_USER_SDMA, 2842 }; 2843 2844 /* l4 core -> mcspi4 interface */ 2845 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { 2846 { 2847 .pa_start = 0x480ba000, 2848 .pa_end = 0x480ba0ff, 2849 .flags = ADDR_TYPE_RT, 2850 }, 2851 { } 2852 }; 2853 2854 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2855 .master = &omap3xxx_l4_core_hwmod, 2856 .slave = &omap34xx_mcspi4, 2857 .clk = "mcspi4_ick", 2858 .addr = omap34xx_mcspi4_addr_space, 2859 .user = OCP_USER_MPU | OCP_USER_SDMA, 2860 }; 2861 2862 /* 2863 * 'mcspi' class 2864 * multichannel serial port interface (mcspi) / master/slave synchronous serial 2865 * bus 2866 */ 2867 2868 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 2869 .rev_offs = 0x0000, 2870 .sysc_offs = 0x0010, 2871 .syss_offs = 0x0014, 2872 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2873 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 2874 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2875 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2876 .sysc_fields = &omap_hwmod_sysc_type1, 2877 }; 2878 2879 static struct omap_hwmod_class omap34xx_mcspi_class = { 2880 .name = "mcspi", 2881 .sysc = &omap34xx_mcspi_sysc, 2882 .rev = OMAP3_MCSPI_REV, 2883 }; 2884 2885 /* mcspi1 */ 2886 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { 2887 &omap34xx_l4_core__mcspi1, 2888 }; 2889 2890 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 2891 .num_chipselect = 4, 2892 }; 2893 2894 static struct omap_hwmod omap34xx_mcspi1 = { 2895 .name = "mcspi1", 2896 .mpu_irqs = omap2_mcspi1_mpu_irqs, 2897 .sdma_reqs = omap2_mcspi1_sdma_reqs, 2898 .main_clk = "mcspi1_fck", 2899 .prcm = { 2900 .omap2 = { 2901 .module_offs = CORE_MOD, 2902 .prcm_reg_id = 1, 2903 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 2904 .idlest_reg_id = 1, 2905 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 2906 }, 2907 }, 2908 .slaves = omap34xx_mcspi1_slaves, 2909 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), 2910 .class = &omap34xx_mcspi_class, 2911 .dev_attr = &omap_mcspi1_dev_attr, 2912 }; 2913 2914 /* mcspi2 */ 2915 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { 2916 &omap34xx_l4_core__mcspi2, 2917 }; 2918 2919 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 2920 .num_chipselect = 2, 2921 }; 2922 2923 static struct omap_hwmod omap34xx_mcspi2 = { 2924 .name = "mcspi2", 2925 .mpu_irqs = omap2_mcspi2_mpu_irqs, 2926 .sdma_reqs = omap2_mcspi2_sdma_reqs, 2927 .main_clk = "mcspi2_fck", 2928 .prcm = { 2929 .omap2 = { 2930 .module_offs = CORE_MOD, 2931 .prcm_reg_id = 1, 2932 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 2933 .idlest_reg_id = 1, 2934 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 2935 }, 2936 }, 2937 .slaves = omap34xx_mcspi2_slaves, 2938 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), 2939 .class = &omap34xx_mcspi_class, 2940 .dev_attr = &omap_mcspi2_dev_attr, 2941 }; 2942 2943 /* mcspi3 */ 2944 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 2945 { .name = "irq", .irq = 91 }, /* 91 */ 2946 { .irq = -1 } 2947 }; 2948 2949 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 2950 { .name = "tx0", .dma_req = 15 }, 2951 { .name = "rx0", .dma_req = 16 }, 2952 { .name = "tx1", .dma_req = 23 }, 2953 { .name = "rx1", .dma_req = 24 }, 2954 { .dma_req = -1 } 2955 }; 2956 2957 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { 2958 &omap34xx_l4_core__mcspi3, 2959 }; 2960 2961 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 2962 .num_chipselect = 2, 2963 }; 2964 2965 static struct omap_hwmod omap34xx_mcspi3 = { 2966 .name = "mcspi3", 2967 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 2968 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 2969 .main_clk = "mcspi3_fck", 2970 .prcm = { 2971 .omap2 = { 2972 .module_offs = CORE_MOD, 2973 .prcm_reg_id = 1, 2974 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 2975 .idlest_reg_id = 1, 2976 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 2977 }, 2978 }, 2979 .slaves = omap34xx_mcspi3_slaves, 2980 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), 2981 .class = &omap34xx_mcspi_class, 2982 .dev_attr = &omap_mcspi3_dev_attr, 2983 }; 2984 2985 /* SPI4 */ 2986 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 2987 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 2988 { .irq = -1 } 2989 }; 2990 2991 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 2992 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 2993 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 2994 { .dma_req = -1 } 2995 }; 2996 2997 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { 2998 &omap34xx_l4_core__mcspi4, 2999 }; 3000 3001 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 3002 .num_chipselect = 1, 3003 }; 3004 3005 static struct omap_hwmod omap34xx_mcspi4 = { 3006 .name = "mcspi4", 3007 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 3008 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 3009 .main_clk = "mcspi4_fck", 3010 .prcm = { 3011 .omap2 = { 3012 .module_offs = CORE_MOD, 3013 .prcm_reg_id = 1, 3014 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 3015 .idlest_reg_id = 1, 3016 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 3017 }, 3018 }, 3019 .slaves = omap34xx_mcspi4_slaves, 3020 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), 3021 .class = &omap34xx_mcspi_class, 3022 .dev_attr = &omap_mcspi4_dev_attr, 3023 }; 3024 3025 /* 3026 * usbhsotg 3027 */ 3028 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 3029 .rev_offs = 0x0400, 3030 .sysc_offs = 0x0404, 3031 .syss_offs = 0x0408, 3032 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 3033 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 3034 SYSC_HAS_AUTOIDLE), 3035 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3036 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 3037 .sysc_fields = &omap_hwmod_sysc_type1, 3038 }; 3039 3040 static struct omap_hwmod_class usbotg_class = { 3041 .name = "usbotg", 3042 .sysc = &omap3xxx_usbhsotg_sysc, 3043 }; 3044 /* usb_otg_hs */ 3045 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 3046 3047 { .name = "mc", .irq = 92 }, 3048 { .name = "dma", .irq = 93 }, 3049 { .irq = -1 } 3050 }; 3051 3052 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 3053 .name = "usb_otg_hs", 3054 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 3055 .main_clk = "hsotgusb_ick", 3056 .prcm = { 3057 .omap2 = { 3058 .prcm_reg_id = 1, 3059 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 3060 .module_offs = CORE_MOD, 3061 .idlest_reg_id = 1, 3062 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 3063 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 3064 }, 3065 }, 3066 .masters = omap3xxx_usbhsotg_masters, 3067 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), 3068 .slaves = omap3xxx_usbhsotg_slaves, 3069 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), 3070 .class = &usbotg_class, 3071 3072 /* 3073 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 3074 * broken when autoidle is enabled 3075 * workaround is to disable the autoidle bit at module level. 3076 */ 3077 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 3078 | HWMOD_SWSUP_MSTANDBY, 3079 }; 3080 3081 /* usb_otg_hs */ 3082 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 3083 3084 { .name = "mc", .irq = 71 }, 3085 { .irq = -1 } 3086 }; 3087 3088 static struct omap_hwmod_class am35xx_usbotg_class = { 3089 .name = "am35xx_usbotg", 3090 .sysc = NULL, 3091 }; 3092 3093 static struct omap_hwmod am35xx_usbhsotg_hwmod = { 3094 .name = "am35x_otg_hs", 3095 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 3096 .main_clk = NULL, 3097 .prcm = { 3098 .omap2 = { 3099 }, 3100 }, 3101 .masters = am35xx_usbhsotg_masters, 3102 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), 3103 .slaves = am35xx_usbhsotg_slaves, 3104 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), 3105 .class = &am35xx_usbotg_class, 3106 }; 3107 3108 /* MMC/SD/SDIO common */ 3109 3110 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 3111 .rev_offs = 0x1fc, 3112 .sysc_offs = 0x10, 3113 .syss_offs = 0x14, 3114 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 3115 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 3116 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3117 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3118 .sysc_fields = &omap_hwmod_sysc_type1, 3119 }; 3120 3121 static struct omap_hwmod_class omap34xx_mmc_class = { 3122 .name = "mmc", 3123 .sysc = &omap34xx_mmc_sysc, 3124 }; 3125 3126 /* MMC/SD/SDIO1 */ 3127 3128 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 3129 { .irq = 83, }, 3130 { .irq = -1 } 3131 }; 3132 3133 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 3134 { .name = "tx", .dma_req = 61, }, 3135 { .name = "rx", .dma_req = 62, }, 3136 { .dma_req = -1 } 3137 }; 3138 3139 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 3140 { .role = "dbck", .clk = "omap_32k_fck", }, 3141 }; 3142 3143 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { 3144 &omap3xxx_l4_core__mmc1, 3145 }; 3146 3147 static struct omap_mmc_dev_attr mmc1_dev_attr = { 3148 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 3149 }; 3150 3151 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 3152 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { 3153 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 3154 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 3155 }; 3156 3157 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 3158 .name = "mmc1", 3159 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3160 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3161 .opt_clks = omap34xx_mmc1_opt_clks, 3162 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 3163 .main_clk = "mmchs1_fck", 3164 .prcm = { 3165 .omap2 = { 3166 .module_offs = CORE_MOD, 3167 .prcm_reg_id = 1, 3168 .module_bit = OMAP3430_EN_MMC1_SHIFT, 3169 .idlest_reg_id = 1, 3170 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 3171 }, 3172 }, 3173 .dev_attr = &mmc1_pre_es3_dev_attr, 3174 .slaves = omap3xxx_mmc1_slaves, 3175 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), 3176 .class = &omap34xx_mmc_class, 3177 }; 3178 3179 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 3180 .name = "mmc1", 3181 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3182 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3183 .opt_clks = omap34xx_mmc1_opt_clks, 3184 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 3185 .main_clk = "mmchs1_fck", 3186 .prcm = { 3187 .omap2 = { 3188 .module_offs = CORE_MOD, 3189 .prcm_reg_id = 1, 3190 .module_bit = OMAP3430_EN_MMC1_SHIFT, 3191 .idlest_reg_id = 1, 3192 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 3193 }, 3194 }, 3195 .dev_attr = &mmc1_dev_attr, 3196 .slaves = omap3xxx_mmc1_slaves, 3197 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), 3198 .class = &omap34xx_mmc_class, 3199 }; 3200 3201 /* MMC/SD/SDIO2 */ 3202 3203 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 3204 { .irq = INT_24XX_MMC2_IRQ, }, 3205 { .irq = -1 } 3206 }; 3207 3208 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 3209 { .name = "tx", .dma_req = 47, }, 3210 { .name = "rx", .dma_req = 48, }, 3211 { .dma_req = -1 } 3212 }; 3213 3214 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 3215 { .role = "dbck", .clk = "omap_32k_fck", }, 3216 }; 3217 3218 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { 3219 &omap3xxx_l4_core__mmc2, 3220 }; 3221 3222 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 3223 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 3224 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 3225 }; 3226 3227 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 3228 .name = "mmc2", 3229 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3230 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3231 .opt_clks = omap34xx_mmc2_opt_clks, 3232 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 3233 .main_clk = "mmchs2_fck", 3234 .prcm = { 3235 .omap2 = { 3236 .module_offs = CORE_MOD, 3237 .prcm_reg_id = 1, 3238 .module_bit = OMAP3430_EN_MMC2_SHIFT, 3239 .idlest_reg_id = 1, 3240 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 3241 }, 3242 }, 3243 .dev_attr = &mmc2_pre_es3_dev_attr, 3244 .slaves = omap3xxx_mmc2_slaves, 3245 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), 3246 .class = &omap34xx_mmc_class, 3247 }; 3248 3249 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 3250 .name = "mmc2", 3251 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3252 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3253 .opt_clks = omap34xx_mmc2_opt_clks, 3254 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 3255 .main_clk = "mmchs2_fck", 3256 .prcm = { 3257 .omap2 = { 3258 .module_offs = CORE_MOD, 3259 .prcm_reg_id = 1, 3260 .module_bit = OMAP3430_EN_MMC2_SHIFT, 3261 .idlest_reg_id = 1, 3262 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 3263 }, 3264 }, 3265 .slaves = omap3xxx_mmc2_slaves, 3266 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), 3267 .class = &omap34xx_mmc_class, 3268 }; 3269 3270 /* MMC/SD/SDIO3 */ 3271 3272 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 3273 { .irq = 94, }, 3274 { .irq = -1 } 3275 }; 3276 3277 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 3278 { .name = "tx", .dma_req = 77, }, 3279 { .name = "rx", .dma_req = 78, }, 3280 { .dma_req = -1 } 3281 }; 3282 3283 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 3284 { .role = "dbck", .clk = "omap_32k_fck", }, 3285 }; 3286 3287 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { 3288 &omap3xxx_l4_core__mmc3, 3289 }; 3290 3291 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 3292 .name = "mmc3", 3293 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 3294 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 3295 .opt_clks = omap34xx_mmc3_opt_clks, 3296 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 3297 .main_clk = "mmchs3_fck", 3298 .prcm = { 3299 .omap2 = { 3300 .prcm_reg_id = 1, 3301 .module_bit = OMAP3430_EN_MMC3_SHIFT, 3302 .idlest_reg_id = 1, 3303 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 3304 }, 3305 }, 3306 .slaves = omap3xxx_mmc3_slaves, 3307 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), 3308 .class = &omap34xx_mmc_class, 3309 }; 3310 3311 /* 3312 * 'usb_host_hs' class 3313 * high-speed multi-port usb host controller 3314 */ 3315 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 3316 .master = &omap3xxx_usb_host_hs_hwmod, 3317 .slave = &omap3xxx_l3_main_hwmod, 3318 .clk = "core_l3_ick", 3319 .user = OCP_USER_MPU, 3320 }; 3321 3322 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 3323 .rev_offs = 0x0000, 3324 .sysc_offs = 0x0010, 3325 .syss_offs = 0x0014, 3326 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 3327 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 3328 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 3329 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3330 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 3331 .sysc_fields = &omap_hwmod_sysc_type1, 3332 }; 3333 3334 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 3335 .name = "usb_host_hs", 3336 .sysc = &omap3xxx_usb_host_hs_sysc, 3337 }; 3338 3339 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { 3340 &omap3xxx_usb_host_hs__l3_main_2, 3341 }; 3342 3343 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { 3344 { 3345 .name = "uhh", 3346 .pa_start = 0x48064000, 3347 .pa_end = 0x480643ff, 3348 .flags = ADDR_TYPE_RT 3349 }, 3350 { 3351 .name = "ohci", 3352 .pa_start = 0x48064400, 3353 .pa_end = 0x480647ff, 3354 }, 3355 { 3356 .name = "ehci", 3357 .pa_start = 0x48064800, 3358 .pa_end = 0x48064cff, 3359 }, 3360 {} 3361 }; 3362 3363 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 3364 .master = &omap3xxx_l4_core_hwmod, 3365 .slave = &omap3xxx_usb_host_hs_hwmod, 3366 .clk = "usbhost_ick", 3367 .addr = omap3xxx_usb_host_hs_addrs, 3368 .user = OCP_USER_MPU | OCP_USER_SDMA, 3369 }; 3370 3371 static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { 3372 &omap3xxx_l4_core__usb_host_hs, 3373 }; 3374 3375 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 3376 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 3377 }; 3378 3379 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { 3380 { .name = "ohci-irq", .irq = 76 }, 3381 { .name = "ehci-irq", .irq = 77 }, 3382 { .irq = -1 } 3383 }; 3384 3385 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 3386 .name = "usb_host_hs", 3387 .class = &omap3xxx_usb_host_hs_hwmod_class, 3388 .clkdm_name = "l3_init_clkdm", 3389 .mpu_irqs = omap3xxx_usb_host_hs_irqs, 3390 .main_clk = "usbhost_48m_fck", 3391 .prcm = { 3392 .omap2 = { 3393 .module_offs = OMAP3430ES2_USBHOST_MOD, 3394 .prcm_reg_id = 1, 3395 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 3396 .idlest_reg_id = 1, 3397 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 3398 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 3399 }, 3400 }, 3401 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 3402 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 3403 .slaves = omap3xxx_usb_host_hs_slaves, 3404 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), 3405 .masters = omap3xxx_usb_host_hs_masters, 3406 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), 3407 3408 /* 3409 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 3410 * id: i660 3411 * 3412 * Description: 3413 * In the following configuration : 3414 * - USBHOST module is set to smart-idle mode 3415 * - PRCM asserts idle_req to the USBHOST module ( This typically 3416 * happens when the system is going to a low power mode : all ports 3417 * have been suspended, the master part of the USBHOST module has 3418 * entered the standby state, and SW has cut the functional clocks) 3419 * - an USBHOST interrupt occurs before the module is able to answer 3420 * idle_ack, typically a remote wakeup IRQ. 3421 * Then the USB HOST module will enter a deadlock situation where it 3422 * is no more accessible nor functional. 3423 * 3424 * Workaround: 3425 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 3426 */ 3427 3428 /* 3429 * Errata: USB host EHCI may stall when entering smart-standby mode 3430 * Id: i571 3431 * 3432 * Description: 3433 * When the USBHOST module is set to smart-standby mode, and when it is 3434 * ready to enter the standby state (i.e. all ports are suspended and 3435 * all attached devices are in suspend mode), then it can wrongly assert 3436 * the Mstandby signal too early while there are still some residual OCP 3437 * transactions ongoing. If this condition occurs, the internal state 3438 * machine may go to an undefined state and the USB link may be stuck 3439 * upon the next resume. 3440 * 3441 * Workaround: 3442 * Don't use smart standby; use only force standby, 3443 * hence HWMOD_SWSUP_MSTANDBY 3444 */ 3445 3446 /* 3447 * During system boot; If the hwmod framework resets the module 3448 * the module will have smart idle settings; which can lead to deadlock 3449 * (above Errata Id:i660); so, dont reset the module during boot; 3450 * Use HWMOD_INIT_NO_RESET. 3451 */ 3452 3453 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | 3454 HWMOD_INIT_NO_RESET, 3455 }; 3456 3457 /* 3458 * 'usb_tll_hs' class 3459 * usb_tll_hs module is the adapter on the usb_host_hs ports 3460 */ 3461 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 3462 .rev_offs = 0x0000, 3463 .sysc_offs = 0x0010, 3464 .syss_offs = 0x0014, 3465 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 3466 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 3467 SYSC_HAS_AUTOIDLE), 3468 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3469 .sysc_fields = &omap_hwmod_sysc_type1, 3470 }; 3471 3472 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 3473 .name = "usb_tll_hs", 3474 .sysc = &omap3xxx_usb_tll_hs_sysc, 3475 }; 3476 3477 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { 3478 { .name = "tll-irq", .irq = 78 }, 3479 { .irq = -1 } 3480 }; 3481 3482 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3483 { 3484 .name = "tll", 3485 .pa_start = 0x48062000, 3486 .pa_end = 0x48062fff, 3487 .flags = ADDR_TYPE_RT 3488 }, 3489 {} 3490 }; 3491 3492 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 3493 .master = &omap3xxx_l4_core_hwmod, 3494 .slave = &omap3xxx_usb_tll_hs_hwmod, 3495 .clk = "usbtll_ick", 3496 .addr = omap3xxx_usb_tll_hs_addrs, 3497 .user = OCP_USER_MPU | OCP_USER_SDMA, 3498 }; 3499 3500 static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { 3501 &omap3xxx_l4_core__usb_tll_hs, 3502 }; 3503 3504 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 3505 .name = "usb_tll_hs", 3506 .class = &omap3xxx_usb_tll_hs_hwmod_class, 3507 .clkdm_name = "l3_init_clkdm", 3508 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 3509 .main_clk = "usbtll_fck", 3510 .prcm = { 3511 .omap2 = { 3512 .module_offs = CORE_MOD, 3513 .prcm_reg_id = 3, 3514 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 3515 .idlest_reg_id = 3, 3516 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 3517 }, 3518 }, 3519 .slaves = omap3xxx_usb_tll_hs_slaves, 3520 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), 3521 }; 3522 3523 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 3524 &omap3xxx_l3_main_hwmod, 3525 &omap3xxx_l4_core_hwmod, 3526 &omap3xxx_l4_per_hwmod, 3527 &omap3xxx_l4_wkup_hwmod, 3528 &omap3xxx_mmc3_hwmod, 3529 &omap3xxx_mpu_hwmod, 3530 3531 &omap3xxx_timer1_hwmod, 3532 &omap3xxx_timer2_hwmod, 3533 &omap3xxx_timer3_hwmod, 3534 &omap3xxx_timer4_hwmod, 3535 &omap3xxx_timer5_hwmod, 3536 &omap3xxx_timer6_hwmod, 3537 &omap3xxx_timer7_hwmod, 3538 &omap3xxx_timer8_hwmod, 3539 &omap3xxx_timer9_hwmod, 3540 &omap3xxx_timer10_hwmod, 3541 &omap3xxx_timer11_hwmod, 3542 3543 &omap3xxx_wd_timer2_hwmod, 3544 &omap3xxx_uart1_hwmod, 3545 &omap3xxx_uart2_hwmod, 3546 &omap3xxx_uart3_hwmod, 3547 3548 /* i2c class */ 3549 &omap3xxx_i2c1_hwmod, 3550 &omap3xxx_i2c2_hwmod, 3551 &omap3xxx_i2c3_hwmod, 3552 3553 /* gpio class */ 3554 &omap3xxx_gpio1_hwmod, 3555 &omap3xxx_gpio2_hwmod, 3556 &omap3xxx_gpio3_hwmod, 3557 &omap3xxx_gpio4_hwmod, 3558 &omap3xxx_gpio5_hwmod, 3559 &omap3xxx_gpio6_hwmod, 3560 3561 /* dma_system class*/ 3562 &omap3xxx_dma_system_hwmod, 3563 3564 /* mcbsp class */ 3565 &omap3xxx_mcbsp1_hwmod, 3566 &omap3xxx_mcbsp2_hwmod, 3567 &omap3xxx_mcbsp3_hwmod, 3568 &omap3xxx_mcbsp4_hwmod, 3569 &omap3xxx_mcbsp5_hwmod, 3570 &omap3xxx_mcbsp2_sidetone_hwmod, 3571 &omap3xxx_mcbsp3_sidetone_hwmod, 3572 3573 3574 /* mcspi class */ 3575 &omap34xx_mcspi1, 3576 &omap34xx_mcspi2, 3577 &omap34xx_mcspi3, 3578 &omap34xx_mcspi4, 3579 3580 NULL, 3581 }; 3582 3583 /* GP-only hwmods */ 3584 static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { 3585 &omap3xxx_timer12_hwmod, 3586 NULL 3587 }; 3588 3589 /* 3430ES1-only hwmods */ 3590 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { 3591 &omap3430es1_dss_core_hwmod, 3592 NULL 3593 }; 3594 3595 /* 3430ES2+-only hwmods */ 3596 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { 3597 &omap3xxx_dss_core_hwmod, 3598 &omap3xxx_usbhsotg_hwmod, 3599 &omap3xxx_usb_host_hs_hwmod, 3600 &omap3xxx_usb_tll_hs_hwmod, 3601 NULL 3602 }; 3603 3604 /* <= 3430ES3-only hwmods */ 3605 static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { 3606 &omap3xxx_pre_es3_mmc1_hwmod, 3607 &omap3xxx_pre_es3_mmc2_hwmod, 3608 NULL 3609 }; 3610 3611 /* 3430ES3+-only hwmods */ 3612 static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { 3613 &omap3xxx_es3plus_mmc1_hwmod, 3614 &omap3xxx_es3plus_mmc2_hwmod, 3615 NULL 3616 }; 3617 3618 /* 34xx-only hwmods (all ES revisions) */ 3619 static __initdata struct omap_hwmod *omap34xx_hwmods[] = { 3620 &omap3xxx_iva_hwmod, 3621 &omap34xx_sr1_hwmod, 3622 &omap34xx_sr2_hwmod, 3623 &omap3xxx_mailbox_hwmod, 3624 NULL 3625 }; 3626 3627 /* 36xx-only hwmods (all ES revisions) */ 3628 static __initdata struct omap_hwmod *omap36xx_hwmods[] = { 3629 &omap3xxx_iva_hwmod, 3630 &omap3xxx_uart4_hwmod, 3631 &omap3xxx_dss_core_hwmod, 3632 &omap36xx_sr1_hwmod, 3633 &omap36xx_sr2_hwmod, 3634 &omap3xxx_usbhsotg_hwmod, 3635 &omap3xxx_mailbox_hwmod, 3636 &omap3xxx_usb_host_hs_hwmod, 3637 &omap3xxx_usb_tll_hs_hwmod, 3638 &omap3xxx_es3plus_mmc1_hwmod, 3639 &omap3xxx_es3plus_mmc2_hwmod, 3640 NULL 3641 }; 3642 3643 static __initdata struct omap_hwmod *am35xx_hwmods[] = { 3644 &omap3xxx_dss_core_hwmod, /* XXX ??? */ 3645 &am35xx_usbhsotg_hwmod, 3646 &am35xx_uart4_hwmod, 3647 &omap3xxx_usb_host_hs_hwmod, 3648 &omap3xxx_usb_tll_hs_hwmod, 3649 &omap3xxx_es3plus_mmc1_hwmod, 3650 &omap3xxx_es3plus_mmc2_hwmod, 3651 NULL 3652 }; 3653 3654 static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { 3655 /* dss class */ 3656 &omap3xxx_dss_dispc_hwmod, 3657 &omap3xxx_dss_dsi1_hwmod, 3658 &omap3xxx_dss_rfbi_hwmod, 3659 &omap3xxx_dss_venc_hwmod, 3660 NULL 3661 }; 3662 3663 int __init omap3xxx_hwmod_init(void) 3664 { 3665 int r; 3666 struct omap_hwmod **h = NULL; 3667 unsigned int rev; 3668 3669 /* Register hwmods common to all OMAP3 */ 3670 r = omap_hwmod_register(omap3xxx_hwmods); 3671 if (r < 0) 3672 return r; 3673 3674 /* Register GP-only hwmods. */ 3675 if (omap_type() == OMAP2_DEVICE_TYPE_GP) { 3676 r = omap_hwmod_register(omap3xxx_gp_hwmods); 3677 if (r < 0) 3678 return r; 3679 } 3680 3681 rev = omap_rev(); 3682 3683 /* 3684 * Register hwmods common to individual OMAP3 families, all 3685 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3686 * All possible revisions should be included in this conditional. 3687 */ 3688 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3689 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3690 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3691 h = omap34xx_hwmods; 3692 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { 3693 h = am35xx_hwmods; 3694 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3695 rev == OMAP3630_REV_ES1_2) { 3696 h = omap36xx_hwmods; 3697 } else { 3698 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3699 return -EINVAL; 3700 }; 3701 3702 r = omap_hwmod_register(h); 3703 if (r < 0) 3704 return r; 3705 3706 /* 3707 * Register hwmods specific to certain ES levels of a 3708 * particular family of silicon (e.g., 34xx ES1.0) 3709 */ 3710 h = NULL; 3711 if (rev == OMAP3430_REV_ES1_0) { 3712 h = omap3430es1_hwmods; 3713 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3714 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3715 rev == OMAP3430_REV_ES3_1_2) { 3716 h = omap3430es2plus_hwmods; 3717 }; 3718 3719 if (h) { 3720 r = omap_hwmod_register(h); 3721 if (r < 0) 3722 return r; 3723 } 3724 3725 h = NULL; 3726 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3727 rev == OMAP3430_REV_ES2_1) { 3728 h = omap3430_pre_es3_hwmods; 3729 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3730 rev == OMAP3430_REV_ES3_1_2) { 3731 h = omap3430_es3plus_hwmods; 3732 }; 3733 3734 if (h) 3735 r = omap_hwmod_register(h); 3736 if (r < 0) 3737 return r; 3738 3739 /* 3740 * DSS code presumes that dss_core hwmod is handled first, 3741 * _before_ any other DSS related hwmods so register common 3742 * DSS hwmods last to ensure that dss_core is already registered. 3743 * Otherwise some change things may happen, for ex. if dispc 3744 * is handled before dss_core and DSS is enabled in bootloader 3745 * DIPSC will be reset with outputs enabled which sometimes leads 3746 * to unrecoverable L3 error. 3747 * XXX The long-term fix to this is to ensure modules are set up 3748 * in dependency order in the hwmod core code. 3749 */ 3750 r = omap_hwmod_register(omap3xxx_dss_hwmods); 3751 3752 return r; 3753 } 3754