1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
211fadcfaSAmbresh K /*
311fadcfaSAmbresh K * DRA7xx Clock domains framework
411fadcfaSAmbresh K *
511fadcfaSAmbresh K * Copyright (C) 2009-2013 Texas Instruments, Inc.
611fadcfaSAmbresh K * Copyright (C) 2009-2011 Nokia Corporation
711fadcfaSAmbresh K *
811fadcfaSAmbresh K * Generated by code originally written by:
911fadcfaSAmbresh K * Abhijit Pagare (abhijitpagare@ti.com)
1011fadcfaSAmbresh K * Benoit Cousson (b-cousson@ti.com)
1111fadcfaSAmbresh K * Paul Walmsley (paul@pwsan.com)
1211fadcfaSAmbresh K *
1311fadcfaSAmbresh K * This file is automatically generated from the OMAP hardware databases.
1411fadcfaSAmbresh K * We respectfully ask that any modifications to this file be coordinated
1511fadcfaSAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the
1611fadcfaSAmbresh K * authors above to ensure that the autogeneration scripts are kept
1711fadcfaSAmbresh K * up-to-date with the file contents.
1811fadcfaSAmbresh K */
1911fadcfaSAmbresh K
2011fadcfaSAmbresh K #include <linux/kernel.h>
2111fadcfaSAmbresh K #include <linux/io.h>
2211fadcfaSAmbresh K
2311fadcfaSAmbresh K #include "clockdomain.h"
2411fadcfaSAmbresh K #include "cm1_7xx.h"
2511fadcfaSAmbresh K #include "cm2_7xx.h"
2611fadcfaSAmbresh K
2711fadcfaSAmbresh K #include "cm-regbits-7xx.h"
2811fadcfaSAmbresh K #include "prm7xx.h"
2911fadcfaSAmbresh K #include "prcm44xx.h"
3011fadcfaSAmbresh K #include "prcm_mpu7xx.h"
3111fadcfaSAmbresh K
3211fadcfaSAmbresh K /* Static Dependencies for DRA7xx Clock Domains */
3311fadcfaSAmbresh K
3411fadcfaSAmbresh K static struct clkdm_dep cam_wkup_sleep_deps[] = {
3511fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
3611fadcfaSAmbresh K { NULL },
3711fadcfaSAmbresh K };
3811fadcfaSAmbresh K
3911fadcfaSAmbresh K static struct clkdm_dep dma_wkup_sleep_deps[] = {
4011fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
4111fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
4211fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
4311fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
4411fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
4511fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
4611fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
4711fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
4811fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
4911fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
5011fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
5111fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
5211fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
5311fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
5411fadcfaSAmbresh K { NULL },
5511fadcfaSAmbresh K };
5611fadcfaSAmbresh K
5711fadcfaSAmbresh K static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
5811fadcfaSAmbresh K { .clkdm_name = "atl_clkdm" },
5911fadcfaSAmbresh K { .clkdm_name = "cam_clkdm" },
6011fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
6111fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
6211fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
6311fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
6411fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
6511fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
6611fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
6711fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
6811fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
6911fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
7011fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
7111fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
7211fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
7311fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
7411fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
7511fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
7611fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
7711fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
7811fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
7911fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
8011fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
8111fadcfaSAmbresh K { NULL },
8211fadcfaSAmbresh K };
8311fadcfaSAmbresh K
8411fadcfaSAmbresh K static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
8511fadcfaSAmbresh K { .clkdm_name = "atl_clkdm" },
8611fadcfaSAmbresh K { .clkdm_name = "cam_clkdm" },
8711fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
8811fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
8911fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
9011fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
9111fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
9211fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
9311fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
9411fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
9511fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
9611fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
9711fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
9811fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
9911fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
10011fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
10111fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
10211fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
10311fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
10411fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
10511fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
10611fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
10711fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
10811fadcfaSAmbresh K { NULL },
10911fadcfaSAmbresh K };
11011fadcfaSAmbresh K
11111fadcfaSAmbresh K static struct clkdm_dep dss_wkup_sleep_deps[] = {
11211fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
11311fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
11411fadcfaSAmbresh K { NULL },
11511fadcfaSAmbresh K };
11611fadcfaSAmbresh K
11711fadcfaSAmbresh K static struct clkdm_dep eve1_wkup_sleep_deps[] = {
11811fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
11911fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
12011fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
12111fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
12211fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
12311fadcfaSAmbresh K { NULL },
12411fadcfaSAmbresh K };
12511fadcfaSAmbresh K
12611fadcfaSAmbresh K static struct clkdm_dep eve2_wkup_sleep_deps[] = {
12711fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
12811fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
12911fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
13011fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
13111fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
13211fadcfaSAmbresh K { NULL },
13311fadcfaSAmbresh K };
13411fadcfaSAmbresh K
13511fadcfaSAmbresh K static struct clkdm_dep eve3_wkup_sleep_deps[] = {
13611fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
13711fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
13811fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
13911fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
14011fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
14111fadcfaSAmbresh K { NULL },
14211fadcfaSAmbresh K };
14311fadcfaSAmbresh K
14411fadcfaSAmbresh K static struct clkdm_dep eve4_wkup_sleep_deps[] = {
14511fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
14611fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
14711fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
14811fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
14911fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
15011fadcfaSAmbresh K { NULL },
15111fadcfaSAmbresh K };
15211fadcfaSAmbresh K
15311fadcfaSAmbresh K static struct clkdm_dep gmac_wkup_sleep_deps[] = {
15411fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
15511fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
15611fadcfaSAmbresh K { NULL },
15711fadcfaSAmbresh K };
15811fadcfaSAmbresh K
15911fadcfaSAmbresh K static struct clkdm_dep gpu_wkup_sleep_deps[] = {
16011fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
16111fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
16211fadcfaSAmbresh K { NULL },
16311fadcfaSAmbresh K };
16411fadcfaSAmbresh K
16511fadcfaSAmbresh K static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
16611fadcfaSAmbresh K { .clkdm_name = "atl_clkdm" },
16711fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
16811fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
16911fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
17011fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
17111fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
17211fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
17311fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
17411fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
17511fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
17611fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
17711fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
17811fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
17911fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
18011fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
18111fadcfaSAmbresh K { .clkdm_name = "l3main1_clkdm" },
18211fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
18311fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
18411fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
18511fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
18611fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
18711fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
18811fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
18911fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
19011fadcfaSAmbresh K { NULL },
19111fadcfaSAmbresh K };
19211fadcfaSAmbresh K
19311fadcfaSAmbresh K static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
19411fadcfaSAmbresh K { .clkdm_name = "atl_clkdm" },
19511fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
19611fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
19711fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
19811fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
19911fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
20011fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
20111fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
20211fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
20311fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
20411fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
20511fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
20611fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
20711fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
20811fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
20911fadcfaSAmbresh K { .clkdm_name = "l3main1_clkdm" },
21011fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
21111fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
21211fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
21311fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
21411fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
21511fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
21611fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
21711fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
21811fadcfaSAmbresh K { NULL },
21911fadcfaSAmbresh K };
22011fadcfaSAmbresh K
22111fadcfaSAmbresh K static struct clkdm_dep iva_wkup_sleep_deps[] = {
22211fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
22311fadcfaSAmbresh K { NULL },
22411fadcfaSAmbresh K };
22511fadcfaSAmbresh K
22611fadcfaSAmbresh K static struct clkdm_dep l3init_wkup_sleep_deps[] = {
22711fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
22811fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
22911fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
23011fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
23111fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
23211fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
23311fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
23411fadcfaSAmbresh K { NULL },
23511fadcfaSAmbresh K };
23611fadcfaSAmbresh K
23711fadcfaSAmbresh K static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
23811fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
23911fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
24011fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
24111fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
24211fadcfaSAmbresh K { NULL },
24311fadcfaSAmbresh K };
24411fadcfaSAmbresh K
24511fadcfaSAmbresh K static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
24611fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
24711fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
24811fadcfaSAmbresh K { NULL },
24911fadcfaSAmbresh K };
25011fadcfaSAmbresh K
25111fadcfaSAmbresh K static struct clkdm_dep mpu_wkup_sleep_deps[] = {
25211fadcfaSAmbresh K { .clkdm_name = "cam_clkdm" },
25311fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
25411fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
25511fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
25611fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
25711fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
25811fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
25911fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
26011fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
26111fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
26211fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
26311fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
26411fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
26511fadcfaSAmbresh K { .clkdm_name = "ipu2_clkdm" },
26611fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
26711fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
26811fadcfaSAmbresh K { .clkdm_name = "l3main1_clkdm" },
26911fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
27011fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
27111fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
27211fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
27311fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
27411fadcfaSAmbresh K { .clkdm_name = "pcie_clkdm" },
27511fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
27611fadcfaSAmbresh K { .clkdm_name = "wkupaon_clkdm" },
27711fadcfaSAmbresh K { NULL },
27811fadcfaSAmbresh K };
27911fadcfaSAmbresh K
28011fadcfaSAmbresh K static struct clkdm_dep pcie_wkup_sleep_deps[] = {
28111fadcfaSAmbresh K { .clkdm_name = "atl_clkdm" },
28211fadcfaSAmbresh K { .clkdm_name = "cam_clkdm" },
28311fadcfaSAmbresh K { .clkdm_name = "dsp1_clkdm" },
28411fadcfaSAmbresh K { .clkdm_name = "dsp2_clkdm" },
28511fadcfaSAmbresh K { .clkdm_name = "dss_clkdm" },
28611fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
28711fadcfaSAmbresh K { .clkdm_name = "eve1_clkdm" },
28811fadcfaSAmbresh K { .clkdm_name = "eve2_clkdm" },
28911fadcfaSAmbresh K { .clkdm_name = "eve3_clkdm" },
29011fadcfaSAmbresh K { .clkdm_name = "eve4_clkdm" },
29111fadcfaSAmbresh K { .clkdm_name = "gmac_clkdm" },
29211fadcfaSAmbresh K { .clkdm_name = "gpu_clkdm" },
29311fadcfaSAmbresh K { .clkdm_name = "ipu_clkdm" },
29411fadcfaSAmbresh K { .clkdm_name = "ipu1_clkdm" },
29511fadcfaSAmbresh K { .clkdm_name = "iva_clkdm" },
29611fadcfaSAmbresh K { .clkdm_name = "l3init_clkdm" },
29711fadcfaSAmbresh K { .clkdm_name = "l4cfg_clkdm" },
29811fadcfaSAmbresh K { .clkdm_name = "l4per_clkdm" },
29911fadcfaSAmbresh K { .clkdm_name = "l4per2_clkdm" },
30011fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
30111fadcfaSAmbresh K { .clkdm_name = "l4sec_clkdm" },
30211fadcfaSAmbresh K { .clkdm_name = "vpe_clkdm" },
30311fadcfaSAmbresh K { NULL },
30411fadcfaSAmbresh K };
30511fadcfaSAmbresh K
30611fadcfaSAmbresh K static struct clkdm_dep vpe_wkup_sleep_deps[] = {
30711fadcfaSAmbresh K { .clkdm_name = "emif_clkdm" },
30811fadcfaSAmbresh K { .clkdm_name = "l4per3_clkdm" },
30911fadcfaSAmbresh K { NULL },
31011fadcfaSAmbresh K };
31111fadcfaSAmbresh K
31211fadcfaSAmbresh K static struct clockdomain l4per3_7xx_clkdm = {
31311fadcfaSAmbresh K .name = "l4per3_clkdm",
31411fadcfaSAmbresh K .pwrdm = { .name = "l4per_pwrdm" },
31511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
31611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
31711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
31811fadcfaSAmbresh K .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
31911fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
32011fadcfaSAmbresh K };
32111fadcfaSAmbresh K
32211fadcfaSAmbresh K static struct clockdomain l4per2_7xx_clkdm = {
32311fadcfaSAmbresh K .name = "l4per2_clkdm",
32411fadcfaSAmbresh K .pwrdm = { .name = "l4per_pwrdm" },
32511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
32611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
32711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
32811fadcfaSAmbresh K .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
32911fadcfaSAmbresh K .wkdep_srcs = l4per2_wkup_sleep_deps,
33011fadcfaSAmbresh K .sleepdep_srcs = l4per2_wkup_sleep_deps,
331b9e23f32SVignesh R .flags = CLKDM_CAN_SWSUP,
33211fadcfaSAmbresh K };
33311fadcfaSAmbresh K
33411fadcfaSAmbresh K static struct clockdomain mpu0_7xx_clkdm = {
33511fadcfaSAmbresh K .name = "mpu0_clkdm",
33611fadcfaSAmbresh K .pwrdm = { .name = "cpu0_pwrdm" },
33711fadcfaSAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
33811fadcfaSAmbresh K .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
33911fadcfaSAmbresh K .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
34011fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
34111fadcfaSAmbresh K };
34211fadcfaSAmbresh K
34311fadcfaSAmbresh K static struct clockdomain iva_7xx_clkdm = {
34411fadcfaSAmbresh K .name = "iva_clkdm",
34511fadcfaSAmbresh K .pwrdm = { .name = "iva_pwrdm" },
34611fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
34711fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_IVA_INST,
34811fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
34911fadcfaSAmbresh K .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
35011fadcfaSAmbresh K .wkdep_srcs = iva_wkup_sleep_deps,
35111fadcfaSAmbresh K .sleepdep_srcs = iva_wkup_sleep_deps,
35211fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
35311fadcfaSAmbresh K };
35411fadcfaSAmbresh K
35511fadcfaSAmbresh K static struct clockdomain coreaon_7xx_clkdm = {
35611fadcfaSAmbresh K .name = "coreaon_clkdm",
35711fadcfaSAmbresh K .pwrdm = { .name = "coreaon_pwrdm" },
35811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
35911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
36011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
36111fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
36211fadcfaSAmbresh K };
36311fadcfaSAmbresh K
36411fadcfaSAmbresh K static struct clockdomain ipu1_7xx_clkdm = {
36511fadcfaSAmbresh K .name = "ipu1_clkdm",
36611fadcfaSAmbresh K .pwrdm = { .name = "ipu_pwrdm" },
36711fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
36811fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
36911fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
37011fadcfaSAmbresh K .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
37111fadcfaSAmbresh K .wkdep_srcs = ipu1_wkup_sleep_deps,
37211fadcfaSAmbresh K .sleepdep_srcs = ipu1_wkup_sleep_deps,
37311fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
37411fadcfaSAmbresh K };
37511fadcfaSAmbresh K
37611fadcfaSAmbresh K static struct clockdomain ipu2_7xx_clkdm = {
37711fadcfaSAmbresh K .name = "ipu2_clkdm",
37811fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
37911fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
38011fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
38111fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
38211fadcfaSAmbresh K .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
38311fadcfaSAmbresh K .wkdep_srcs = ipu2_wkup_sleep_deps,
38411fadcfaSAmbresh K .sleepdep_srcs = ipu2_wkup_sleep_deps,
38511fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
38611fadcfaSAmbresh K };
38711fadcfaSAmbresh K
38811fadcfaSAmbresh K static struct clockdomain l3init_7xx_clkdm = {
38911fadcfaSAmbresh K .name = "l3init_clkdm",
39011fadcfaSAmbresh K .pwrdm = { .name = "l3init_pwrdm" },
39111fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
39211fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
39311fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
39411fadcfaSAmbresh K .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
39511fadcfaSAmbresh K .wkdep_srcs = l3init_wkup_sleep_deps,
39611fadcfaSAmbresh K .sleepdep_srcs = l3init_wkup_sleep_deps,
39711fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
39811fadcfaSAmbresh K };
39911fadcfaSAmbresh K
40011fadcfaSAmbresh K static struct clockdomain l4sec_7xx_clkdm = {
40111fadcfaSAmbresh K .name = "l4sec_clkdm",
40211fadcfaSAmbresh K .pwrdm = { .name = "l4per_pwrdm" },
40311fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
40411fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
40511fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
40611fadcfaSAmbresh K .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
40711fadcfaSAmbresh K .wkdep_srcs = l4sec_wkup_sleep_deps,
40811fadcfaSAmbresh K .sleepdep_srcs = l4sec_wkup_sleep_deps,
409c2ce5fb3SJoel Fernandes .flags = CLKDM_CAN_SWSUP,
41011fadcfaSAmbresh K };
41111fadcfaSAmbresh K
41211fadcfaSAmbresh K static struct clockdomain l3main1_7xx_clkdm = {
41311fadcfaSAmbresh K .name = "l3main1_clkdm",
41411fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
41511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
41611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
41711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
41811fadcfaSAmbresh K .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
41911fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP,
42011fadcfaSAmbresh K };
42111fadcfaSAmbresh K
42211fadcfaSAmbresh K static struct clockdomain vpe_7xx_clkdm = {
42311fadcfaSAmbresh K .name = "vpe_clkdm",
42411fadcfaSAmbresh K .pwrdm = { .name = "vpe_pwrdm" },
42511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
42611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
42711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
42811fadcfaSAmbresh K .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
42911fadcfaSAmbresh K .wkdep_srcs = vpe_wkup_sleep_deps,
43011fadcfaSAmbresh K .sleepdep_srcs = vpe_wkup_sleep_deps,
43111fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
43211fadcfaSAmbresh K };
43311fadcfaSAmbresh K
43411fadcfaSAmbresh K static struct clockdomain mpu_7xx_clkdm = {
43511fadcfaSAmbresh K .name = "mpu_clkdm",
43611fadcfaSAmbresh K .pwrdm = { .name = "mpu_pwrdm" },
43711fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
43811fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
43911fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
44011fadcfaSAmbresh K .wkdep_srcs = mpu_wkup_sleep_deps,
44111fadcfaSAmbresh K .sleepdep_srcs = mpu_wkup_sleep_deps,
44211fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
44311fadcfaSAmbresh K };
44411fadcfaSAmbresh K
44511fadcfaSAmbresh K static struct clockdomain custefuse_7xx_clkdm = {
44611fadcfaSAmbresh K .name = "custefuse_clkdm",
44711fadcfaSAmbresh K .pwrdm = { .name = "custefuse_pwrdm" },
44811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
44911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
45011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
45111fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
45211fadcfaSAmbresh K };
45311fadcfaSAmbresh K
45411fadcfaSAmbresh K static struct clockdomain ipu_7xx_clkdm = {
45511fadcfaSAmbresh K .name = "ipu_clkdm",
45611fadcfaSAmbresh K .pwrdm = { .name = "ipu_pwrdm" },
45711fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
45811fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
45911fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
46011fadcfaSAmbresh K .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
4611cbabcb9SKeerthy .flags = CLKDM_CAN_SWSUP,
46211fadcfaSAmbresh K };
46311fadcfaSAmbresh K
46411fadcfaSAmbresh K static struct clockdomain mpu1_7xx_clkdm = {
46511fadcfaSAmbresh K .name = "mpu1_clkdm",
46611fadcfaSAmbresh K .pwrdm = { .name = "cpu1_pwrdm" },
46711fadcfaSAmbresh K .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
46811fadcfaSAmbresh K .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
46911fadcfaSAmbresh K .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
47011fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
47111fadcfaSAmbresh K };
47211fadcfaSAmbresh K
47311fadcfaSAmbresh K static struct clockdomain gmac_7xx_clkdm = {
47411fadcfaSAmbresh K .name = "gmac_clkdm",
47511fadcfaSAmbresh K .pwrdm = { .name = "l3init_pwrdm" },
47611fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
47711fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
47811fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
47911fadcfaSAmbresh K .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
48011fadcfaSAmbresh K .wkdep_srcs = gmac_wkup_sleep_deps,
48111fadcfaSAmbresh K .sleepdep_srcs = gmac_wkup_sleep_deps,
48211fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
48311fadcfaSAmbresh K };
48411fadcfaSAmbresh K
48511fadcfaSAmbresh K static struct clockdomain l4cfg_7xx_clkdm = {
48611fadcfaSAmbresh K .name = "l4cfg_clkdm",
48711fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
48811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
48911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
49011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
49111fadcfaSAmbresh K .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
49211fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP,
49311fadcfaSAmbresh K };
49411fadcfaSAmbresh K
49511fadcfaSAmbresh K static struct clockdomain dma_7xx_clkdm = {
49611fadcfaSAmbresh K .name = "dma_clkdm",
49711fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
49811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
49911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
50011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
50111fadcfaSAmbresh K .wkdep_srcs = dma_wkup_sleep_deps,
50211fadcfaSAmbresh K .sleepdep_srcs = dma_wkup_sleep_deps,
50311fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
50411fadcfaSAmbresh K };
50511fadcfaSAmbresh K
50611fadcfaSAmbresh K static struct clockdomain rtc_7xx_clkdm = {
50711fadcfaSAmbresh K .name = "rtc_clkdm",
50811fadcfaSAmbresh K .pwrdm = { .name = "rtc_pwrdm" },
50911fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
51011fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
51111fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
51211fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
51311fadcfaSAmbresh K };
51411fadcfaSAmbresh K
51511fadcfaSAmbresh K static struct clockdomain pcie_7xx_clkdm = {
51611fadcfaSAmbresh K .name = "pcie_clkdm",
51711fadcfaSAmbresh K .pwrdm = { .name = "l3init_pwrdm" },
51811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
51911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
52011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
52111fadcfaSAmbresh K .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
52211fadcfaSAmbresh K .wkdep_srcs = pcie_wkup_sleep_deps,
52311fadcfaSAmbresh K .sleepdep_srcs = pcie_wkup_sleep_deps,
5242c949ce3SKishon Vijay Abraham I .flags = CLKDM_CAN_SWSUP,
52511fadcfaSAmbresh K };
52611fadcfaSAmbresh K
52711fadcfaSAmbresh K static struct clockdomain atl_7xx_clkdm = {
52811fadcfaSAmbresh K .name = "atl_clkdm",
52911fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
53011fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
53111fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
53211fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
53311fadcfaSAmbresh K .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
53411fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
53511fadcfaSAmbresh K };
53611fadcfaSAmbresh K
53711fadcfaSAmbresh K static struct clockdomain l3instr_7xx_clkdm = {
53811fadcfaSAmbresh K .name = "l3instr_clkdm",
53911fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
54011fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
54111fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
54211fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
54311fadcfaSAmbresh K };
54411fadcfaSAmbresh K
54511fadcfaSAmbresh K static struct clockdomain dss_7xx_clkdm = {
54611fadcfaSAmbresh K .name = "dss_clkdm",
54711fadcfaSAmbresh K .pwrdm = { .name = "dss_pwrdm" },
54811fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
54911fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_DSS_INST,
55011fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
55111fadcfaSAmbresh K .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
55211fadcfaSAmbresh K .wkdep_srcs = dss_wkup_sleep_deps,
55311fadcfaSAmbresh K .sleepdep_srcs = dss_wkup_sleep_deps,
55411fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
55511fadcfaSAmbresh K };
55611fadcfaSAmbresh K
55711fadcfaSAmbresh K static struct clockdomain emif_7xx_clkdm = {
55811fadcfaSAmbresh K .name = "emif_clkdm",
55911fadcfaSAmbresh K .pwrdm = { .name = "core_pwrdm" },
56011fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
56111fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CORE_INST,
56211fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
56311fadcfaSAmbresh K .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
56411fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
56511fadcfaSAmbresh K };
56611fadcfaSAmbresh K
56711fadcfaSAmbresh K static struct clockdomain emu_7xx_clkdm = {
56811fadcfaSAmbresh K .name = "emu_clkdm",
56911fadcfaSAmbresh K .pwrdm = { .name = "emu_pwrdm" },
57011fadcfaSAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION,
57111fadcfaSAmbresh K .cm_inst = DRA7XX_PRM_EMU_CM_INST,
57211fadcfaSAmbresh K .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
57311fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
57411fadcfaSAmbresh K };
57511fadcfaSAmbresh K
57611fadcfaSAmbresh K static struct clockdomain dsp2_7xx_clkdm = {
57711fadcfaSAmbresh K .name = "dsp2_clkdm",
57811fadcfaSAmbresh K .pwrdm = { .name = "dsp2_pwrdm" },
57911fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
58011fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
58111fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
58211fadcfaSAmbresh K .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
58311fadcfaSAmbresh K .wkdep_srcs = dsp2_wkup_sleep_deps,
58411fadcfaSAmbresh K .sleepdep_srcs = dsp2_wkup_sleep_deps,
58511fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
58611fadcfaSAmbresh K };
58711fadcfaSAmbresh K
58811fadcfaSAmbresh K static struct clockdomain dsp1_7xx_clkdm = {
58911fadcfaSAmbresh K .name = "dsp1_clkdm",
59011fadcfaSAmbresh K .pwrdm = { .name = "dsp1_pwrdm" },
59111fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
59211fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
59311fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
59411fadcfaSAmbresh K .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
59511fadcfaSAmbresh K .wkdep_srcs = dsp1_wkup_sleep_deps,
59611fadcfaSAmbresh K .sleepdep_srcs = dsp1_wkup_sleep_deps,
59711fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
59811fadcfaSAmbresh K };
59911fadcfaSAmbresh K
60011fadcfaSAmbresh K static struct clockdomain cam_7xx_clkdm = {
60111fadcfaSAmbresh K .name = "cam_clkdm",
60211fadcfaSAmbresh K .pwrdm = { .name = "cam_pwrdm" },
60311fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
60411fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_CAM_INST,
60511fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
60611fadcfaSAmbresh K .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
60711fadcfaSAmbresh K .wkdep_srcs = cam_wkup_sleep_deps,
60811fadcfaSAmbresh K .sleepdep_srcs = cam_wkup_sleep_deps,
609*2baee0c5SBenoit Parrot .flags = CLKDM_CAN_SWSUP,
61011fadcfaSAmbresh K };
61111fadcfaSAmbresh K
61211fadcfaSAmbresh K static struct clockdomain l4per_7xx_clkdm = {
61311fadcfaSAmbresh K .name = "l4per_clkdm",
61411fadcfaSAmbresh K .pwrdm = { .name = "l4per_pwrdm" },
61511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
61611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
61711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
61811fadcfaSAmbresh K .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
61911fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
62011fadcfaSAmbresh K };
62111fadcfaSAmbresh K
62211fadcfaSAmbresh K static struct clockdomain gpu_7xx_clkdm = {
62311fadcfaSAmbresh K .name = "gpu_clkdm",
62411fadcfaSAmbresh K .pwrdm = { .name = "gpu_pwrdm" },
62511fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_PARTITION,
62611fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_GPU_INST,
62711fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
62811fadcfaSAmbresh K .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
62911fadcfaSAmbresh K .wkdep_srcs = gpu_wkup_sleep_deps,
63011fadcfaSAmbresh K .sleepdep_srcs = gpu_wkup_sleep_deps,
63111fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
63211fadcfaSAmbresh K };
63311fadcfaSAmbresh K
63411fadcfaSAmbresh K static struct clockdomain eve4_7xx_clkdm = {
63511fadcfaSAmbresh K .name = "eve4_clkdm",
63611fadcfaSAmbresh K .pwrdm = { .name = "eve4_pwrdm" },
63711fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
63811fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
63911fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
64011fadcfaSAmbresh K .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
64111fadcfaSAmbresh K .wkdep_srcs = eve4_wkup_sleep_deps,
64211fadcfaSAmbresh K .sleepdep_srcs = eve4_wkup_sleep_deps,
64311fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
64411fadcfaSAmbresh K };
64511fadcfaSAmbresh K
64611fadcfaSAmbresh K static struct clockdomain eve2_7xx_clkdm = {
64711fadcfaSAmbresh K .name = "eve2_clkdm",
64811fadcfaSAmbresh K .pwrdm = { .name = "eve2_pwrdm" },
64911fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
65011fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
65111fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
65211fadcfaSAmbresh K .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
65311fadcfaSAmbresh K .wkdep_srcs = eve2_wkup_sleep_deps,
65411fadcfaSAmbresh K .sleepdep_srcs = eve2_wkup_sleep_deps,
65511fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
65611fadcfaSAmbresh K };
65711fadcfaSAmbresh K
65811fadcfaSAmbresh K static struct clockdomain eve3_7xx_clkdm = {
65911fadcfaSAmbresh K .name = "eve3_clkdm",
66011fadcfaSAmbresh K .pwrdm = { .name = "eve3_pwrdm" },
66111fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
66211fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
66311fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
66411fadcfaSAmbresh K .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
66511fadcfaSAmbresh K .wkdep_srcs = eve3_wkup_sleep_deps,
66611fadcfaSAmbresh K .sleepdep_srcs = eve3_wkup_sleep_deps,
66711fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
66811fadcfaSAmbresh K };
66911fadcfaSAmbresh K
67011fadcfaSAmbresh K static struct clockdomain wkupaon_7xx_clkdm = {
67111fadcfaSAmbresh K .name = "wkupaon_clkdm",
67211fadcfaSAmbresh K .pwrdm = { .name = "wkupaon_pwrdm" },
67311fadcfaSAmbresh K .prcm_partition = DRA7XX_PRM_PARTITION,
67411fadcfaSAmbresh K .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
67511fadcfaSAmbresh K .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
67611fadcfaSAmbresh K .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
67711fadcfaSAmbresh K .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
67811fadcfaSAmbresh K };
67911fadcfaSAmbresh K
68011fadcfaSAmbresh K static struct clockdomain eve1_7xx_clkdm = {
68111fadcfaSAmbresh K .name = "eve1_clkdm",
68211fadcfaSAmbresh K .pwrdm = { .name = "eve1_pwrdm" },
68311fadcfaSAmbresh K .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
68411fadcfaSAmbresh K .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
68511fadcfaSAmbresh K .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
68611fadcfaSAmbresh K .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
68711fadcfaSAmbresh K .wkdep_srcs = eve1_wkup_sleep_deps,
68811fadcfaSAmbresh K .sleepdep_srcs = eve1_wkup_sleep_deps,
68911fadcfaSAmbresh K .flags = CLKDM_CAN_HWSUP_SWSUP,
69011fadcfaSAmbresh K };
69111fadcfaSAmbresh K
69211fadcfaSAmbresh K /* As clockdomains are added or removed above, this list must also be changed */
69311fadcfaSAmbresh K static struct clockdomain *clockdomains_dra7xx[] __initdata = {
69411fadcfaSAmbresh K &l4per3_7xx_clkdm,
69511fadcfaSAmbresh K &l4per2_7xx_clkdm,
69611fadcfaSAmbresh K &mpu0_7xx_clkdm,
69711fadcfaSAmbresh K &iva_7xx_clkdm,
69811fadcfaSAmbresh K &coreaon_7xx_clkdm,
69911fadcfaSAmbresh K &ipu1_7xx_clkdm,
70011fadcfaSAmbresh K &ipu2_7xx_clkdm,
70111fadcfaSAmbresh K &l3init_7xx_clkdm,
70211fadcfaSAmbresh K &l4sec_7xx_clkdm,
70311fadcfaSAmbresh K &l3main1_7xx_clkdm,
70411fadcfaSAmbresh K &vpe_7xx_clkdm,
70511fadcfaSAmbresh K &mpu_7xx_clkdm,
70611fadcfaSAmbresh K &custefuse_7xx_clkdm,
70711fadcfaSAmbresh K &ipu_7xx_clkdm,
70811fadcfaSAmbresh K &mpu1_7xx_clkdm,
70911fadcfaSAmbresh K &gmac_7xx_clkdm,
71011fadcfaSAmbresh K &l4cfg_7xx_clkdm,
71111fadcfaSAmbresh K &dma_7xx_clkdm,
71211fadcfaSAmbresh K &rtc_7xx_clkdm,
71311fadcfaSAmbresh K &pcie_7xx_clkdm,
71411fadcfaSAmbresh K &atl_7xx_clkdm,
71511fadcfaSAmbresh K &l3instr_7xx_clkdm,
71611fadcfaSAmbresh K &dss_7xx_clkdm,
71711fadcfaSAmbresh K &emif_7xx_clkdm,
71811fadcfaSAmbresh K &emu_7xx_clkdm,
71911fadcfaSAmbresh K &dsp2_7xx_clkdm,
72011fadcfaSAmbresh K &dsp1_7xx_clkdm,
72111fadcfaSAmbresh K &cam_7xx_clkdm,
72211fadcfaSAmbresh K &l4per_7xx_clkdm,
72311fadcfaSAmbresh K &gpu_7xx_clkdm,
72411fadcfaSAmbresh K &eve4_7xx_clkdm,
72511fadcfaSAmbresh K &eve2_7xx_clkdm,
72611fadcfaSAmbresh K &eve3_7xx_clkdm,
72711fadcfaSAmbresh K &wkupaon_7xx_clkdm,
72811fadcfaSAmbresh K &eve1_7xx_clkdm,
72911fadcfaSAmbresh K NULL
73011fadcfaSAmbresh K };
73111fadcfaSAmbresh K
dra7xx_clockdomains_init(void)73211fadcfaSAmbresh K void __init dra7xx_clockdomains_init(void)
73311fadcfaSAmbresh K {
73411fadcfaSAmbresh K clkdm_register_platform_funcs(&omap4_clkdm_operations);
73511fadcfaSAmbresh K clkdm_register_clkdms(clockdomains_dra7xx);
73611fadcfaSAmbresh K clkdm_complete_init();
73711fadcfaSAmbresh K }
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