1f577ffd7STony Lindgren /* 2f30c2269SUwe Zeisberger * linux/arch/arm/mach-omap1/serial.c 3f577ffd7STony Lindgren * 465d873caSMarek Vašut * OMAP1 serial support. 5f577ffd7STony Lindgren * 6f577ffd7STony Lindgren * This program is free software; you can redistribute it and/or modify 7f577ffd7STony Lindgren * it under the terms of the GNU General Public License version 2 as 8f577ffd7STony Lindgren * published by the Free Software Foundation. 9f577ffd7STony Lindgren */ 10f577ffd7STony Lindgren 11f577ffd7STony Lindgren #include <linux/module.h> 12f577ffd7STony Lindgren #include <linux/kernel.h> 13f577ffd7STony Lindgren #include <linux/init.h> 14d533c128SThomas Gleixner #include <linux/irq.h> 15f577ffd7STony Lindgren #include <linux/delay.h> 16f577ffd7STony Lindgren #include <linux/serial.h> 17f577ffd7STony Lindgren #include <linux/tty.h> 18f577ffd7STony Lindgren #include <linux/serial_8250.h> 19f577ffd7STony Lindgren #include <linux/serial_reg.h> 20f8ce2547SRussell King #include <linux/clk.h> 21fced80c7SRussell King #include <linux/io.h> 22f577ffd7STony Lindgren 23f577ffd7STony Lindgren #include <asm/mach-types.h> 24f577ffd7STony Lindgren 25*ce491cf8STony Lindgren #include <plat/board.h> 26*ce491cf8STony Lindgren #include <plat/mux.h> 27a09e64fbSRussell King #include <mach/gpio.h> 28*ce491cf8STony Lindgren #include <plat/fpga.h> 29f577ffd7STony Lindgren 30120db2cbSTony Lindgren static struct clk * uart1_ck; 31120db2cbSTony Lindgren static struct clk * uart2_ck; 32120db2cbSTony Lindgren static struct clk * uart3_ck; 33f577ffd7STony Lindgren 34f577ffd7STony Lindgren static inline unsigned int omap_serial_in(struct plat_serial8250_port *up, 35f577ffd7STony Lindgren int offset) 36f577ffd7STony Lindgren { 37f577ffd7STony Lindgren offset <<= up->regshift; 38f577ffd7STony Lindgren return (unsigned int)__raw_readb(up->membase + offset); 39f577ffd7STony Lindgren } 40f577ffd7STony Lindgren 41f577ffd7STony Lindgren static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset, 42f577ffd7STony Lindgren int value) 43f577ffd7STony Lindgren { 44f577ffd7STony Lindgren offset <<= p->regshift; 45f577ffd7STony Lindgren __raw_writeb(value, p->membase + offset); 46f577ffd7STony Lindgren } 47f577ffd7STony Lindgren 48f577ffd7STony Lindgren /* 49f577ffd7STony Lindgren * Internal UARTs need to be initialized for the 8250 autoconfig to work 50f577ffd7STony Lindgren * properly. Note that the TX watermark initialization may not be needed 51f577ffd7STony Lindgren * once the 8250.c watermark handling code is merged. 52f577ffd7STony Lindgren */ 53f577ffd7STony Lindgren static void __init omap_serial_reset(struct plat_serial8250_port *p) 54f577ffd7STony Lindgren { 55f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ 56f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ 57f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ 58f577ffd7STony Lindgren 5965d873caSMarek Vašut if (!cpu_is_omap15xx()) { 60f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_SYSC, 0x01); 61f577ffd7STony Lindgren while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01)); 62f577ffd7STony Lindgren } 63f577ffd7STony Lindgren } 64f577ffd7STony Lindgren 65f577ffd7STony Lindgren static struct plat_serial8250_port serial_platform_data[] = { 66f577ffd7STony Lindgren { 67e8a91c95SRussell King .mapbase = OMAP_UART1_BASE, 68f577ffd7STony Lindgren .irq = INT_UART1, 69f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 70f577ffd7STony Lindgren .iotype = UPIO_MEM, 71f577ffd7STony Lindgren .regshift = 2, 72f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 73f577ffd7STony Lindgren }, 74f577ffd7STony Lindgren { 75e8a91c95SRussell King .mapbase = OMAP_UART2_BASE, 76f577ffd7STony Lindgren .irq = INT_UART2, 77f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 78f577ffd7STony Lindgren .iotype = UPIO_MEM, 79f577ffd7STony Lindgren .regshift = 2, 80f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 81f577ffd7STony Lindgren }, 82f577ffd7STony Lindgren { 83e8a91c95SRussell King .mapbase = OMAP_UART3_BASE, 84f577ffd7STony Lindgren .irq = INT_UART3, 85f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 86f577ffd7STony Lindgren .iotype = UPIO_MEM, 87f577ffd7STony Lindgren .regshift = 2, 88f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 89f577ffd7STony Lindgren }, 90f577ffd7STony Lindgren { }, 91f577ffd7STony Lindgren }; 92f577ffd7STony Lindgren 93f577ffd7STony Lindgren static struct platform_device serial_device = { 94f577ffd7STony Lindgren .name = "serial8250", 956df29debSRussell King .id = PLAT8250_DEV_PLATFORM, 96f577ffd7STony Lindgren .dev = { 97f577ffd7STony Lindgren .platform_data = serial_platform_data, 98f577ffd7STony Lindgren }, 99f577ffd7STony Lindgren }; 100f577ffd7STony Lindgren 101f577ffd7STony Lindgren /* 102f577ffd7STony Lindgren * Note that on Innovator-1510 UART2 pins conflict with USB2. 103f577ffd7STony Lindgren * By default UART2 does not work on Innovator-1510 if you have 104f577ffd7STony Lindgren * USB OHCI enabled. To use UART2, you must disable USB2 first. 105f577ffd7STony Lindgren */ 1063179a019STony Lindgren void __init omap_serial_init(void) 107f577ffd7STony Lindgren { 108f577ffd7STony Lindgren int i; 109f577ffd7STony Lindgren 110d8723ae2SAlistair Buxton if (cpu_is_omap7xx()) { 111f577ffd7STony Lindgren serial_platform_data[0].regshift = 0; 112f577ffd7STony Lindgren serial_platform_data[1].regshift = 0; 113372b1c32SAlistair Buxton serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; 114372b1c32SAlistair Buxton serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; 115f577ffd7STony Lindgren } 116f577ffd7STony Lindgren 11765d873caSMarek Vašut if (cpu_is_omap15xx()) { 118f577ffd7STony Lindgren serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; 119f577ffd7STony Lindgren serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; 120f577ffd7STony Lindgren serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; 121f577ffd7STony Lindgren } 122f577ffd7STony Lindgren 123f577ffd7STony Lindgren for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 124f577ffd7STony Lindgren unsigned char reg; 125f577ffd7STony Lindgren 12684f90c9cSTony Lindgren /* Static mapping, never released */ 12784f90c9cSTony Lindgren serial_platform_data[i].membase = 12884f90c9cSTony Lindgren ioremap(serial_platform_data[i].mapbase, SZ_2K); 12984f90c9cSTony Lindgren if (!serial_platform_data[i].membase) { 13084f90c9cSTony Lindgren printk(KERN_ERR "Could not ioremap uart%i\n", i); 13184f90c9cSTony Lindgren continue; 13284f90c9cSTony Lindgren } 13384f90c9cSTony Lindgren 134f577ffd7STony Lindgren switch (i) { 135f577ffd7STony Lindgren case 0: 136f577ffd7STony Lindgren uart1_ck = clk_get(NULL, "uart1_ck"); 137f577ffd7STony Lindgren if (IS_ERR(uart1_ck)) 138f577ffd7STony Lindgren printk("Could not get uart1_ck\n"); 139f577ffd7STony Lindgren else { 14030ff720bSTony Lindgren clk_enable(uart1_ck); 14165d873caSMarek Vašut if (cpu_is_omap15xx()) 142f577ffd7STony Lindgren clk_set_rate(uart1_ck, 12000000); 143f577ffd7STony Lindgren } 14465d873caSMarek Vašut if (cpu_is_omap15xx()) { 145f577ffd7STony Lindgren omap_cfg_reg(UART1_TX); 146f577ffd7STony Lindgren omap_cfg_reg(UART1_RTS); 147f577ffd7STony Lindgren if (machine_is_omap_innovator()) { 148f577ffd7STony Lindgren reg = fpga_read(OMAP1510_FPGA_POWER); 149f577ffd7STony Lindgren reg |= OMAP1510_FPGA_PCR_COM1_EN; 150f577ffd7STony Lindgren fpga_write(reg, OMAP1510_FPGA_POWER); 151f577ffd7STony Lindgren udelay(10); 152f577ffd7STony Lindgren } 153f577ffd7STony Lindgren } 154f577ffd7STony Lindgren break; 155f577ffd7STony Lindgren case 1: 156f577ffd7STony Lindgren uart2_ck = clk_get(NULL, "uart2_ck"); 157f577ffd7STony Lindgren if (IS_ERR(uart2_ck)) 158f577ffd7STony Lindgren printk("Could not get uart2_ck\n"); 159f577ffd7STony Lindgren else { 16030ff720bSTony Lindgren clk_enable(uart2_ck); 16165d873caSMarek Vašut if (cpu_is_omap15xx()) 162f577ffd7STony Lindgren clk_set_rate(uart2_ck, 12000000); 163f577ffd7STony Lindgren else 164f577ffd7STony Lindgren clk_set_rate(uart2_ck, 48000000); 165f577ffd7STony Lindgren } 16665d873caSMarek Vašut if (cpu_is_omap15xx()) { 167f577ffd7STony Lindgren omap_cfg_reg(UART2_TX); 168f577ffd7STony Lindgren omap_cfg_reg(UART2_RTS); 169f577ffd7STony Lindgren if (machine_is_omap_innovator()) { 170f577ffd7STony Lindgren reg = fpga_read(OMAP1510_FPGA_POWER); 171f577ffd7STony Lindgren reg |= OMAP1510_FPGA_PCR_COM2_EN; 172f577ffd7STony Lindgren fpga_write(reg, OMAP1510_FPGA_POWER); 173f577ffd7STony Lindgren udelay(10); 174f577ffd7STony Lindgren } 175f577ffd7STony Lindgren } 176f577ffd7STony Lindgren break; 177f577ffd7STony Lindgren case 2: 178f577ffd7STony Lindgren uart3_ck = clk_get(NULL, "uart3_ck"); 179f577ffd7STony Lindgren if (IS_ERR(uart3_ck)) 180f577ffd7STony Lindgren printk("Could not get uart3_ck\n"); 181f577ffd7STony Lindgren else { 18230ff720bSTony Lindgren clk_enable(uart3_ck); 18365d873caSMarek Vašut if (cpu_is_omap15xx()) 184f577ffd7STony Lindgren clk_set_rate(uart3_ck, 12000000); 185f577ffd7STony Lindgren } 18665d873caSMarek Vašut if (cpu_is_omap15xx()) { 187f577ffd7STony Lindgren omap_cfg_reg(UART3_TX); 188f577ffd7STony Lindgren omap_cfg_reg(UART3_RX); 189f577ffd7STony Lindgren } 190f577ffd7STony Lindgren break; 191f577ffd7STony Lindgren } 192f577ffd7STony Lindgren omap_serial_reset(&serial_platform_data[i]); 193f577ffd7STony Lindgren } 194f577ffd7STony Lindgren } 195f577ffd7STony Lindgren 1967c38cf02STony Lindgren #ifdef CONFIG_OMAP_SERIAL_WAKE 1977c38cf02STony Lindgren 1980cd61b68SLinus Torvalds static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id) 1997c38cf02STony Lindgren { 2007c38cf02STony Lindgren /* Need to do something with serial port right after wake-up? */ 2017c38cf02STony Lindgren return IRQ_HANDLED; 2027c38cf02STony Lindgren } 2037c38cf02STony Lindgren 2047c38cf02STony Lindgren /* 2057c38cf02STony Lindgren * Reroutes serial RX lines to GPIO lines for the duration of 2067c38cf02STony Lindgren * sleep to allow waking up the device from serial port even 2077c38cf02STony Lindgren * in deep sleep. 2087c38cf02STony Lindgren */ 2097c38cf02STony Lindgren void omap_serial_wake_trigger(int enable) 2107c38cf02STony Lindgren { 2117c38cf02STony Lindgren if (!cpu_is_omap16xx()) 2127c38cf02STony Lindgren return; 2137c38cf02STony Lindgren 2147c38cf02STony Lindgren if (uart1_ck != NULL) { 2157c38cf02STony Lindgren if (enable) 2167c38cf02STony Lindgren omap_cfg_reg(V14_16XX_GPIO37); 2177c38cf02STony Lindgren else 2187c38cf02STony Lindgren omap_cfg_reg(V14_16XX_UART1_RX); 2197c38cf02STony Lindgren } 2207c38cf02STony Lindgren if (uart2_ck != NULL) { 2217c38cf02STony Lindgren if (enable) 2227c38cf02STony Lindgren omap_cfg_reg(R9_16XX_GPIO18); 2237c38cf02STony Lindgren else 2247c38cf02STony Lindgren omap_cfg_reg(R9_16XX_UART2_RX); 2257c38cf02STony Lindgren } 2267c38cf02STony Lindgren if (uart3_ck != NULL) { 2277c38cf02STony Lindgren if (enable) 2287c38cf02STony Lindgren omap_cfg_reg(L14_16XX_GPIO49); 2297c38cf02STony Lindgren else 2307c38cf02STony Lindgren omap_cfg_reg(L14_16XX_UART3_RX); 2317c38cf02STony Lindgren } 2327c38cf02STony Lindgren } 2337c38cf02STony Lindgren 2347c38cf02STony Lindgren static void __init omap_serial_set_port_wakeup(int gpio_nr) 2357c38cf02STony Lindgren { 2367c38cf02STony Lindgren int ret; 2377c38cf02STony Lindgren 238f2d18feaSJarkko Nikula ret = gpio_request(gpio_nr, "UART wake"); 2397c38cf02STony Lindgren if (ret < 0) { 2407c38cf02STony Lindgren printk(KERN_ERR "Could not request UART wake GPIO: %i\n", 2417c38cf02STony Lindgren gpio_nr); 2427c38cf02STony Lindgren return; 2437c38cf02STony Lindgren } 24440e3925bSDavid Brownell gpio_direction_input(gpio_nr); 24515f74b03SDavid Brownell ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt, 24652e405eaSThomas Gleixner IRQF_TRIGGER_RISING, "serial wakeup", NULL); 2477c38cf02STony Lindgren if (ret) { 248f2d18feaSJarkko Nikula gpio_free(gpio_nr); 2497c38cf02STony Lindgren printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", 2507c38cf02STony Lindgren gpio_nr); 2517c38cf02STony Lindgren return; 2527c38cf02STony Lindgren } 25315f74b03SDavid Brownell enable_irq_wake(gpio_to_irq(gpio_nr)); 2547c38cf02STony Lindgren } 2557c38cf02STony Lindgren 2567c38cf02STony Lindgren static int __init omap_serial_wakeup_init(void) 2577c38cf02STony Lindgren { 2587c38cf02STony Lindgren if (!cpu_is_omap16xx()) 2597c38cf02STony Lindgren return 0; 2607c38cf02STony Lindgren 2617c38cf02STony Lindgren if (uart1_ck != NULL) 2627c38cf02STony Lindgren omap_serial_set_port_wakeup(37); 2637c38cf02STony Lindgren if (uart2_ck != NULL) 2647c38cf02STony Lindgren omap_serial_set_port_wakeup(18); 2657c38cf02STony Lindgren if (uart3_ck != NULL) 2667c38cf02STony Lindgren omap_serial_set_port_wakeup(49); 2677c38cf02STony Lindgren 2687c38cf02STony Lindgren return 0; 2697c38cf02STony Lindgren } 2707c38cf02STony Lindgren late_initcall(omap_serial_wakeup_init); 2717c38cf02STony Lindgren 2727c38cf02STony Lindgren #endif /* CONFIG_OMAP_SERIAL_WAKE */ 2737c38cf02STony Lindgren 274f577ffd7STony Lindgren static int __init omap_init(void) 275f577ffd7STony Lindgren { 276f577ffd7STony Lindgren return platform_device_register(&serial_device); 277f577ffd7STony Lindgren } 278f577ffd7STony Lindgren arch_initcall(omap_init); 279