1f577ffd7STony Lindgren /* 2f30c2269SUwe Zeisberger * linux/arch/arm/mach-omap1/serial.c 3f577ffd7STony Lindgren * 465d873caSMarek Vašut * OMAP1 serial support. 5f577ffd7STony Lindgren * 6f577ffd7STony Lindgren * This program is free software; you can redistribute it and/or modify 7f577ffd7STony Lindgren * it under the terms of the GNU General Public License version 2 as 8f577ffd7STony Lindgren * published by the Free Software Foundation. 9f577ffd7STony Lindgren */ 10f577ffd7STony Lindgren 11f577ffd7STony Lindgren #include <linux/module.h> 12f577ffd7STony Lindgren #include <linux/kernel.h> 13f577ffd7STony Lindgren #include <linux/init.h> 14d533c128SThomas Gleixner #include <linux/irq.h> 15f577ffd7STony Lindgren #include <linux/delay.h> 16f577ffd7STony Lindgren #include <linux/serial.h> 17f577ffd7STony Lindgren #include <linux/tty.h> 18f577ffd7STony Lindgren #include <linux/serial_8250.h> 19f577ffd7STony Lindgren #include <linux/serial_reg.h> 20f8ce2547SRussell King #include <linux/clk.h> 21fced80c7SRussell King #include <linux/io.h> 22f577ffd7STony Lindgren 23f577ffd7STony Lindgren #include <asm/mach-types.h> 24f577ffd7STony Lindgren 25a09e64fbSRussell King #include <mach/board.h> 26a09e64fbSRussell King #include <mach/mux.h> 27a09e64fbSRussell King #include <mach/gpio.h> 28a09e64fbSRussell King #include <mach/fpga.h> 297c38cf02STony Lindgren #ifdef CONFIG_PM 30a09e64fbSRussell King #include <mach/pm.h> 317c38cf02STony Lindgren #endif 32f577ffd7STony Lindgren 33120db2cbSTony Lindgren static struct clk * uart1_ck; 34120db2cbSTony Lindgren static struct clk * uart2_ck; 35120db2cbSTony Lindgren static struct clk * uart3_ck; 36f577ffd7STony Lindgren 37f577ffd7STony Lindgren static inline unsigned int omap_serial_in(struct plat_serial8250_port *up, 38f577ffd7STony Lindgren int offset) 39f577ffd7STony Lindgren { 40f577ffd7STony Lindgren offset <<= up->regshift; 41f577ffd7STony Lindgren return (unsigned int)__raw_readb(up->membase + offset); 42f577ffd7STony Lindgren } 43f577ffd7STony Lindgren 44f577ffd7STony Lindgren static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset, 45f577ffd7STony Lindgren int value) 46f577ffd7STony Lindgren { 47f577ffd7STony Lindgren offset <<= p->regshift; 48f577ffd7STony Lindgren __raw_writeb(value, p->membase + offset); 49f577ffd7STony Lindgren } 50f577ffd7STony Lindgren 51f577ffd7STony Lindgren /* 52f577ffd7STony Lindgren * Internal UARTs need to be initialized for the 8250 autoconfig to work 53f577ffd7STony Lindgren * properly. Note that the TX watermark initialization may not be needed 54f577ffd7STony Lindgren * once the 8250.c watermark handling code is merged. 55f577ffd7STony Lindgren */ 56f577ffd7STony Lindgren static void __init omap_serial_reset(struct plat_serial8250_port *p) 57f577ffd7STony Lindgren { 58f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ 59f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ 60f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ 61f577ffd7STony Lindgren 6265d873caSMarek Vašut if (!cpu_is_omap15xx()) { 63f577ffd7STony Lindgren omap_serial_outp(p, UART_OMAP_SYSC, 0x01); 64f577ffd7STony Lindgren while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01)); 65f577ffd7STony Lindgren } 66f577ffd7STony Lindgren } 67f577ffd7STony Lindgren 68f577ffd7STony Lindgren static struct plat_serial8250_port serial_platform_data[] = { 69f577ffd7STony Lindgren { 70e8a91c95SRussell King .membase = IO_ADDRESS(OMAP_UART1_BASE), 71e8a91c95SRussell King .mapbase = OMAP_UART1_BASE, 72f577ffd7STony Lindgren .irq = INT_UART1, 73f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 74f577ffd7STony Lindgren .iotype = UPIO_MEM, 75f577ffd7STony Lindgren .regshift = 2, 76f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 77f577ffd7STony Lindgren }, 78f577ffd7STony Lindgren { 79e8a91c95SRussell King .membase = IO_ADDRESS(OMAP_UART2_BASE), 80e8a91c95SRussell King .mapbase = OMAP_UART2_BASE, 81f577ffd7STony Lindgren .irq = INT_UART2, 82f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 83f577ffd7STony Lindgren .iotype = UPIO_MEM, 84f577ffd7STony Lindgren .regshift = 2, 85f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 86f577ffd7STony Lindgren }, 87f577ffd7STony Lindgren { 88e8a91c95SRussell King .membase = IO_ADDRESS(OMAP_UART3_BASE), 89e8a91c95SRussell King .mapbase = OMAP_UART3_BASE, 90f577ffd7STony Lindgren .irq = INT_UART3, 91f577ffd7STony Lindgren .flags = UPF_BOOT_AUTOCONF, 92f577ffd7STony Lindgren .iotype = UPIO_MEM, 93f577ffd7STony Lindgren .regshift = 2, 94f577ffd7STony Lindgren .uartclk = OMAP16XX_BASE_BAUD * 16, 95f577ffd7STony Lindgren }, 96f577ffd7STony Lindgren { }, 97f577ffd7STony Lindgren }; 98f577ffd7STony Lindgren 99f577ffd7STony Lindgren static struct platform_device serial_device = { 100f577ffd7STony Lindgren .name = "serial8250", 1016df29debSRussell King .id = PLAT8250_DEV_PLATFORM, 102f577ffd7STony Lindgren .dev = { 103f577ffd7STony Lindgren .platform_data = serial_platform_data, 104f577ffd7STony Lindgren }, 105f577ffd7STony Lindgren }; 106f577ffd7STony Lindgren 107f577ffd7STony Lindgren /* 108f577ffd7STony Lindgren * Note that on Innovator-1510 UART2 pins conflict with USB2. 109f577ffd7STony Lindgren * By default UART2 does not work on Innovator-1510 if you have 110f577ffd7STony Lindgren * USB OHCI enabled. To use UART2, you must disable USB2 first. 111f577ffd7STony Lindgren */ 1123179a019STony Lindgren void __init omap_serial_init(void) 113f577ffd7STony Lindgren { 114f577ffd7STony Lindgren int i; 1153179a019STony Lindgren const struct omap_uart_config *info; 116f577ffd7STony Lindgren 117f577ffd7STony Lindgren if (cpu_is_omap730()) { 118f577ffd7STony Lindgren serial_platform_data[0].regshift = 0; 119f577ffd7STony Lindgren serial_platform_data[1].regshift = 0; 120f577ffd7STony Lindgren serial_platform_data[0].irq = INT_730_UART_MODEM_1; 121f577ffd7STony Lindgren serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; 122f577ffd7STony Lindgren } 123f577ffd7STony Lindgren 124*56739a69SZebediah C. McClure if (cpu_is_omap850()) { 125*56739a69SZebediah C. McClure serial_platform_data[0].regshift = 0; 126*56739a69SZebediah C. McClure serial_platform_data[1].regshift = 0; 127*56739a69SZebediah C. McClure serial_platform_data[0].irq = INT_850_UART_MODEM_1; 128*56739a69SZebediah C. McClure serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; 129*56739a69SZebediah C. McClure } 130*56739a69SZebediah C. McClure 13165d873caSMarek Vašut if (cpu_is_omap15xx()) { 132f577ffd7STony Lindgren serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; 133f577ffd7STony Lindgren serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; 134f577ffd7STony Lindgren serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; 135f577ffd7STony Lindgren } 136f577ffd7STony Lindgren 1373179a019STony Lindgren info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); 1383179a019STony Lindgren if (info == NULL) 1393179a019STony Lindgren return; 1403179a019STony Lindgren 141f577ffd7STony Lindgren for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 142f577ffd7STony Lindgren unsigned char reg; 143f577ffd7STony Lindgren 1443179a019STony Lindgren if (!((1 << i) & info->enabled_uarts)) { 145f577ffd7STony Lindgren serial_platform_data[i].membase = NULL; 146f577ffd7STony Lindgren serial_platform_data[i].mapbase = 0; 147f577ffd7STony Lindgren continue; 148f577ffd7STony Lindgren } 149f577ffd7STony Lindgren 150f577ffd7STony Lindgren switch (i) { 151f577ffd7STony Lindgren case 0: 152f577ffd7STony Lindgren uart1_ck = clk_get(NULL, "uart1_ck"); 153f577ffd7STony Lindgren if (IS_ERR(uart1_ck)) 154f577ffd7STony Lindgren printk("Could not get uart1_ck\n"); 155f577ffd7STony Lindgren else { 15630ff720bSTony Lindgren clk_enable(uart1_ck); 15765d873caSMarek Vašut if (cpu_is_omap15xx()) 158f577ffd7STony Lindgren clk_set_rate(uart1_ck, 12000000); 159f577ffd7STony Lindgren } 16065d873caSMarek Vašut if (cpu_is_omap15xx()) { 161f577ffd7STony Lindgren omap_cfg_reg(UART1_TX); 162f577ffd7STony Lindgren omap_cfg_reg(UART1_RTS); 163f577ffd7STony Lindgren if (machine_is_omap_innovator()) { 164f577ffd7STony Lindgren reg = fpga_read(OMAP1510_FPGA_POWER); 165f577ffd7STony Lindgren reg |= OMAP1510_FPGA_PCR_COM1_EN; 166f577ffd7STony Lindgren fpga_write(reg, OMAP1510_FPGA_POWER); 167f577ffd7STony Lindgren udelay(10); 168f577ffd7STony Lindgren } 169f577ffd7STony Lindgren } 170f577ffd7STony Lindgren break; 171f577ffd7STony Lindgren case 1: 172f577ffd7STony Lindgren uart2_ck = clk_get(NULL, "uart2_ck"); 173f577ffd7STony Lindgren if (IS_ERR(uart2_ck)) 174f577ffd7STony Lindgren printk("Could not get uart2_ck\n"); 175f577ffd7STony Lindgren else { 17630ff720bSTony Lindgren clk_enable(uart2_ck); 17765d873caSMarek Vašut if (cpu_is_omap15xx()) 178f577ffd7STony Lindgren clk_set_rate(uart2_ck, 12000000); 179f577ffd7STony Lindgren else 180f577ffd7STony Lindgren clk_set_rate(uart2_ck, 48000000); 181f577ffd7STony Lindgren } 18265d873caSMarek Vašut if (cpu_is_omap15xx()) { 183f577ffd7STony Lindgren omap_cfg_reg(UART2_TX); 184f577ffd7STony Lindgren omap_cfg_reg(UART2_RTS); 185f577ffd7STony Lindgren if (machine_is_omap_innovator()) { 186f577ffd7STony Lindgren reg = fpga_read(OMAP1510_FPGA_POWER); 187f577ffd7STony Lindgren reg |= OMAP1510_FPGA_PCR_COM2_EN; 188f577ffd7STony Lindgren fpga_write(reg, OMAP1510_FPGA_POWER); 189f577ffd7STony Lindgren udelay(10); 190f577ffd7STony Lindgren } 191f577ffd7STony Lindgren } 192f577ffd7STony Lindgren break; 193f577ffd7STony Lindgren case 2: 194f577ffd7STony Lindgren uart3_ck = clk_get(NULL, "uart3_ck"); 195f577ffd7STony Lindgren if (IS_ERR(uart3_ck)) 196f577ffd7STony Lindgren printk("Could not get uart3_ck\n"); 197f577ffd7STony Lindgren else { 19830ff720bSTony Lindgren clk_enable(uart3_ck); 19965d873caSMarek Vašut if (cpu_is_omap15xx()) 200f577ffd7STony Lindgren clk_set_rate(uart3_ck, 12000000); 201f577ffd7STony Lindgren } 20265d873caSMarek Vašut if (cpu_is_omap15xx()) { 203f577ffd7STony Lindgren omap_cfg_reg(UART3_TX); 204f577ffd7STony Lindgren omap_cfg_reg(UART3_RX); 205f577ffd7STony Lindgren } 206f577ffd7STony Lindgren break; 207f577ffd7STony Lindgren } 208f577ffd7STony Lindgren omap_serial_reset(&serial_platform_data[i]); 209f577ffd7STony Lindgren } 210f577ffd7STony Lindgren } 211f577ffd7STony Lindgren 2127c38cf02STony Lindgren #ifdef CONFIG_OMAP_SERIAL_WAKE 2137c38cf02STony Lindgren 2140cd61b68SLinus Torvalds static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id) 2157c38cf02STony Lindgren { 2167c38cf02STony Lindgren /* Need to do something with serial port right after wake-up? */ 2177c38cf02STony Lindgren return IRQ_HANDLED; 2187c38cf02STony Lindgren } 2197c38cf02STony Lindgren 2207c38cf02STony Lindgren /* 2217c38cf02STony Lindgren * Reroutes serial RX lines to GPIO lines for the duration of 2227c38cf02STony Lindgren * sleep to allow waking up the device from serial port even 2237c38cf02STony Lindgren * in deep sleep. 2247c38cf02STony Lindgren */ 2257c38cf02STony Lindgren void omap_serial_wake_trigger(int enable) 2267c38cf02STony Lindgren { 2277c38cf02STony Lindgren if (!cpu_is_omap16xx()) 2287c38cf02STony Lindgren return; 2297c38cf02STony Lindgren 2307c38cf02STony Lindgren if (uart1_ck != NULL) { 2317c38cf02STony Lindgren if (enable) 2327c38cf02STony Lindgren omap_cfg_reg(V14_16XX_GPIO37); 2337c38cf02STony Lindgren else 2347c38cf02STony Lindgren omap_cfg_reg(V14_16XX_UART1_RX); 2357c38cf02STony Lindgren } 2367c38cf02STony Lindgren if (uart2_ck != NULL) { 2377c38cf02STony Lindgren if (enable) 2387c38cf02STony Lindgren omap_cfg_reg(R9_16XX_GPIO18); 2397c38cf02STony Lindgren else 2407c38cf02STony Lindgren omap_cfg_reg(R9_16XX_UART2_RX); 2417c38cf02STony Lindgren } 2427c38cf02STony Lindgren if (uart3_ck != NULL) { 2437c38cf02STony Lindgren if (enable) 2447c38cf02STony Lindgren omap_cfg_reg(L14_16XX_GPIO49); 2457c38cf02STony Lindgren else 2467c38cf02STony Lindgren omap_cfg_reg(L14_16XX_UART3_RX); 2477c38cf02STony Lindgren } 2487c38cf02STony Lindgren } 2497c38cf02STony Lindgren 2507c38cf02STony Lindgren static void __init omap_serial_set_port_wakeup(int gpio_nr) 2517c38cf02STony Lindgren { 2527c38cf02STony Lindgren int ret; 2537c38cf02STony Lindgren 254f2d18feaSJarkko Nikula ret = gpio_request(gpio_nr, "UART wake"); 2557c38cf02STony Lindgren if (ret < 0) { 2567c38cf02STony Lindgren printk(KERN_ERR "Could not request UART wake GPIO: %i\n", 2577c38cf02STony Lindgren gpio_nr); 2587c38cf02STony Lindgren return; 2597c38cf02STony Lindgren } 26040e3925bSDavid Brownell gpio_direction_input(gpio_nr); 26115f74b03SDavid Brownell ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt, 26252e405eaSThomas Gleixner IRQF_TRIGGER_RISING, "serial wakeup", NULL); 2637c38cf02STony Lindgren if (ret) { 264f2d18feaSJarkko Nikula gpio_free(gpio_nr); 2657c38cf02STony Lindgren printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n", 2667c38cf02STony Lindgren gpio_nr); 2677c38cf02STony Lindgren return; 2687c38cf02STony Lindgren } 26915f74b03SDavid Brownell enable_irq_wake(gpio_to_irq(gpio_nr)); 2707c38cf02STony Lindgren } 2717c38cf02STony Lindgren 2727c38cf02STony Lindgren static int __init omap_serial_wakeup_init(void) 2737c38cf02STony Lindgren { 2747c38cf02STony Lindgren if (!cpu_is_omap16xx()) 2757c38cf02STony Lindgren return 0; 2767c38cf02STony Lindgren 2777c38cf02STony Lindgren if (uart1_ck != NULL) 2787c38cf02STony Lindgren omap_serial_set_port_wakeup(37); 2797c38cf02STony Lindgren if (uart2_ck != NULL) 2807c38cf02STony Lindgren omap_serial_set_port_wakeup(18); 2817c38cf02STony Lindgren if (uart3_ck != NULL) 2827c38cf02STony Lindgren omap_serial_set_port_wakeup(49); 2837c38cf02STony Lindgren 2847c38cf02STony Lindgren return 0; 2857c38cf02STony Lindgren } 2867c38cf02STony Lindgren late_initcall(omap_serial_wakeup_init); 2877c38cf02STony Lindgren 2887c38cf02STony Lindgren #endif /* CONFIG_OMAP_SERIAL_WAKE */ 2897c38cf02STony Lindgren 290f577ffd7STony Lindgren static int __init omap_init(void) 291f577ffd7STony Lindgren { 292f577ffd7STony Lindgren return platform_device_register(&serial_device); 293f577ffd7STony Lindgren } 294f577ffd7STony Lindgren arch_initcall(omap_init); 295